Public Version
IVA2.2 Subsystem Functional Description
www.ti.com
5.3.2 DMA Engines
5.3.2.1
EDMA
The IVA2.2 subsystem has an EDMA to transfer instructions and data from/to any external memory
connected to the L3 interconnect to/from the DSP megamodule L1D and L2 and, potentially, L1P (if not
configured as full cache) local memories. The EDMA can also perform transfers from external memory to
external memory and from DSP megamodule internal memory to DSP megamodule internal memory, with
some performance loss caused by resource sharing between the read and write ports. For DSP
megamodule internal memory to internal memory, use the IDMA.
For the IDMA functional description and a description of IDMA relative programming, see
,
IDMA, and
, Internal Memory-to-Memory Transfer (IDMA), respectively.
The EDMA is based on two primary components:
•
Third-party DMA channel controller (TPCC)
•
Third-party DMA transfer controller (TPTC)
There are two instances of the TPTC in the IVA2.2 subsystem.
shows how the EDMA is integrated in the IVA2.2 subsystem:
•
Code running on the DSP can configure the EDMA; through the DSP megamodule configuration port
and the local interconnect, the code can program DMA transfers and software-trigger them by writing
to the TPCC configuration registers.
•
Preprogrammed DMA transfers can be triggered by external events, referred to in this chapter as DMA
requests.
•
The TPCC schedules DMA transfers to the TPTC DMA engines (TPTC0 and TPTC1) through
dedicated local interconnect 32-bit configuration ports.
•
Each TPTC issues concurrent traffic on the local interconnect through dedicated read and write 64-bit
ports.
•
Interrupts generated by the EDMA are routed to the DSP INTC.
•
Power-management handshakes are exchanged between EDMA components and the SYSC module.
716
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
