Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
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Table 5-271. Register Call Summary for Register TPCC_ESRH
IVA2.2 Subsystem Functional Description
• EDMA : [0] [1]
IVA2.2 Subsystem Basic Programming Model
• Starting the Transfer : [2]
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [3]
Table 5-272. TPCC_CER
Address Offset 0x1018
Physical address 0x01C0 1018 Instance IVA2.2 TPCC
Description Chained Event Register:
If CER.En bit is set (regardless of state of EER.En), then the corresponding DMA channel is prioritized vs. other
pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned
from one of the TPTCs through the completion interface, or is generated internally through Early Completion path.
CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set
and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event
Missed Register is set. CER.En cannot be set or cleared through software.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10
Bits Field Name Description Type Reset
31 E31 Event #31 R 0
30 E30 Event #30 R 0
29 E29 Event #29 R 0
28 E28 Event #28 R 0
27 E27 Event #27 R 0
26 E26 Event #26 R 0
25 E25 Event #25 R 0
24 E24 Event #24 R 0
23 E23 Event #23 R 0
22 E22 Event #22 R 0
21 E21 Event #21 R 0
20 E20 Event #20 R 0
19 E19 Event #19 R 0
18 E18 Event #18 R 0
17 E17 Event #17 R 0
16 E16 Event #16 R 0
15 E15 Event #15 R 0
14 E14 Event #14 R 0
13 E13 Event #13 R 0
12 E12 Event #12 R 0
11 E11 Event #11 R 0
10 E10 Event #10 R 0
9 E9 Event #9 R 0
8 E8 Event #8 R 0
7 E7 Event #7 R 0
6 E6 Event #6 R 0
5 E5 Event #5 R 0
898 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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