Requestor
Camera MMU
Resources
(memory, peripherals)
V
irtualaddress
Physicaladdress
Physicaladdress
Data
Data
Data
L4-Coreinterconnect
Configuration
L3 interconnect
Camera subsystem
MMU-002
Requestor
IVA2.2 MMU
Resources
(memory, peripherals)
V
irtualaddress
Physicaladdress
Physicaladdress
Data
Data
Data
Configuration
L3 interconnect
Image Video and Audio
accelerator
MMU-003
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MMU Integration
15.2 MMU Integration
The MMU communicates accesses from the requestor (either the the camera subsystem or the IVA2.2) to
the L3 main interconnect, performing virtual to physical address translation. The camera MMU is
programmed through the L4-core interconnect. The IVA2.2 MMU is programmed through the L3
interconnect. Both MMU error conditions are signaled as interrupts to the system master processor (that
is, the MPU).
and
show the system integration of the camera MMU instance and the IVA2.2
MMU instance.
Figure 15-2. Camera MMU System Integration
Figure 15-3. IVA2.2 MMU System Integration
15.2.1 Clock Domains
The camera MMU instance has two clock domains: the functional clock domain for the MMU, which is
synchronous to the L3 interconnect clock, and the L4 interconnect clock, which is used to configure the
MMU instance. Both camera MMU clocks are derived from a common reference clock generated by the
power reset and clock management (PRCM) module.
2665
SWPU177N – December 2009 – Revised November 2010
Memory Management Units
Copyright © 2009–2010, Texas Instruments Incorporated
