Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Bits Field Name Description Type Reset
3 E3 Event #3 W 0
2 E2 Event #2 W 0
1 E1 Event #1 W 0
0 E0 Event #0 W 0
Table 5-379. Register Call Summary for Register TPCC_QEECR_Rn
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
Table 5-380. TPCC_QEESR_Rn
Address Offset (0x200*n) n = 0 to 7
Physical address 0x01C0 208C + (0x200*n) n = 0 to 7 Instance IVA2.2 TPCC
Description QDMA Event Enable Set Register:
CPU write of 1 to the QEESR.En bit causes the QEESR.En bit to be set.
CPU write of 0 has no effect.
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
E7 E6 E5 E4 E3 E2 E1 E0
Bits Field Name Description Type Reset
31:8 Reserved Write 0s for future compatibility. W 0x000000
7 E7 Event #7 W 0
6 E6 Event #6 W 0
5 E5 Event #5 W 0
4 E4 Event #4 W 0
3 E3 Event #3 W 0
2 E2 Event #2 W 0
1 E1 Event #1 W 0
0 E0 Event #0 W 0
Table 5-381. Register Call Summary for Register TPCC_QEESR_Rn
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
Table 5-382. TPCC_QSER_Rn
Address Offset (0x200*n) n = 0 to 7
Physical address 0x01C0 2090 + (0x200*n) n = 0 to 7 Instance IVA2.2 TPCC
Description QDMA Secondary Event Register:
The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information
on the state of a QDMA Event.
En = 0: Event is not currently in the Event Queue.
En = 1: Event is currently stored in Event Queue. Event arbiter will not prioritize additional events.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
E7 E6 E5 E4 E3 E2 E1 E0
947 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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