Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
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Bits Field Name Description Type Reset
15:0 SCIDX Source Frame Index: RW 0x----
SCIDX is a 16-bit signed value (2s complement) used for source
address modification for the 3rd dimension. It is a signed value
between -32768 and 32767. It provides a byte address offset from
the
beginning of the current array (pointed to by SRC address) to the
beginning of the first source array in the next frame. It applies to
both A-sync and AB-sync transfers. Note that when SCIDX is
applied, the current arraya in an A-sync transfer is the last array in
the frame, while the current array in a AB-sync transfer is the first
array in the frame.
Table 5-399. Register Call Summary for Register TPCC_CIDXm
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
Table 5-400. TPCC_CCNTm
Address Offset (0x20*m)
Physical address 0x01C0 401C + (0x20*m) Instance IVA2.2 TPCC
Description C byte count
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CCNT
Bits Field Name Description Type Reset
31:16 Reserved Write 0s for future compatibility. RW 0x0000
Read returns 0.
15:0 CCNT CCNT Count for 3rd Dimension: RW 0x----
CCNT is a 16-bit unsigned value that specifies the number of frames
in a block. Valid values for CCNT can be anywhere between 1 and
65535. Therefore, the maximum number of frames in a block is
65535 (64K-1 frames). CCNT of 1 means 1 frame in the block, and
CCNT of 0 means 0 frames in the block. A CCNT value of 0 is
considered as either a null or dummy transfer. A Dummy or Null
transfer will generate a Completion code depending on the settings
of the completion bit fields of the OPTi field.
Table 5-401. Register Call Summary for Register TPCC_CCNTm
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
5.5.6 TPTC0 and TPTC1 Registers
This section provides information about the TPTC0 and TPTC1 Modules. Each register in the Modules is
described separately below.
5.5.6.1 TPTC0 and TPTC1 Register Mapping Summary
Table 5-402. TPTC0 and TPTC1 Register Summary
Register Name (j = 0 Type RegisterWidth Address TPTC0 TPTC1
or 1) (Bits) Offset Physical Address Physical Address
TPTCj_PID R 32 0x000 0x01C1 0000 0x01C1 0400
TPTCj_TCCFG R 32 0x004 0x01C1 0004 0x01C1 0404
TPTCj_TCSTAT R 32 0x100 0x01C1 0100 0x01C1 0500
TPTCj_INTSTAT R 32 0x104 0x01C1 0104 0x01C1 0504
954 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated