Public Version
www.ti.com
McBSP Overview
–
32-bit data bus width
–
32-bit access supported
–
16- /8-bit access supported only by data registers
–
10-bit address bus width
–
Burst mode not supported
–
Write nonposted transaction mode supported
•
128 × 32-bit words (512 bytes) for each buffer for transmit/receive operations (McBSP1, 3, 4, 5)
•
5K bytes (1024 x 32 bits for audio 256 × 32 bits for buffer) for each buffer for transmit/receive
audio operations (McBSP2 only)
•
Interrupts configurable in legacy mode (2 requests) or PRCM compliant (1 request)
•
Transmit and receive DMA requests triggered with programmable FIFO thresholds
•
SIDETONE core support: Audio loopback capability (McBSP2 and 3 only)
•
Multidrop support
•
Serial interface description
–
6 pin configuration (McBSP 1 only)
–
4 pin configuration (McBSP2, 3, 4, 5)
–
Full-duplex communication
–
Multichannel selection modes
•
Support to enable or block transfers in each of the channels
•
128 channels for transmission and for reception
–
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected A/D and D/A devices:
•
Inter-IC sound (I2S) compliant devices
•
Pulse code modulation (PCM) devices
•
Time division multiplexed (TDM) bus devices
CAUTION
McBSP modules do not offer support for
m
-law and A-law companding, two
partitions mode dynamic reassignment, AC’97, and SPI protocol.
–
A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
–
Bit reordering (send/receive least significant bit [LSB])
•
Clock and frame-synchronization generation support:
–
Independent clocking and framing for reception and for transmission up to 48 MHz
–
Support for external generation of clock signals and frame-synchronization (frame-sync) signals
–
A programmable sample rate generator for internal generation and control of clock signals and
frame-sync signals
–
Programmable polarity for frame-sync pulses and for clock signals
NOTE:
•
McBSP modules do not support features such as re-transmit or re-receive of an
erroneous frame or word.
•
McBSP modules support dual phase frames to provide I2S fully compliant capabilities.
But, this dual phase mode is limited at one channel (or word) for each phase instead of
128 channels max for single phase mode.
21.1.2 SIDETONE Core
The purpose of this section is to present the SIDETONE core implemented in McBSP2 and 3 modules. It
is required that two of the audio input channels to be looped back, filtered, and mixed to the two
corresponding audio output channels.
3057
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated
