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General-Purpose Interface Basic Programming Model
•
Interrupt status registers (GPIOi.
and GPIOi.
)
The interrupt-status1 (or interrupt-status2) register determines which of the input GPIO pins triggered
the interrupt line1 (or interrupt line2) request (or the wake-up line).
When a bit in this register is set to 1, it indicates that the corresponding GPIO pin is requesting the
interrupt (or the wakeup). To reset a bit in this register, write 1 to the appropriate bit. However, an
interrupt cannot be generated by writing 1 to the interrupt-status1 (or interrupt-status2) register.
If 0 is written to a bit in this register, the value remains unchanged. The interrupt-status1 (or
interrupt-status2) register is synchronous with the interface clock. In idle mode, the event is detected
through an asynchronous path, and the corresponding bit in the interrupt-status1 and interrupt-status2
registers are set when GPIO is awake.
NOTE:
The wake-up capabilities of GPIO2 to GPIO6 are operational only when the PER power
domain is active.
25.5.3.2 Description
To generate interrupt request to a host processor (the MPU and/or digital signal processor [DSP]
subsystem in the device) at a defined event (level or edge logic transition) occurring on a GPIO pin
(interrupt source), the GPIO configuration registers must be programmed as follows:
1. The GPIO channel must be configured as input by the output-enable register (write 1 to the
corresponding bit of the GPIOi.
register).
2. The expected event(s) on the GPIO input to trigger the interrupt request must be selected in the
low-level interrupt-enable register (write 1 or 0 to the corresponding bit of
GPIOi.
), and/or high-level interrupt-enable register (write 1 or 0 to the
corresponding bit of GPIOi.
), and/or rising-edge interrupt/wakeup-enable
register (write 1 or 0 to the corresponding bit of GPIOi.
), and/or falling edge
interrupt/wakeup-enable register (write 1 or 0 to the corresponding bit of
GPIOi.
NOTE:
Interrupt generation on both edges on one input is configured by setting the corresponding
bit to 1 in the rising detect enabling register (GPIOi.
) and falling
detect enabling register (GPIOi.
) along with the interrupt-enable by
setting the corresponding bit to 1 in one or both interrupt-enable registers
(GPIOi.
and GPIOi.
Simultaneous enabling of high-level and low-level detections for one given pin creates a
constant-interrupt generator.
3. Interrupts from the GPIO channel must be enabled in the interrupt 1 enable register (write 1 to the
corresponding bit of the GPIOi.
register) and/or the interrupt 2 enable register
(write 1 to the corresponding bit of the GPIOi.
register).
To configure a GPIO module to send a wake-up request to the PRCM module at a defined event (logic
transition) occurring on a GPIO pin (wake-up source), the GPIO configuration registers must be
programmed as follows:
1. The GPIO pin must be configured as input by the output-enable register (write 1 to the corresponding
bit of the GPIOi.
register).
2. The expected event(s) on the GPIO input to trigger the wake-up request must be selected in the
rising-edge interrupt/wakeup-enable register (write 1 or 0 to the corresponding bit of
GPIOi.
) and/or falling-edge interrupt/wakeup-enable register (write 1 or 0 to the
corresponding bit of GPIOi.
). The wake-up request can be generated only on
edge transitions.
3. The GPIO channel must be enabled in the wakeup-enable register (write 1 to the corresponding bit of
the GPIOi.
register).
4. The wake-up request generation on the expected transition occurring on the GPIO input pins must
enable the module (write 1 to the corresponding bit of the GPIOi.
[2] ENAWAKEUP
bit) .
3483
SWPU177N – December 2009 – Revised November 2010
General-Purpose Interface
Copyright © 2009–2010, Texas Instruments Incorporated
