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PRCM Functional Description
The power-up sequence shown in
is:
1. Voltages ramp up and global power-on reset is asserted by the external power IC:
•
vdds, vdds_mem, vdda_wkup_bg_bb, vdda_sram voltage rails are ramped up.
•
sys_nrespwron is asserted (set to low).
•
vdda_dpll_dll and vdda_dpll_per voltage rails are ramped up before release of sys_nrespwron
(transition to high).
•
The VDD3 voltage domain LDO (WKUP power domain) tracks vdda_wkup voltage rail and
automatically ramps up.
•
After VDD3 voltage domain stabilization, the power IC ramps up VDD2 voltage domain.
•
After VDD2 voltage domain stabalization, the power IC ramps up VDD1 voltage domain.
2. Source clock stabilizes:
•
The 32-kHz input clock and the system clock oscillator stabilize.
•
The device reset manager holds the entire device under reset.
•
The system clock (SYS_CLK) is on.
3. The global power-on reset sys_nrespwron released (to high) when vdda_dpll_dll and vdda_dpll_per
voltage rails are stabilized.
4. The eFuse farm reset is released.
5. Internal memory LDOs ramp up:
•
Processor memory LDO (VDD4 voltage domain) is ramped up.
•
CORE memory LDO (VDD5 voltage domain) is ramped up.
•
The PRCM module waits for internal memory LDO stabilization.
6. Global resets are released. Global power-on reset and global warm reset are extended (remain
asserted) on release of the external power-on reset until the following conditions are met:
•
Voltages are stable in the processor power domains, CORE power domain, and WKUP power
domain.
•
System clock is stable.
•
Internal memory LDO is stable.
•
Device reset manager counter overflows (set up by the PRCM.
[7:0] RSTTIME1 bit
field).
•
Hardware conditions, such as eFuse farm ready, are set.
7. The PRM_RSTPWRON reset is released.
8. The CM_SYS_CLK clock starts running (gating logic is enabled).
9. The CM_RSTPWRON_RET reset is released.
10. The reset of the DPLLs is released.
11. The DPLL3_ALWON_FCLK clock starts to run (gating logic is enabled).
12. The L3_ICLK clock starts to run.
13. The DPLL1_ALWON_FCLK clock starts to run (logic controlling the clock-gating conditions element is
clocked and the clock is requested).
14. The CORE_RST reset is released.
15. The MPU_CLK clock starts to run.
16. The MPU boots.
NOTE:
•
The IVA2 power domain is held under reset after power up by assertion of the software
source of reset.
•
Power domains such as DSS, CAM, SGX, and NEON are held under reset after power
up until the MPU software enables the power domain interface clocks.
269
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
