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General-Purpose Memory Controller
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Table 10-18. Useful Timing Parameters on the Memory Side (continued)
AC Read Characteristics on the
Description
Duration (ns)
Memory Side
tBACC
Burst access time valid clock to output
5,2
delay
tCEZ
Chip-select to High-Z
7
tOEZ
Output enable to High-Z
7
tAVC
nADV setup time
6
tAVD
nAVD pulse
6
tACH
Address hold time from clock
3
The following terms, which describe the timing interface between the controller and its attached device,
are used to calculate the timing parameters on the GPMC side:
•
Read access time (GPMC side): Time required to activate the clock + read access time requested on
the memory side + data setup time required for optimal capture of a burst of data
•
Data setup time (GPMC side): Ensures a good capture of a burst of data (as opposed to taking a burst
of data out). One burst of data is processed in one clock cycle (T = 9,615 ns). The read access time
between two bursts of data is tBACC = 5,2 ns. Therefore, data setup time is a clock period - tBACC =
4,415 ns of data setup.
•
Access completion (GPMC side): (Different from page burst access time) Time required between the
last burst access and access completion: nCS/nOE hold time (nCS and nOE must be released at the
end of an access. These signals are held to allow the access to complete).
•
Read cycle time (GPMC side): Read access time + access completion
•
Write cycle time for burst access: Not supported for NOR flash memory
Table 10-19. Calculating GPMC Timing Parameters
Parameter
Formula
Duration (ns)
Number of
GPMC Register
Name on GPMC
Clock Cycles
Configurations
Side
(F = 104 MHz)
ClkActivation
min ( tCES, tACS)
3
1
CLKACTIVATIONTIME = 0x1
Time
RdAccessTime
roundmax (ClkActivati
94,03: (9,615 + 80
10 : roundmax
ACCESSTIME = 0x0A
tIACC + DataSetupTime)
+ 4,415)
(94,03 / 9,615)
PageBurst
roundmax (tBACC)
roundmax (5,2)
1
PAGEBURSTACCESSTIME =
AccessTime
0x1
RdCycleTime
Acce max ( tCEZ, tOEZ)
101, 03: (94, 03 +
11
RDCYCLETIME = 0x0B
7)
CsOnTime
tCES
0
0
CSONTIME = 0x0
CsReadOffTime
RdCycleTime
-
11
CSRDOFFTIME = 0x0B
AdvOnTime
tAVC
(1)
0
0
ADVONTIME = 0x0
AdvRdOffTime
tAVD + tAVC
(2)
12
2
ADVRDOFFTIME = 0x02
OeOnTime
(3)
(ClkActivati tACH) <
-
3 for instance.
OEONTIME = 0x3
OeOnTime < (ClkActivati
tIACC)
OeOffTime
RdCycleTime
-
11
OEOFFTIME = 0x0B
(1)
The external clock provided to the NOR flash is not yet available.
(2)
AdvRdOffTime - AdvOnTime = tAVD; thus, AdvRdOffTime = tAVD + AdvOnTime = tAVD + tAVC.
(3)
OeOnTime must guarantee that addresses are available. It must not exceed the availability of the first burst of data.
2188
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
