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Camera ISP Environment
Table 6-2. IO Description (continued)
Ball Name
I/O
(1)
Description
Parallel SYNC
Parallel ITU Mode
Serial Mode CSI\CCP2
Serial Mode CSI2
Mode
ccpv2_dy0
I
Serial CSI/CCP2B mode: Fully
+
configurable pair: strobe or
data, positive or negative
ccpv2_dx1
I
Serial CSI/CCP2B mode: Fully
+
configurable pair: strobe or
data, positive or negative
ccpv2_dy1
I
Serial CSI1/CCP2B mode:
+
Fully configurable pair: strobe
or data, positive or negative
cam_xclka
O
External clock for the
+
+
+
+
image-sensor module
cam_xclkb
O
External clock for the
+
+
+
+
image-sensor module
6.2.3 Camera ISP Connectivity Schemes
The cam_d[9:6] implements the CSIPHY1. The cam_d[1:0] implements the CSIPHY2. Moreover, the PHY's can be configured in GPI, CCP or
D-PHY modes from the control module and the SCM.CONTROL_CAMERA_PHY_CTRL control module register. Besides the mode set, from the
SCM.CONTROL_CAMERA_PHY_CTRL[4] CSI1_RX_sel sets which PHY will be hooked to the CSI1/ CCP2B receiver of the ISP. Some
initialization and pad configuration must also be done. For information about initializing and configuring the CSIPHY, see
Programming the CSI1/CCP2B or CSI2 Receiver Associated PHY.
❏
In GPI mode, the PHY can be connected to a parallel camera (CAM_D[1:0] in CSIPHY1 and CAM_D[9:6] in CSIPHY2)
❏
In CCP mode, the PHY can be connected to a CCPV2 camera (strobe/data pairs) or a CSI1 camera (clock/data pairs)
❏
In D-PHY mode, the PHY can be connected to a CSI2 camera (2 or 1 data lane in CSIPHY1 and 1 data lane only in CSIPHY2)
Table 6-3. Camera ISP Connectivity Schemes
Receiver
Scheme 1
Scheme 2
Scheme 3
Scheme 4
Scheme 5
Scheme 6
Legacy
Legacy
Addon
Legacy
Addon
Addon
CPI
ON, up to 10-bit
ON, 12-bit
ON, 12-bit
OFF
OFF
OFF
Serial CSI2A
ON, CSI2A 2 data lanes
ON, CSI2A 1 data lane
OFF
ON, CSI2A 2 data lanes
ON, CSI2A 2 data lanes
OFF
Serial CSI1 / CCP2B
OFF
OFF
ON, CSI1/ CCP2B 1
ON, CSI1/ CCP2B 1
OFF
ON, CSI1/CCP2B 1
data lane
data lane
data lane
Serial CSI2C
OFF
OFF
OFF
OFF
ON, CSI2C 1 data lanes
OFF
Data flows handling by ISP
Simultaneous
Simultaneous
Simultaneous
Simultaneous
Simultaneous
Sequential through
control module selection
1093
SWPU177N – December 2009 – Revised November 2010
Camera Image Signal Processor
Copyright © 2009–2010, Texas Instruments Incorporated