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IVA2.2 Subsystem Register Manual
Table 5-776. iLF_CONFIGREG
Address Offset
0x0000 05FC
Physical Address
0x000A 15FC
Instance
iLF
Description
Configuration Register
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
ITENABLE
RESERVED
DEBUGHALTEN
Bits
Field Name
Description
Type
Reset
31:3
RESERVED
read returns 0.
R
0x0000000
2
DEBUGHALTEN
"Debug Halt" control bit
R
0x0
1
RESERVED
read returns 0.
R
0x0
0
ITENABLE
Interrupt Enable bit
RW
0x0
Table 5-777. Register Call Summary for Register iLF_CONFIGREG
IVA2.2 Subsystem Register Manual
•
Table 5-778. iLF_PARSEDDATAREG0
Address Offset
0x0000 0600 in 0xc byte increments
Physical Address
0x000A 1600
Instance
iLF
Description
Lower part of the Loop Filter parameters set
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TC0_FIELD
TC0B_FIELD
BETA2_FIELD
BETA_FIELD
ALPHA_FIELD
RESERVED
RESERVED
Bits
Field Name
Description
Type
Reset
31
RESERVED
read returns 0.
R
0x-
30:26
TC0_FIELD
Tc0 parameter, 5 bits, unsigned
RW
0x--
25
RESERVED
read returns 0.
RW
0x--
24:20
TC0B_FIELD
Tc0B parameter, 5 bits, unsigned
RW
0x--
19:13
BETA2_FIELD
Beta2 parameter, 7 bits, unsigned
RW
0x--
12:8
BETA_FIELD
Beta parameter, 5 bits, unsigned
RW
0x--
7:0
ALPHA_FIELD
Alpha parameter, 8 bits, unsigned
RW
0x--
Table 5-779. Register Call Summary for Register iLF_PARSEDDATAREG0
IVA2.2 Subsystem Register Manual
•
1075
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated