Texas Instruments OMAP36 Series, Technical Reference Manual

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SDRAM Controller (SDRC) Subsystem
Table 10-173. SDRC_MCFG_p
Address Offset 0x0000 0080 + (0x0000 0030 * p) Index p = 0 to 1
Physical Address 0x6D00 0080 + (0x0000 0030 * p) Instance SDRC
Description This register provides the memory configuration register.
Type RW
Register Description for ADDRMUXLEGACY = 0x1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMSIZE
DEEPPD
DDRTYPE
RAMTYPE
B32NOT16
RASWIDTH CASWIDTH
RESERVED RESERVED RESERVED RESERVED RESERVED
LOCKSTATUS
BANKALLOCATION ADDRMUXLEGACY
Bits Field Name Description Type Reset
31 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
30 LOCKSTATUS Read-only access lock bit RW See
(1)
0x0: This register is fully writable
0x1: When this bit is set, the register can not be unset until next reset of
the module.
29:27 RESERVED Write 0s for future compatibility. Read returns 0. RW See
(1)
26:24 RASWIDTH RAS address width RW See
(1)
0x0: RAS width = 11 bits
0x1: RAS width = 12 bits
0x2: RAS width = 13 bits
0x3: RAS width = 14 bits
0x4: RAS width = 15 bits
0x5: RAS width = 16 bits - Must not be used
0x6: RAS width = 17 bits - Must not be used
0x7: RAS width = 18 bits - Must not be used
23 RESERVED Write 0s for future compatibility. Read returns 0. RW See
(1)
22:20 CASWIDTH CAS address width RW See
(1)
0x0: CAS width = 5 bits
0x1: CAS width = 6 bits
0x2: CAS width = 7 bits
0x3: CAS width = 8 bits
0x4: CAS width = 9 bits
0x5: CAS width = 10 bits
0x6: CAS width = 11 bits
0x7: CAS width = 12 bits
19 ADDRMUXLEGACY Selects the fixed address-muxing scheme or the flexible address-muxing RW See
(1)
scheme
0x0: Fixed address mux scheme
0x1: Flexible address mux scheme
18 RESERVED Write 0s for future compatibility. Read returns 0. RW See
(1)
17:8 RAMSIZE RAM address space size number of 2-MB chunks RW See
(1)
(1)
Reset value is copied from the system control module. See the note in Section 10.2.5.3.2 and Section 13.4.9 , SDRC Registers, in
Chapter 13 , System Control Module.
2323 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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