D6
D7
D5
D4
D3
D2
D1
D0
X
i2c _sccbe
i
Start of
transmission
Stop of
transmission
i2c _sda
i
i2c _scl
i
i2c-013
7-bit slave address
R/W
X
8-bit subaddress (register address)
-
X
8-bit write data
X
7
1
1
8
1
8
1
Phase 1
Phase 2
Phase 3
(a) SCCB 3-phase write
7-bit slave address
R/W
X
8-bit subaddress (register address)
X
7
1
1
8
1
Phase 1
Phase 2
7-bit slave address
R/W
X
8-bit read data
NA
7
1
1
8
1
Phase 1
Phase 2
(c) SCCB 2-phase read
R/W: 0 = Write, 1 = Read
X: Don’t care
:
0
NA: Ninth bit of a read phase. This bit must be set to 1 by the master device.
ID value
ID value
ID value
Master to slave
Slave to master
0
(b) SCCB 2-phase write
1
i2c-014
Public Version
www.ti.com
HS I
2
C Environment
17.2.2.3 HS I
2
C SCCB Typical Connection Protocol and Data Format
17.2.2.3.1 HS I
2
C Serial Transmission Timing Diagram
is the timing diagram of the 3-wire SCCB data transmission.
Figure 17-13. HS I
2
C 3-Wire SCCB Transmission Timing Diagram
NOTE:
When operating in 2-wire SCCB mode, the i2ci_sccbe signal is not used by the 2-wire
SCCB-compliant slave device attached to the 2-wire SCCB bus.
17.2.2.3.2 HS I
2
C SCCB Transmission Data Formats
describes the data format of the three kinds of transmission.
Figure 17-14. HS I
2
C SCCB Transmission Data Formats
The basic element of a data transmission is a phase. A phase contains 9 bits, which consist of an 8-bit
sequential data transmission followed by a ninth bit. The ninth bit is a don't-care bit (X) or an NA bit,
depending on whether the data transmission is a write or a read. The maximum number of phases that
can be included in a transmission is three. The MSB is always asserted first for each phase.
A data transmission is one of three types:
2777
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated
