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21-31. McBSP Reception Physical Data Path

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3100

21-32. McBSP Reception Signal Activity

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21-33. McBSP Transmission Physical Data Path

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21-34. McBSP Transmission Signal Activity

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21-35. Transmit Full Cycle Timing Diagram

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21-36. Transmit Half Cycle Timing Diagram

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21-37. Receive Full Cycle Timing Diagram

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21-38. Receive Half Cycle Timing Diagram

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21-39. Conceptual Block Diagram of the Sample Rate Generator

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21-40. CLKG Synchronization and FSG Generation (GSYNC = 1 and CLKGDV = 0x1)

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21-41. CLKG Synchronization and FSG Generation (GSYNC = 1 and CLKGDV = 0x3)

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21-42. Overrun in the McBSP Receiver

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21-43. Unexpected Frame-sync Pulse During a McBSP Reception

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21-44. Proper Positioning of Receive Frame-sync Pulses

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21-45. Unexpected Frame-sync Pulse During a McBSP Transmission

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21-46. Proper Positioning of Transmit Frame-sync Pulses

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21-47. McBSP Data Transfer in 8-Partition Mode

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21-48. Alternating Between Partitions A and B Channels

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21-49. Activity on McBSP Pins When XMCM=0b00

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21-50. Activity on McBSP Pins When XMCM=0b01

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21-51. Activity on McBSP Pins When XMCM=0b10

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21-52. Activity on McBSP Pins When XMCM=0b11

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21-53. SIDETONE Data Path

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21-54. McBSP to SIDETONE Data Exchange

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21-55. SIDETONE to McBSP Data Exchange

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21-56. SIDETONE Processed Data Interfaces

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21-57. Flow Diagram of McBSP Initialization Procedure for Master Mode

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21-58. Flow Diagram of McBSP Initialization Procedure for Slave Mode

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21-59. Flow Diagram for the SRG Registers Programmation

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21-60. Important Tasks to Configure the McBSP Receiver (Part 1)

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21-61. Important Tasks to Configure the McBSP Receiver (Part 2)

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21-62. Range of Programmable Data Delay

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21-63. 2-Bit Data Delay Used to Skip a Framing Bit

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3138

21-64. Data Externally Clocked on a Rising Edge and Sampled on a Falling Edge

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21-65. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods

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3141

21-66. Important Tasks to Configure the McBSP Transmitter (Part 1)

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3143

21-67. Important Tasks to Configure the McBSP Transmitter (Part 2)

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21-68. Range of Programmable Data Delay

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21-69. 2-Bit Data Delay Used to Skip a Framing Bit

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3146

21-70. Four 8-bit Data Words Transferred To/From McBSP Module

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21-71. One 32-bit Data Word Transferred To/From McBSP Module

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21-72. 8-bit Data Words Transferred at Maximum Packet Frequency

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3152

21-73. Configuring the Data Stream as a Continuous 32-bit Word

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3152

22-1.

USB Modules Overview

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3210

22-2.

High-Speed USB Controller Highlight

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3211

22-3.

High-Speed USB Controller Typical Application System

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3213

22-4.

High-Speed USB Controller Functional Interface Signals

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3214

22-5.

High-Speed USB Controller Integration

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22-6.

High-Speed USB Controller

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3221

List of Figures

SWPU177N – December 2009 – Revised November 2010

Summary of Contents for OMAP36 Series

Page 1: ... Public Version OMAP36xx Multimedia Device Silicon Revision 1 x Texas Instruments OMAP Family of Products Version N Technical Reference Manual Literature Number SWPU177N December 2009 Revised November 2010 ...

Page 2: ...ibited by U S or other applicable laws without obtaining prior authorisation from U S Department of Commerce and other competent Government authorities to the extent required by those laws This provision shall survive termination or expiration of this Agreement According to our best knowledge of the state and end use of this product or technology and in compliance with the export control regulatio...

Page 3: ... 3 2 4 L4 Emulation Memory Space Mapping 215 2 3 3 Register Access Restrictions 216 2 4 IVA2 2 Subsystem Memory Space Mapping 218 2 4 1 IVA2 2 Subsystem Internal Memory and Cache Allocation 218 2 4 1 1 IVA2 2 Subsystem Memory Hierarchy 218 2 4 1 2 IVA2 2 Cache Allocation 219 2 4 2 DSP Access to L2 Memories 220 2 4 2 1 DSP Access to L2 ROM 220 2 4 2 2 DSP Access to L2 RAM 220 2 4 3 DSP and EDMA Acc...

Page 4: ...tion 246 3 4 1 Power Management Scheme Reset and Interrupt Requests 249 3 4 1 1 Power Domain 249 3 4 1 2 Resets 249 3 4 1 3 Interrupt Requests 250 3 5 PRCM Functional Description 251 3 5 1 PRCM Reset Manager Functional Description 251 3 5 1 1 Overview 251 3 5 1 2 General Characteristics of Reset Signals 251 3 5 1 2 1 Scope 252 3 5 1 2 2 Occurrence 252 3 5 1 2 3 Source Type 252 3 5 1 3 Reset Source...

Page 5: ...r Domain Implementation 286 3 5 2 2 1 Device Power Domains 286 3 5 2 2 2 Power Domain Memory Status 288 3 5 2 2 3 Power Domain State Transition Rules 288 3 5 2 2 4 Power Domain Dependencies 288 3 5 2 2 5 Power Domain Controls 289 3 5 3 PRCM Clock Manager Functional Description 291 3 5 3 1 Overview 291 3 5 3 1 1 Interface and Functional Clocks 292 3 5 3 2 External Clock I Os 293 3 5 3 2 1 External ...

Page 6: ...view 353 3 5 4 2 Sleep Transition 355 3 5 4 3 Wakeup 355 3 5 4 4 Device Wake Up Events 356 3 5 4 5 Sleep and Wake Up Dependencies 361 3 5 4 5 1 Sleep Dependencies 361 3 5 4 5 2 Wake Up Dependencies 363 3 5 4 6 USBHOST USBTLL Save and Restore Management 366 3 5 4 6 1 USBHOST SAR Sequences 368 3 5 4 6 2 USB TLL SAR Sequences 368 3 5 5 PRCM Interrupts 369 3 5 6 PRCM Voltage Management Functional Desc...

Page 7: ...6 2 3 DPLL Clock Control Registers 403 3 6 2 3 1 CM_CLKSELn_PLL_ processor_name Processor DPLL Clock Selection Register 403 3 6 2 3 2 CM_CLKSELn_PLL DPLL Clock Selection Register 403 3 6 2 3 3 CM_CLKEN_PLL_ processor_name Processor DPLL Clock Enable Register 404 3 6 2 3 4 CM_CLKEN_PLL DPLL Enable Register 404 3 6 2 3 5 CM_AUTOIDLE_PLL_ processor_name Processor DPLL Autoidle Register 404 3 6 2 3 6 ...

Page 8: ... Configuration Register 422 3 6 5 2 7 PRM_VC_BYPASS_VAL Voltage Controller Bypass Command Register 423 3 6 5 3 Voltage Processor Registers 423 3 6 5 3 1 PRM_VP_CONFIG Voltage Processor Configuration Register 423 3 6 5 3 2 PRM_VP_VSTEPMIN Voltage Processor Minimum Voltage Step 423 3 6 5 3 3 PRM_VP_VSTEPMAX Voltage Processor Maximum Voltage Step 423 3 6 5 3 4 PRM_VP_VLIMITTO Voltage Processor Voltag...

Page 9: ... 1 6 SGX_CM Registers 487 3 8 1 6 1 SGX_CM Register Summary 487 3 8 1 6 2 SGX_CM Registers 488 3 8 1 7 WKUP_CM Registers 492 3 8 1 7 1 WKUP_CM Register Summary 492 3 8 1 7 2 WKUP_CM Registers 492 3 8 1 8 Clock_Control_Reg_CM Registers 497 3 8 1 8 1 Clock_Control_Reg_CM Register Summary 497 3 8 1 8 2 Clock_Control_Reg_CM Registers 498 3 8 1 9 DSS_CM Registers 510 3 8 1 9 1 DSS_CM Register Summary 5...

Page 10: ...ister Summary 600 3 8 2 8 2 Clock_Control_Reg_PRM Registers 601 3 8 2 9 DSS_PRM Registers 602 3 8 2 9 1 DSS_PRM Register Summary 602 3 8 2 9 2 DSS_PRM Registers 602 3 8 2 10 CAM_PRM Registers 607 3 8 2 10 1 CAM_PRM Registers 607 3 8 2 10 2 CAM_PRM Registers 607 3 8 2 11 PER_PRM Registers 611 3 8 2 11 1 PER_PRM Register Summary 611 3 8 2 11 2 PER_PRM Registers 611 3 8 2 12 EMU_PRM Registers 624 3 8...

Page 11: ...Subsystem Functional Description 685 4 3 1 Interrupts 685 4 3 2 Power Management 685 4 3 2 1 Power Domains 685 4 3 2 2 Power States 686 4 3 2 3 Power Modes 686 4 3 2 4 Transitions 688 4 4 MPU Subsystem Basic Programming Model 690 4 4 1 MPU Subsystem Initialization Sequence 690 4 4 2 Clock Control 690 4 4 3 MPU Power Mode Transitions 690 4 4 3 1 Basic Power On Reset 690 4 4 3 2 MPU Into Standby Mod...

Page 12: ...r Sequencer 726 5 3 2 3 IDMA 727 5 3 3 MMU 727 5 3 3 1 MMU VA to PA Translation 728 5 3 3 2 MMU Configuration 729 5 3 4 Video Accelerator Sequencer Local Interconnect 730 5 3 5 SL2 Interface 731 5 3 5 1 BWO 732 5 3 5 2 Arbiter 733 5 3 5 3 Restrictions on SL2 Memory Usage 733 5 3 5 4 Error Management 733 5 3 6 Wake Up Generator 733 5 3 6 1 Interrupts DMA Requests and Event Management 734 5 3 6 1 1 ...

Page 13: ... 4 4 2 Internal Memory to Memory Transfer IDMA 757 5 4 4 3 Programming an EDMA Transfer 758 5 4 4 4 Defining a Logical Channel 758 5 4 4 4 1 Single Logical Channel Definition 758 5 4 4 4 2 Controlling Submission Granularity 759 5 4 4 4 3 Linking to Another Logical Channel 759 5 4 4 4 4 Chaining Logical Channel 760 5 4 4 5 Prioritizing Defined Transfers 760 5 4 4 5 1 Mapping Between DMA QDMA Events...

Page 14: ...r Down of IVA2 2 Subsystem 783 5 4 8 6 Interrupt Controller Basic Programming Model for Power On of IVA2 2 Subsystem 783 5 4 8 7 Video and Sequencer Module interrupt Handling 786 5 4 8 7 1 Sequencer Interrupt 786 5 4 8 7 2 DSP Megamodule Interrupt 786 5 4 9 Memory Management 788 5 4 9 1 External Memory 788 5 4 9 1 1 Cacheability 788 5 4 9 1 2 Virtual Addressing 788 5 4 9 2 Internal Memory 788 5 4 ...

Page 15: ...ions 986 5 5 9 iVLCD Registers 1004 5 5 9 1 iVLCD Register Mapping Summary 1004 5 5 9 2 iVLCD Register Descriptions 1006 5 5 10 SEQ Registers 1044 5 5 10 1 SEQ Register Mapping Summary 1044 5 5 10 2 SEQ Register Descriptions 1044 5 5 11 Video System Controller Registers 1051 5 5 11 1 Video System Controller Register Mapping Summary 1051 5 5 11 2 Video System Controller Register Descriptions 1051 5...

Page 16: ... 1 Camera ISP Hardware Reset 1143 6 3 1 4 2 Camera ISP Software Reset 1144 6 3 2 Camera ISP Hardware Requests 1144 6 3 2 1 Camera ISP Interrupt Requests 1144 6 4 Camera ISP Functional Description 1154 6 4 1 Camera ISP Block Diagram 1154 6 4 1 1 Camera ISP Possible Data Paths Inside the module 1156 6 4 1 1 1 Camera ISP RGB RAW Data 1157 6 4 1 1 2 Camera ISP YUV4 2 2 Data 1158 6 4 1 1 3 JPEG Data 11...

Page 17: ...1 6 Camera ISP VPBE Preview Dark Frame Subtract or Shading Compensation 1209 6 4 7 1 7 Camera ISP VPBE Preview Horizontal Median Filter 1209 6 4 7 1 8 Camera ISP VPBE Preview Noise Filter and Faulty Pixel Correction 1209 6 4 7 1 9 Camera ISP VPBE Preview White Balance 1209 6 4 7 1 10 Camera ISP VPBE Preview CFA Interpolation 1210 6 4 7 1 11 Camera ISP VPBE Preview Black Adjustment 1210 6 4 7 1 12 ...

Page 18: ... Initialization for Work With CSI2 Receiver 1244 6 5 2 2 Camera ISP CSIPHY Initialization for Work With CSI1 CCP2B Receiver 1246 6 5 3 Programming the CSI1 CCP2B Receiver 1247 6 5 3 1 Camera ISP CSI1 CCP2B Hardware Setup Initialization 1247 6 5 3 1 1 Camera ISP CSI1 CCP2B Reset Behavior 1247 6 5 3 2 Camera ISP CSI1 CCP2B Event and Status Checking 1248 6 5 3 3 Camera ISP CSI1 CCP2B Register Accessi...

Page 19: ...ra ISP CCDC CCDC_VD2_IRQ Interrupt 1269 6 5 6 3 4 Camera ISP CCDC Status Checking 1269 6 5 6 4 Camera ISP CCDC Register Accessibility During Frame Processing 1269 6 5 6 5 Camera ISP CCDC Interframe Operations 1270 6 5 6 6 Camera ISP CCDC Operations 1270 6 5 6 6 1 Camera ISP CCDC Image Sensor Configuration 1270 6 5 6 6 2 Camera ISP CCDC Image Signal Processing 1273 6 5 6 7 Camera ISP CCDC Summary o...

Page 20: ...Central Resource SBL Event and Status Checking 1295 6 5 11 4 Camera ISP Central Resource SBL Register Accessibility During Frame Processing 1297 6 5 11 5 Camera ISP Central Resource SBL Camera ISP Bandwidth Adjustments 1297 6 5 11 5 1 Camera ISP Central Resource SBL Input From CCDC Video Port Interface 1297 6 5 11 5 2 Camera ISP Central Resource SBL Input From Memory 1298 6 5 12 Programming the Ci...

Page 21: ... 1559 7 1 Display Subsystem Overview 1560 7 2 Display Subsystem Environment 1565 7 2 1 LCD Support 1565 7 2 1 1 Parallel Interface 1569 7 2 1 1 1 Parallel Interface in RFBI Mode MIPI DBI Protocol 1569 7 2 1 1 2 Parallel Interface in Bypass Mode MIPI DPI Protocol 1572 7 2 1 1 3 LCD Output and Data Format for the Parallel Interface 1573 7 2 1 1 4 Transaction Timing Diagrams 1577 7 2 1 2 DSI Serial I...

Page 22: ... 7 3 2 1 2 DSI Protocol Engine DMA Request 1629 7 3 2 1 3 RFBI DMA Request 1629 7 3 2 2 Interrupt Requests 1629 7 3 2 2 1 DISPC Interrupt Request 1630 7 3 2 2 2 DSI Interrupt Request 1631 7 4 Display Subsystem Functional Description 1634 7 4 1 Block Diagram 1634 7 4 2 Display Controller Functionalities 1634 7 4 2 1 Display Modes 1636 7 4 2 1 1 LCD Output 1636 7 4 2 1 2 Digital Output 1636 7 4 2 2 ...

Page 23: ... 1675 7 4 3 7 1 Twakeup Timer 1675 7 4 3 7 2 ForceTxStopMode FSM 1675 7 4 3 7 3 TurnRequest FSM 1676 7 4 3 7 4 Peripheral Reset Timer 1677 7 4 3 7 5 HS TX Timer 1677 7 4 3 7 6 LP RX Timer 1678 7 4 3 8 Bus Turnaround 1679 7 4 3 9 PHY Triggers 1681 7 4 3 9 1 Reset 1681 7 4 3 9 2 Tearing Effect 1681 7 4 3 9 3 Acknowledge 1682 7 4 3 10 ECC Generation 1683 7 4 3 11 Checksum Generation for Long Packet P...

Page 24: ...ler Configuration 1708 7 5 3 2 Graphics Layer Configuration 1708 7 5 3 2 1 Graphics DMA Registers 1708 7 5 3 2 2 Graphics Layer Configuration Registers 1710 7 5 3 2 3 Graphics Window Attributes 1710 7 5 3 3 Video Layer Configuration 1713 7 5 3 3 1 Video DMA Registers 1713 7 5 3 3 2 Video Configuration Register 1714 7 5 3 3 3 Video Window Attributes 1714 7 5 3 3 4 Video Up Down Sampling Configurati...

Page 25: ...ence 1754 7 5 5 6 DSI PLL Error Handling 1757 7 5 5 7 DSI PLL Recommended Values 1757 7 5 6 DSI Complex I O Basic Programming Model 1758 7 5 6 1 Software Reset 1758 7 5 6 2 Reset Done Bits 1758 7 5 6 3 Pad Configuration 1759 7 5 6 4 Display Timing Configuration 1759 7 5 6 4 1 High Speed Clock Transmission 1759 7 5 6 4 2 High Speed Data Transmission 1760 7 5 6 4 3 Turn Around Request in Transmit Mo...

Page 26: ...y Subsystem Clock Enable 1790 7 6 2 3 DPLL4 in Low Power Mode 1790 7 6 2 4 Autoidle and Smart Idle 1791 7 6 2 4 1 Autoidle 1791 7 6 2 4 2 Smart Idle 1791 7 6 2 5 FIFO Thresholds 1791 7 6 2 5 1 FIFO Threshold Settings to Reduce Power Consumption 1791 7 6 2 6 Vertical and Horizontal Timings 1792 7 6 2 6 1 Horizontal and Vertical Timing Settings to Reduce Power Consumption 1793 7 6 3 How to Configure...

Page 27: ...sters 1818 7 7 2 2 Display Controller Registers 1822 7 7 2 3 RFBI Registers 1867 7 7 2 4 Video Encoder Registers 1882 7 7 2 5 DSI Protocol Engine Registers 1908 7 7 2 6 DSI Complex I O Registers 1952 7 7 2 7 DSI PLL Control Module Registers 1958 8 2D 3D Graphics Accelerator 1965 8 1 SGX Overview 1966 8 1 1 POWERVR SGX Main Features 1966 8 1 2 SGX 3D Features 1967 8 1 3 Universal Scalable Shader En...

Page 28: ...4 2 Time Out 2016 9 2 3 4 3 Error Steering 2016 9 2 3 4 4 Global Error Reporting 2017 9 2 4 L3 Interconnect Basic Programming Model 2021 9 2 4 1 General Recommendation 2021 9 2 4 2 Initialization 2021 9 2 4 3 Error Analysis 2021 9 2 4 3 1 Time Out Handling 2022 9 2 4 3 2 Acknowledging Errors 2024 9 2 4 4 Typical Example of Firewall Programming Example 2024 9 2 5 L3 Interconnect Register Manual 202...

Page 29: ...ent L4 TA 2086 9 3 5 2 1 L4 Target Agent L4 TA Registers Description 2092 9 3 5 3 L4 Link Register Agent LA 2096 9 3 5 3 1 L4 Link Register Agent LA Registers Description 2097 9 3 5 4 L4 Address Protection AP 2101 9 3 5 4 1 L4 Address Protection AP Registers Description 2102 10 Memory Subsystem 2113 10 1 General Purpose Memory Controller 2114 10 1 1 General Purpose Memory Controller Overview 2114 ...

Page 30: ...5 3 8 Access Time RDACCESSTIME WRACCESSTIME 2132 10 1 5 3 9 Page Burst Access Time PAGEBURSTACCESSTIME 2133 10 1 5 3 10 Bus Keeping Support 2134 10 1 5 4 WAIT Pin Monitoring Control 2134 10 1 5 4 1 Wait Monitoring During an Asynchronous Read Access 2134 10 1 5 4 2 Wait Monitoring During an Asynchronous Write Access 2136 10 1 5 4 3 Wait Monitoring During a Synchronous Read Access 2136 10 1 5 4 4 Wa...

Page 31: ...m Integration 2233 10 2 3 1 Clocking Reset and Power Management Scheme 2234 10 2 3 1 1 Clocking 2234 10 2 3 1 2 Hardware Reset 2235 10 2 3 1 3 Software Reset 2235 10 2 3 1 4 Power Management 2235 10 2 4 SDRC Subsystem Functional Description 2236 10 2 4 1 SDRAM Memory Scheduler 2236 10 2 4 1 1 Memory Access Scheduling 2238 10 2 4 1 2 Arbitration Policy 2238 10 2 4 1 3 Internal Class Arbitration 224...

Page 32: ...Rotation Mechanism 2277 10 2 6 1 2 Setting a VRFB Context 2279 10 2 6 1 3 Applicative Use Case and Tips 2282 10 2 6 2 SMS Mode of Operation 2285 10 2 6 2 1 SDRAM Memory Scheduler and Arbitration Policy 2285 10 2 6 2 2 Arbitration Decision 2286 10 2 6 2 3 Arbitration Granularity 2288 10 2 6 2 4 How these Mechanisms Interact 2290 10 2 6 3 Understanding SDRAM Subsystem Address Spaces 2295 10 2 6 3 1 ...

Page 33: ...Transfer Overview 2346 11 4 2 FIFO Queue Memory Pool 2348 11 4 3 Addressing Modes 2348 11 4 4 Packed Accesses 2352 11 4 5 Burst Transactions 2353 11 4 6 Endianism Conversion 2353 11 4 7 Transfer Synchronization 2353 11 4 7 1 Software Synchronization 2353 11 4 7 2 Hardware Synchronization 2353 11 4 8 Thread Budget Allocation 2356 11 4 9 FIFO Budget Allocation 2356 11 4 10 Chained Logical Channel Tr...

Page 34: ...nvironment 2406 12 3 MPU Subsystem INTCPS Integration 2407 12 3 1 Clocking Reset and Power Management Scheme 2407 12 3 1 1 MPU Subsystem INTC Clocks 2407 12 3 1 2 Hardware and Software Reset 2408 12 3 1 3 Power Management 2408 12 3 2 Interrupt Request Lines 2408 12 4 Interrupt Controller Functional Description 2410 12 4 1 Interrupt Processing 2413 12 4 1 1 Input Selection 2413 12 4 1 2 Masking 241...

Page 35: ...CONTCONV 0 2472 13 4 6 2 2 Continuous Conversion Mode CONTCONV 1 2473 13 4 6 2 3 ADC Codes Versus Temperature 2473 13 4 7 Functional Register Description 2474 13 4 7 1 Static Device Configuration Registers 2474 13 4 7 2 MPU and or DSP IVA2 2 MSuspend Configuration Registers 2474 13 4 7 3 IVA2 2 Boot Registers 2475 13 4 7 4 PBIAS LITE Control Register 2476 13 4 7 5 Temperature Sensor Control Regist...

Page 36: ...5 13 5 1 15 Force MPU Writes to Be Nonposted 2535 13 5 2 Extended Drain I Os and PBIAS Cells Programming Guide 2536 13 5 2 1 PBIAS Error Generation 2538 13 5 2 2 Critical Timing Requirements 2539 13 5 2 3 Speed Control and Voltage Supply State 2539 13 5 3 Off Mode Preliminary Settings 2539 13 5 4 Pad Configuration Programming Points 2540 13 5 5 I O Power Optimization Guidelines 2542 13 6 SCM Regis...

Page 37: ...ister Manual 2657 14 5 1 Mailbox Register Mapping Summary 2657 14 5 2 Register Description 2657 15 Memory Management Units 2663 15 1 MMU Overview 2664 15 2 MMU Integration 2665 15 2 1 Clock Domains 2665 15 2 2 Power Management 2666 15 2 2 1 System Power Management 2666 15 2 2 2 Module Power Saving 2666 15 2 3 Reset 2667 15 2 4 Interrupts 2667 15 3 MMU Functional Description 2668 15 3 1 MMU Benefit...

Page 38: ... 16 2 3 3 GP Timer Interrupts 2711 16 2 4 GP Timers Functional Description 2712 16 2 4 1 GP Timers Block Diagram 2712 16 2 4 2 Timer Mode Functionality 2714 16 2 4 2 1 1 ms Tick Generation Only GPTIMER1 GPTIMER2 and GPTIMER10 2715 16 2 4 3 Capture Mode Functionality 2717 16 2 4 4 Compare Mode Functionality 2718 16 2 4 5 Prescaler Functionality 2719 16 2 4 6 Pulse Width Modulation 2719 16 2 4 7 Tim...

Page 39: ...anual 2765 16 7 1 32 kHz Sync Timer Instance Summary 2765 16 7 2 32 kHz Sync Timer Register Mapping Summary 2765 16 7 3 32 kHz Sync Timer Register Descriptions 2765 17 Multimaster High Speed I2 C Controller 2767 17 1 HS I2 C Overview 2768 17 2 HS I2 C Environment 2770 17 2 1 HS I2 C in I2 C Mode 2770 17 2 1 1 HS I2 C Pins for Typical Connections in I2 C Mode 2770 17 2 1 2 HS I2 C Interface Typical...

Page 40: ...2791 17 4 4 2 HS I2 C FIFO Polling Mode Operation 2793 17 4 4 3 HS I2 C FIFO DMA Mode Operation I2 C Mode Only 2793 17 4 4 4 HS I2 C Draining Feature I2 C Mode Only 2794 17 4 5 HS I2 C Programmable Multislave Channel Feature I2 C Mode Only 2795 17 4 6 HS I2 C Automatic Blocking of the I2 C Clock Feature I2 C Mode Only 2795 17 4 7 HS I2 C Clocking 2795 17 4 8 HS I2 C Noise Filter 2797 17 4 9 HS I2 ...

Page 41: ...ocol Initialization 2844 18 2 2 3 Communication Sequence HDQ and 1 Wire Protocols 2844 18 3 HDQ 1 Wire Integration 2846 18 3 1 Clocking Reset and Power Management Scheme 2846 18 3 1 1 HDQ 1 Wire Clocks 2846 18 3 1 2 HDQ 1 Wire Reset Scheme 2846 18 3 1 3 HDQ 1 Wire Power Domain 2847 18 3 2 Hardware Requests 2847 18 4 HDQ 1 Wire Functional Description 2848 18 4 1 HDQ 1 Wire Block Diagram 2848 18 4 2...

Page 42: ...9 2 1 System Using UART Communication with Hardware Handshake 2873 19 2 2 System Using IrDA Communication Protocol 2873 19 2 3 System Using CIR Communication Protocol with Remote Control 2873 19 2 4 UART Interface Description 2874 19 2 4 1 UART Interface Description 2874 19 2 4 2 UART Protocol and Data Format 2874 19 2 5 IrDA Functional Interfaces 2875 19 2 5 1 UART3 Interface Description 2875 19 ...

Page 43: ...te Generation 2904 19 4 4 1 2 Choosing the Appropriate Divisor Value 2904 19 4 4 1 3 UART Data Formatting 2905 19 4 4 1 4 UART Mode Interrupt Management 2909 19 4 4 2 IrDA Mode UART3 Only 2910 19 4 4 2 1 IrDA Clock Generation Baud Generator 2910 19 4 4 2 2 Choosing the Appropriate Divisor Value 2911 19 4 4 2 3 IrDA Data Formatting 2912 19 4 4 2 4 SIR Mode DATA Formatting 2913 19 4 4 2 5 MIR and FI...

Page 44: ... 2982 20 3 3 Multichannel SPI Protocol and Data Format 2983 20 3 3 1 Transfer Format 2984 20 4 McSPI Integration 2987 20 4 1 McSPI Description 2987 20 4 2 Clocking Reset and Power Management Scheme 2987 20 4 2 1 Clocking 2987 20 4 2 2 Power Domain 2988 20 4 2 3 Hardware Reset 2988 20 4 2 4 Software Reset 2988 20 4 3 Hardware Requests 2989 20 4 3 1 DMA Requests 2989 20 4 3 2 Interrupt Requests 2990...

Page 45: ...e Mode 3011 20 6 McSPI Basic Programming Model 3012 20 6 1 Initialization of Modules 3012 20 6 2 Transfer Procedures without FIFO 3012 20 6 2 1 Common Transfer Procedure 3013 20 6 2 2 End of Transfer Procedure 3013 20 6 2 3 Transmit and Receive Procedure 3015 20 6 2 4 Transmit Only Procedure 3016 20 6 2 4 1 Based on Interrupt Requests 3016 20 6 2 4 2 Transmit Only Based on DMA Write Requests 3016 ...

Page 46: ...al Protocol and Data Formats 3065 21 2 4 2 1 Protocol 3065 21 2 4 2 2 Data Format 3065 21 2 4 3 Audio Protocol and Data Formats 3066 21 2 4 3 1 Protocol 3066 21 2 4 3 2 Data Formats 3066 21 2 4 4 Voice Protocol and Data Formats 3068 21 2 4 4 1 Protocol 3068 21 2 4 4 2 Data Formats 3068 21 3 McBSP Integration 3069 21 3 1 Signal Source Control 3073 21 3 1 1 McBSP1 Module 6 Pins Configuration 3073 21...

Page 47: ...Cycle Mode 3103 21 4 2 8 4 Receive Half Cycle Mode 3103 21 4 3 McBSP SRG 3104 21 4 3 1 Clock Generation in the SRG 3105 21 4 3 2 Frame Sync Generation in the SRG 3106 21 4 3 2 1 Choosing the Width of the Frame sync Pulse 3106 21 4 3 2 2 Controlling the Period Between the Starting Edges of Frame Sync Pulses 3106 21 4 3 2 3 Keeping FSG Synchronized to an External Clock 3107 21 4 3 3 Synchronizing SR...

Page 48: ...ceiver Configuration 3133 21 5 1 5 1 Resetting Step 1 and Enabling Step 3 the Receiver 3133 21 5 1 5 2 Programming the McBSP Registers for the Desired Receiver Configuration Step 2 3134 21 5 1 6 Transmitter Configuration 3142 21 5 1 6 1 Resetting Step 1 and Enabling Step 3 the Transmitter 3142 21 5 1 6 2 Programming the McBSP Registers for the Desired Transmitter Operation Step 2 3143 21 5 1 7 Gen...

Page 49: ...d USB Controller Interface Selection 3226 22 1 5 2 Enable Simulation Acceleration Features 3226 22 1 5 3 Enabling MSTANDBY in Force Standby Mode 3227 22 1 5 4 Power Management Basic Programming Model 3227 22 1 5 4 1 High Speed USB Controller Not Used for Application 3227 22 1 5 4 2 High Speed USB Controller in Host Mode 3227 22 1 5 4 3 High Speed USB Controller in Peripheral Mode 3228 22 1 5 4 4 H...

Page 50: ...anagement and Emulations 3277 22 2 4 2 5 Multimode Serial Port 3278 22 2 4 2 6 Attach Connect Emulation for Serial TLL Modes 3279 22 2 4 2 7 Save and Restore 3280 22 2 5 High Speed USB Host Subsystem Basic Programming Model 3281 22 2 5 1 Selecting and Configuring USB Connectivity 3281 22 2 5 1 1 ULPI Interface Selection 3282 22 2 5 1 2 Serial Interface Selection 3283 22 2 5 2 USBTLL Registers 3284...

Page 51: ...a Buffer Status 3388 24 4 4 Transfer Process 3389 24 4 4 1 Different Types of Commands 3389 24 4 4 2 Different Types of Responses 3389 24 4 5 Transfer or Command Status and Error Reporting 3389 24 4 5 1 Busy Timeout For R1b R5b Response Type 3390 24 4 5 2 Busy Timeout After Write CRC Status 3390 24 4 5 3 Write CRC Status Timeout 3391 24 4 5 4 Read Data Timeout 3391 24 4 5 5 Boot Acknowledge Timeou...

Page 52: ...MMC SD SDIO Registers 3423 24 7 2 1 MMC SD SDIO Register Summary 3423 24 7 2 2 MMCHS Registers 3424 25 General Purpose Interface 3463 25 1 General Purpose Interface Overview 3464 25 1 1 Global Features 3464 25 2 General Purpose Interface Environment 3466 25 2 1 GPIO as a Keyboard Interface 3466 25 2 2 General Purpose Interface Functional Interfaces 3468 25 2 2 1 General Purpose Interface Pins 3468...

Page 53: ...em Input Clocks 3514 26 2 2 2 2 Optional System Input Clock sys_altclk 3515 26 2 2 2 3 Optional System Output Clock sys_clkout1 and sys_clkout2 3515 26 2 2 3 Reset Configuration 3515 26 2 3 Boot Configuration 3516 26 3 Power Clocks and Reset Power Up Sequence 3520 26 4 Device Initialization by ROM Code 3520 26 4 1 Booting Overview 3520 26 4 1 1 Booting Types 3520 26 4 1 2 Main Features 3521 26 4 2...

Page 54: ...70 26 4 8 2 1 CHSETTINGS 3571 26 4 8 2 2 CHRAM 3572 26 4 8 2 3 CHFLASH 3573 26 4 8 2 4 CHMMCSD 3574 26 4 8 3 Image Format for GP Devices 3575 26 4 8 4 Image Execution 3575 26 4 9 Tracing 3576 26 5 Wake Up Booting by ROM Code 3578 26 6 Debug Configuration 3582 26 6 1 Overview 3582 26 6 2 JTAG Port Signal Description 3582 26 6 3 Initial Scan Chain Configuration 3582 26 6 4 Adding TAPs to the Scan Ch...

Page 55: ...n 3612 27 3 4 1 SDTI Block Diagram 3612 27 3 4 2 SDTI Ownership 3612 27 3 4 2 1 Ownership States 3612 27 3 4 2 2 Ownership Commands 3613 27 3 4 2 3 Claim Bits 3613 27 3 4 2 4 Claim Resets 3614 27 3 4 3 Trace Data Collection 3614 27 3 4 4 Trace Buffer FIFO 3615 27 3 4 5 Serial Interface Test Pattern Generation 3615 27 3 4 5 1 Simple Patterns 3616 27 3 4 5 2 Walking Ones 3616 27 3 4 5 3 Ramp Pattern...

Page 56: ...ing 3656 A 2 2 2 3 L4 Peripheral Memory Space Mapping 3656 A 3 Power Reset and Clock Management 3658 A 3 1 PRCM Environment 3658 A 3 2 PRCM Use Guidelines 3659 A 4 IVA2 2 Subsystem 3659 A 4 1 IVA2 2 Subsystem Overview 3659 A 4 2 IVA2 2 Subsystem Hardware Requests 3660 A 4 2 1 DMA Requests 3660 A 4 2 2 Interrupt Requests 3660 A 4 3 IVA2 2 Subsystem Use Guidelines 3663 A 5 Camera Image Signal Proces...

Page 57: ...Guidelines 3695 A 16 High Speed USB Host Subsystem 3695 A 16 1 Overview 3695 A 16 2 High Speed USB Host Subsystem Use Guidelines 3696 A 17 General Purpose Interface 3696 A 17 1 General Purpose Interface Overview 3696 A 17 2 General Purpose Interface Environment 3696 A 18 Initialization 3698 A 18 1 Overview 3698 A 18 2 Preinitialization 3698 A 18 2 1 Power Connections 3698 A 18 3 Clock and Reset 36...

Page 58: ...nterface Detailed View 242 3 13 External Clock Interface 243 3 14 PRCM External Clock Sources 244 3 15 External Reset Signals 245 3 16 Power Control Interface for External Power IC 245 3 17 PRCM Integration 247 3 18 Device Power Domains 248 3 19 PRCM Reset Signals 250 3 20 Reset Manager Interface With Generic Power Domain 251 3 21 Reset Sources Overview 253 3 22 Reset Destination Overview 255 3 23...

Page 59: ...ock Controls Part 1 341 3 66 CORE Power Domain Clock Controls Part 2 342 3 67 EFUSE Power Domain Clock Controls 343 3 68 DSS Power Domain Clock Controls 344 3 69 CAM Power Domain Clock Controls 345 3 70 USBHOST Power Domain Clock Controls 345 3 71 WKUP Power Domain Clock Controls 346 3 72 PER Power Domain Clock Controls Part 1 347 3 73 PER Power Domain Clock Controls Part 2 348 3 74 SMARTREFLEX Po...

Page 60: ...Integration Overview 678 4 3 MPU Subsystem Clocking Scheme 679 4 4 MPU Subsystem Reset Scheme 681 4 5 MPU Subsystem Power Domain Overview 685 5 1 IVA2 2 Subsystem Highlight 694 5 2 IVA2 2 Subsystem Integration 696 5 3 IVA2 2 Subsystem Resets 698 5 4 IVA2 2 Power Domain 700 5 5 IVA2 2 EDMA Requests 701 5 6 IVA2 2 Interrupt Management 703 5 7 IVA2 2 Subsystem Block Diagram 706 5 8 DSP Megamodule Blo...

Page 61: ...P CSI1 CCP2 RAW 6 1107 6 15 Camera ISP CSI1 CCP2 RAW 7 1108 6 16 Camera ISP CSI1 CCP2 RAW8 1109 6 17 Camera ISP CSI1 CCP2 RAW10 1110 6 18 Camera ISP CSI1 CCP2 RAW12 1111 6 19 Camera ISP CSI1 CCP2 JPEG8 and JPEG8 FSP 1112 6 20 Camera ISP CSI2 Two Data Lane Merger Configuration 1113 6 21 Camera ISP CSI2 One Data Lane Configuration 1113 6 22 Camera ISP CSI2 Protocol Layer With Short and Long Packets ...

Page 62: ...ram 1176 6 67 Camera ISP CSI2 RAW Image Transcoding Diagram 1179 6 68 Camera ISP CSI2 Frame Cropping 1180 6 69 Camera ISP CSI2 SHORT_PACKET Field Format 1182 6 70 Camera ISP CSI2 Virtual Channel to Context 1183 6 71 Camera ISP CSI2 Pixel Data Destination Setting in Progressive and Interlaced Mode 1185 6 72 Camera ISP CSI2 PHY Overview 1185 6 73 Camera ISP CSIPHY Power FSM 1186 6 74 Camera ISP CSI2...

Page 63: ...Eye Removal 1264 6 111 Camera ISP CCDC Dependencies Among Framing Settings in Data Flow 1267 6 112 Camera ISP CCDC CCDC_VD0_IRQ CCDC_VD1_IRQ Interrupt Behavior When VDPOL 0 1269 6 113 Camera ISP CCDC CCDC_VD0_IRQ CCDC_VD1_IRQ Interrupt Behavior When VDPOL 1 1269 6 114 Camera ISP CCDC CCDC_VD2_IRQ Interrupt Behavior 1269 6 115 Camera ISP CCDC HS VS Sync Pulse Output Timings 1272 6 116 Camera ISP CC...

Page 64: ...7 36 DSI Video Mode With Burst Two Line Buffers 1592 7 37 Stall Timing With Pixel on Rising Edge 1594 7 38 Stall Timing With Pixel on Falling Edge 1594 7 39 Data Flow in Command Mode Using the Video Port 1595 7 40 Two Data Lane Configuration 1596 7 41 One Data Lane Configuration 1596 7 42 Two Packets Using Two Data Lane Configuration Example 1597 7 43 Protocol Layer With Short and Long Packets 159...

Page 65: ... 1653 7 84 Graphics Destination Transparency Example 1654 7 85 Color Phase Rotation Matrix 1655 7 86 Color Phase Rotation Macro Architecture 1655 7 87 DSI Protocol Engine 1659 7 88 DSI Transmitter Receiver Data Flow 1660 7 89 LP to HS Timing 1661 7 90 HS to LP Timing 1662 7 91 HS Command Mode Interleaving 1667 7 92 LP Command Mode Interleaving 1669 7 93 Complex I O Power FSM 1672 7 94 DSI PLL Powe...

Page 66: ...5 7 133 Image With and Without CPR Diagonal Matrix 1736 7 134 Example Image With and Without CPR Standard Matrix 1737 7 135 DSI PLL Programming Blocks 1751 7 136 DSI PLL Go Sequence Manual Mode 1752 7 137 DSI PLL Go Sequence Automatic Mode 1753 7 138 Gated Mode Sequence 1754 7 139 DSI PLL Programming Sequence 1755 7 140 High Speed Clock Transmission 1759 7 141 High Speed Data Transmission 1761 7 1...

Page 67: ...137 10 10 Asynchronous Single Read on an Address Data Nonmultiplexed Device 2141 10 11 Asynchronous Single Read on an Address Data Multiplexed Device 2142 10 12 Asynchronous Single Write on an Address Data Nonmultiplexed Device 2144 10 13 Asynchronous Single Write on an Address Data Multiplexed Device 2145 10 14 Asynchronous Multiple Page Mode Read 2146 10 15 Synchronous Single Read GPMCFCLKDIVIDE...

Page 68: ...ding to BANKALLOCATION 2251 10 54 Simplified View of Bank Row Column vs Row Bank Column Bank Allocation 2252 10 55 Data Multiplexing Scheme 2254 10 56 Data Demultiplexing Scheme 2255 10 57 Generic DDR Data Write and Data Read Waveforms 2261 10 58 Required Synchronization DFF Input Signals 2261 10 59 DLL CDL Architecture 2262 10 60 Simplified DLL CDL Block Diagram 2263 10 61 Natural Scan Order 2266...

Page 69: ... 2444 13 8 Pad Configuration Diagram 2446 13 9 Off Mode Pad Control Overview 2464 13 10 Save and Restore Mechanism Overview 2465 13 11 Wake Up Event Detection Overview 2466 13 12 Functional Block Diagram 2467 13 13 Extended Drain I O 2470 13 14 Functional Block Diagram 2471 13 15 Single Conversion Mode CONTCONV 0 2473 13 16 Continuous Conversion Mode CONTCONV 1 2473 13 17 Overview of the Debug and...

Page 70: ...ck Diagram of GPTIMER1 GPTIMER2 and GPTIMER10 2714 16 8 GPTi TCRR Timing Value 2715 16 9 Block Diagram of the 1 ms Tick Module 2716 16 10 Capture Wave Example for GPTi TCLR 13 CAPT_MODE 0 2718 16 11 Capture Wave Example for GPTi TCLR 13 CAPT_MODE 1 2718 16 12 Timing Diagram of PWM With GPTi TCLR 7 SCPWM Bit 0 2720 16 13 Timing Diagram of PWM With GPTi TCLR 7 SCPWM Bit 1 2720 16 14 WDTs Block Diagr...

Page 71: ...eiver Mode Interrupt Method in F S and HS Modes I2 C Mode 2806 17 33 HS I2 C Master Transmitter Mode DMA Method in F S and HS Modes I2 C Mode 2807 17 34 HS I2 C Master Receiver Mode DMA Method in F S and HS Modes I2 C Mode 2808 17 35 HS I2 C Slave Transmitter Receiver Mode Polling I2 C Mode 2809 17 36 HS I2 C Slave Transmitter Receiver Mode Interrupt I2 C Mode 2810 17 37 HS I2 C Setup Procedure SC...

Page 72: ...4 2977 20 2 Typical Application Using the McSPI 2979 20 3 McSPI Master Mode Full Duplex 2980 20 4 McSPI Master Single Mode Receive Only 2980 20 5 McSPI Slave Mode Full Duplex 2981 20 6 McSPI Slave Single Mode Transmit Only 2981 20 7 McSPI Interface Signals in Master Mode 2982 20 8 McSPI Interface Signals in Slave Mode 2982 20 9 Phase and Polarity Combinations 2984 20 10 Full Duplex Transfer Format...

Page 73: ... 21 6 Audio Data Application 3063 21 7 Voice Data Application 3063 21 8 McBSP Reception Transmission Signal Activity 3065 21 9 Serial Data Formats 3065 21 10 TDM Data Format Word Width 32 Bits Data Length 24 Bits 3066 21 11 I2S Data Format Word Width 32 Bits Data Length 24 Bits 3067 21 12 Left Justified Data Format Word Width 32 Bits Data Length 24 Bits 3067 21 13 Right Justified Data Format Word ...

Page 74: ...Processed Data Interfaces 3123 21 57 Flow Diagram of McBSP Initialization Procedure for Master Mode 3126 21 58 Flow Diagram of McBSP Initialization Procedure for Slave Mode 3127 21 59 Flow Diagram for the SRG Registers Programmation 3130 21 60 Important Tasks to Configure the McBSP Receiver Part 1 3134 21 61 Important Tasks to Configure the McBSP Receiver Part 2 3135 21 62 Range of Programmable Da...

Page 75: ... Pin Bidirectional TLL Using DP DM Encoding With 4 Pin Bidirectional USB Device 3256 22 29 2 Pin Bidirectional TLL Using DAT SE0 Encoding With 3 Pin Bidirectional USB Device 3257 22 30 High Speed USB Subsystem Integration 3261 22 31 High Speed USB Host Controller Architecture 3271 22 32 USBTLL Channel 3274 22 33 Per Configuration Datapath Through USBTLL 3276 22 34 Selecting and Configuring High Sp...

Page 76: ...ATA Mode 3405 24 41 MMC SD SDIO Controller Suspend Flow 3406 24 42 MMC SD SDIO Controller Resume Flow 3407 24 43 MMC SD SDIO Controller Command Transfer Flow With Polling 3408 24 44 MMC SD SDIO Controller Command Transfer Flow With Interrupts 3409 24 45 MMC SD SDIO Controller Clock Frequency Change Flow 3410 24 46 MMC SD SDIO Power Switching Procedure 3411 24 47 Overview 3412 24 48 Environment 341...

Page 77: ...eSD Booting on SD MMC Port 2 3561 26 28 MMC SD Detection Procedure 3562 26 29 SD MMC Booting 3564 26 30 MBR Detection Procedure 3566 26 31 Get MBR Partition 3567 26 32 Image Format 3570 26 33 CH Format 3571 26 34 CONTROL_SAVE_RESTORE_MEM Format 3579 27 1 Debug and Emulation Hardware in the Device 3586 27 2 ICEPick Overview 3588 27 3 ICEPick Overview 3589 27 4 TAP State Transitions 3590 27 5 Multip...

Page 79: ...Space 222 2 10 EDMA View of the IVA2 2 Subsystem Memory Space 223 3 1 States of a Clock Domain 231 3 2 External Clock Signals 243 3 3 External Reset Signals 245 3 4 Power Control Interface 245 3 5 PRCM Power Domains 249 3 6 PRCM Reset Signals 249 3 7 Global Reset Sources 253 3 8 Local Reset Sources 254 3 9 MPU Power Domain Reset Signal 256 3 10 NEON Power Domain Reset Signal 256 3 11 IVA2 Power Do...

Page 80: ... EFUSE Power Domain Clock Gating Control 343 3 52 DSS Power Domain Clock Gating Controls 344 3 53 CAM Power Domain Clock Gating Controls 345 3 54 USBHOST Power Domain Clock Gating Controls 345 3 55 WKUP Power Domain Clock Gating Controls 346 3 56 PER Power Domain Clock Gating Controls 349 3 57 SMARTREFLEX Power Domain Clock Gating Controls 349 3 58 Processor Clock Configuration Controls 351 3 59 P...

Page 81: ...r Register CM_FCLKEN_IVA2 460 3 99 CM_CLKEN_PLL_IVA2 460 3 100 Register Call Summary for Register CM_CLKEN_PLL_IVA2 461 3 101 CM_IDLEST_IVA2 461 3 102 Register Call Summary for Register CM_IDLEST_IVA2 462 3 103 CM_IDLEST_PLL_IVA2 462 3 104 Register Call Summary for Register CM_IDLEST_PLL_IVA2 462 3 105 CM_AUTOIDLE_PLL_IVA2 462 3 106 Register Call Summary for Register CM_AUTOIDLE_PLL_IVA2 463 3 107...

Page 82: ...47 Register Call Summary for Register CM_IDLEST1_CORE 481 3 148 CM_IDLEST3_CORE 481 3 149 Register Call Summary for Register CM_IDLEST3_CORE 482 3 150 CM_AUTOIDLE1_CORE 482 3 151 Register Call Summary for Register CM_AUTOIDLE1_CORE 484 3 152 CM_AUTOIDLE3_CORE 485 3 153 Register Call Summary for Register CM_AUTOIDLE3_CORE 485 3 154 CM_CLKSEL_CORE 485 3 155 Register Call Summary for Register CM_CLKS...

Page 83: ...l Summary for Register CM_AUTOIDLE_PLL 503 3 197 CM_AUTOIDLE2_PLL 504 3 198 Register Call Summary for Register CM_AUTOIDLE2_PLL 504 3 199 CM_CLKSEL1_PLL 504 3 200 Register Call Summary for Register CM_CLKSEL1_PLL 506 3 201 CM_CLKSEL2_PLL 506 3 202 Register Call Summary for Register CM_CLKSEL2_PLL 506 3 203 CM_CLKSEL3_PLL 507 3 204 Register Call Summary for Register CM_CLKSEL3_PLL 507 3 205 CM_CLKS...

Page 84: ... 245 PER_CM Register Summary 524 3 246 CM_FCLKEN_PER 524 3 247 Register Call Summary for Register CM_FCLKEN_PER 525 3 248 CM_ICLKEN_PER 526 3 249 Register Call Summary for Register CM_ICLKEN_PER 527 3 250 CM_IDLEST_PER 527 3 251 Register Call Summary for Register CM_IDLEST_PER 529 3 252 CM_AUTOIDLE_PER 529 3 253 Register Call Summary for Register CM_AUTOIDLE_PER 531 3 254 CM_CLKSEL_PER 532 3 255 R...

Page 85: ...USBHOST 547 3 294 CM_CLKSTST_USBHOST 547 3 295 Register Call Summary for Register CM_CLKSTST_USBHOST 548 3 296 PRM Instance Summary 548 3 297 IVA2_PRM Register Summary 548 3 298 RM_RSTCTRL_IVA2 549 3 299 Register Call Summary for Register RM_RSTCTRL_IVA2 549 3 300 RM_RSTST_IVA2 550 3 301 Register Call Summary for Register RM_RSTST_IVA2 551 3 302 PM_WKDEP_IVA2 552 3 303 Register Call Summary for Re...

Page 86: ...7 3 343 PM_WKEN1_CORE 577 3 344 Register Call Summary for Register PM_WKEN1_CORE 578 3 345 PM_MPUGRPSEL1_CORE 579 3 346 Register Call Summary for Register PM_MPUGRPSEL1_CORE 581 3 347 PM_IVA2GRPSEL1_CORE 581 3 348 Register Call Summary for Register PM_IVA2GRPSEL1_CORE 583 3 349 PM_WKST1_CORE 583 3 350 Register Call Summary for Register PM_WKST1_CORE 585 3 351 PM_WKST3_CORE 585 3 352 Register Call ...

Page 87: ...SS 602 3 392 Register Call Summary for Register RM_RSTST_DSS 603 3 393 PM_WKEN_DSS 603 3 394 Register Call Summary for Register PM_WKEN_DSS 604 3 395 PM_WKDEP_DSS 604 3 396 Register Call Summary for Register PM_WKDEP_DSS 604 3 397 PM_PWSTCTRL_DSS 605 3 398 Register Call Summary for Register PM_PWSTCTRL_DSS 605 3 399 PM_PWSTST_DSS 605 3 400 Register Call Summary for Register PM_PWSTST_DSS 606 3 401...

Page 88: ..._VC_SMPS_VOL_RA 628 3 442 Register Call Summary for Register PRM_VC_SMPS_VOL_RA 628 3 443 PRM_VC_SMPS_CMD_RA 628 3 444 Register Call Summary for Register PRM_VC_SMPS_CMD_RA 629 3 445 PRM_VC_CMD_VAL_0 629 3 446 Register Call Summary for Register PRM_VC_CMD_VAL_0 629 3 447 PRM_VC_CMD_VAL_1 630 3 448 Register Call Summary for Register PRM_VC_CMD_VAL_1 630 3 449 PRM_VC_CH_CONF 630 3 450 Register Call ...

Page 89: ...er PRM_VP1_STATUS 645 3 491 PRM_VP2_CONFIG 645 3 492 Register Call Summary for Register PRM_VP2_CONFIG 646 3 493 PRM_VP2_VSTEPMIN 646 3 494 Register Call Summary for Register PRM_VP2_VSTEPMIN 646 3 495 PRM_VP2_VSTEPMAX 647 3 496 Register Call Summary for Register PRM_VP2_VSTEPMAX 647 3 497 PRM_VP2_VLIMITTO 647 3 498 Register Call Summary for Register PRM_VP2_VLIMITTO 647 3 499 PRM_VP2_VOLTAGE 648 ...

Page 90: ...USBHOST 661 3 537 SR Instance Summary 661 3 538 SR Register Summary 661 3 539 SRCONFIG 662 3 540 Register Call Summary for Register SRCONFIG 663 3 541 SRSTATUS 663 3 542 Register Call Summary for Register SRSTATUS 664 3 543 SENVAL 664 3 544 Register Call Summary for Register SENVAL 664 3 545 SENMIN 665 3 546 Register Call Summary for Register SENMIN 665 3 547 SENMAX 665 3 548 Register Call Summary...

Page 91: ...5 8 IVA2 2 DSP Megamodule Cache Controller Features 741 5 9 Boot Loader Configuration 744 5 10 PDCCMD Programmed Value in IDLE Boot Mode 745 5 11 Header Format Used in Defautl Config Cache Mode 745 5 12 Header Format Used in User Defined Bootstrap Mode 746 5 13 Cache Size Specified by L1PMODE 749 5 14 Cache Size Specified by L1DMODE 750 5 15 Cache Size Specified by L2MODE 750 5 16 Switching Cache ...

Page 92: ... 5 57 Register Call Summary for Register IDMA0_MASK 819 5 58 IDMA0_SOURCE 819 5 59 Register Call Summary for Register IDMA0_SOURCE 819 5 60 IDMA0_DEST 819 5 61 Register Call Summary for Register IDMA0_DEST 819 5 62 IDMA0_COUNT 820 5 63 Register Call Summary for Register IDMA0_COUNT 820 5 64 IDMA1_STAT 820 5 65 Register Call Summary for Register IDMA1_STAT 820 5 66 IDMA1_SOURCE 821 5 67 Register Ca...

Page 93: ... 105 SDMAARBU 833 5 106 Register Call Summary for Register SDMAARBU 834 5 107 UCARBU 834 5 108 Register Call Summary for Register UCARBU 834 5 109 CPUARBD 834 5 110 Register Call Summary for Register CPUARBD 835 5 111 IDMAARBD 835 5 112 Register Call Summary for Register IDMAARBD 835 5 113 SDMAARBD 836 5 114 Register Call Summary for Register SDMAARBD 836 5 115 UCARBD 836 5 116 Register Call Summa...

Page 94: ...Call Summary for Register L1DWB 845 5 155 L1DWBINV 845 5 156 Register Call Summary for Register L1DWBINV 845 5 157 L1DINV 846 5 158 Register Call Summary for Register L1DINV 846 5 159 MARi 846 5 160 Register Call Summary for Register MARi 846 5 161 L2MPFAR 847 5 162 Register Call Summary for Register L2MPFAR 847 5 163 L2MPFSR 847 5 164 Register Call Summary for Register L2MPFSR 847 5 165 L2MPFCR 8...

Page 95: ...Register Call Summary for Register TPCC_DMAQNUM4 866 5 204 TPCC_DMAQNUM5 866 5 205 Register Call Summary for Register TPCC_DMAQNUM5 867 5 206 TPCC_DMAQNUM6 868 5 207 Register Call Summary for Register TPCC_DMAQNUM6 869 5 208 TPCC_DMAQNUM7 869 5 209 Register Call Summary for Register TPCC_DMAQNUM7 870 5 210 TPCC_QDMAQNUM 870 5 211 Register Call Summary for Register TPCC_QDMAQNUM 871 5 212 TPCC_QUET...

Page 96: ... for Register TPCC_CCSTAT 888 5 252 TPCC_MPFAR 888 5 253 Register Call Summary for Register TPCC_MPFAR 888 5 254 TPCC_MPFSR 888 5 255 Register Call Summary for Register TPCC_MPFSR 889 5 256 TPCC_MPFCR 889 5 257 Register Call Summary for Register TPCC_MPFCR 890 5 258 TPCC_MPPAG 890 5 259 Register Call Summary for Register TPCC_MPPAG 891 5 260 TPCC_MPPAj 891 5 261 Register Call Summary for Register ...

Page 97: ...ter Call Summary for Register TPCC_IESRH 912 5 302 TPCC_IPR 913 5 303 Register Call Summary for Register TPCC_IPR 913 5 304 TPCC_IPRH 914 5 305 Register Call Summary for Register TPCC_IPRH 914 5 306 TPCC_ICR 915 5 307 Register Call Summary for Register TPCC_ICR 915 5 308 TPCC_ICRH 916 5 309 Register Call Summary for Register TPCC_ICRH 916 5 310 TPCC_IEVAL 917 5 311 Register Call Summary for Regist...

Page 98: ... 5 350 TPCC_SECRH_Rn 934 5 351 Register Call Summary for Register TPCC_SECRH_Rn 934 5 352 TPCC_IER_Rn 935 5 353 Register Call Summary for Register TPCC_IER_Rn 935 5 354 TPCC_IERH_Rn 936 5 355 Register Call Summary for Register TPCC_IERH_Rn 936 5 356 TPCC_IECR_Rn 937 5 357 Register Call Summary for Register TPCC_IECR_Rn 937 5 358 TPCC_IECRH_Rn 938 5 359 Register Call Summary for Register TPCC_IECRH...

Page 99: ...for Register TPCC_CIDXm 954 5 400 TPCC_CCNTm 954 5 401 Register Call Summary for Register TPCC_CCNTm 954 5 402 TPTC0 and TPTC1 Register Summary 954 5 403 TPTCj_PID 956 5 404 Register Call Summary for Register TPTCj_PID 956 5 405 TPTCj_TCCFG 956 5 406 Register Call Summary for Register TPTCj_TCCFG 957 5 407 TPTCj_TCSTAT 957 5 408 Register Call Summary for Register TPTCj_TCSTAT 958 5 409 TPTCj_INTST...

Page 100: ...PTCj_SADST 971 5 449 TPTCj_SABIDX 971 5 450 Register Call Summary for Register TPTCj_SABIDX 972 5 451 TPTCj_SAMPPRXY 972 5 452 Register Call Summary for Register TPTCj_SAMPPRXY 972 5 453 TPTCj_SACNTRLD 973 5 454 Register Call Summary for Register TPTCj_SACNTRLD 973 5 455 TPTCj_SASRCBREF 973 5 456 Register Call Summary for Register TPTCj_SASRCBREF 973 5 457 TPTCj_SADSTBREF 974 5 458 Register Call S...

Page 101: ... 498 Register Call Summary for Register WUGEN_MEVT1 988 5 499 WUGEN_MEVT2 989 5 500 Register Call Summary for Register WUGEN_MEVT2 989 5 501 WUGEN_MEVTCLR0 990 5 502 Register Call Summary for Register WUGEN_MEVTCLR0 991 5 503 WUGEN_MEVTCLR1 991 5 504 Register Call Summary for Register WUGEN_MEVTCLR1 992 5 505 WUGEN_MEVTCLR2 992 5 506 Register Call Summary for Register WUGEN_MEVTCLR2 993 5 507 WUGE...

Page 102: ...1012 5 547 Register Call Summary for Register VLCD_IQIN_ADDR 1012 5 548 VLCD_IQOUT_ADDR 1013 5 549 Register Call Summary for Register VLCD_IQOUT_ADDR 1013 5 550 VLCD_VLCDIN_ADDR 1013 5 551 Register Call Summary for Register VLCD_VLCDIN_ADDR 1014 5 552 VLCD_VLCDOUT_ADDR 1014 5 553 Register Call Summary for Register VLCD_VLCDOUT_ADDR 1014 5 554 VLCD_DC_PREDj 1014 5 555 Register Call Summary for Regi...

Page 103: ...gister Call Summary for Register VLCD_SYMTAB_DCUV 1024 5 596 VLCD_SYMTAB_ACi 1024 5 597 Register Call Summary for Register VLCD_SYMTAB_ACi 1024 5 598 VLCD_VLD_CTL 1024 5 599 Register Call Summary for Register VLCD_VLD_CTL 1025 5 600 VLCD_VLD_NRBIT_DC 1025 5 601 Register Call Summary for Register VLCD_VLD_NRBIT_DC 1026 5 602 VLCD_VLD_NRBIT_AC 1026 5 603 Register Call Summary for Register VLCD_VLD_N...

Page 104: ...gister CAVLC_RBTOP 1037 5 644 CAVLC_RBEND 1037 5 645 Register Call Summary for Register CAVLC_RBEND 1037 5 646 CAVLC_BUFPTR 1037 5 647 Register Call Summary for Register CAVLC_BUFPTR 1038 5 648 CAVLC_BITPTR 1038 5 649 Register Call Summary for Register CAVLC_BITPTR 1038 5 650 CAVLC_STRMWDU 1038 5 651 Register Call Summary for Register CAVLC_STRMWDU 1039 5 652 CAVLC_STRMWDL 1039 5 653 Register Call...

Page 105: ...SYSCONFIG 1052 5 695 Register Call Summary for Register VIDEOSYSC_SYSCONFIG 1052 5 696 VIDEOSYSC_IRQMASK 1052 5 697 Register Call Summary for Register VIDEOSYSC_IRQMASK 1052 5 698 VIDEOSYSC_IRQCLR 1053 5 699 Register Call Summary for Register VIDEOSYSC_IRQCLR 1053 5 700 VIDEOSYSC_IRQSET 1053 5 701 Register Call Summary for Register VIDEOSYSC_IRQSET 1053 5 702 VIDEOSYSC_IRQSTATE 1054 5 703 Register...

Page 106: ...r Register iME_IRQLOG 1065 5 743 iME_LATESTERRORS 1065 5 744 Register Call Summary for Register iME_LATESTERRORS 1065 5 745 iME_CONFIGREG 1066 5 746 Register Call Summary for Register iME_CONFIGREG 1066 5 747 iME_SL2INSTADDRESS 1066 5 748 Register Call Summary for Register iME_SL2INSTADDRESS 1066 5 749 iME_COMMANDREG 1067 5 750 Register Call Summary for Register iME_COMMANDREG 1067 5 751 iLF Regis...

Page 107: ...gister iLF_COMMANDREG 1078 5 792 IA_GEM Register Mapping Summary 1079 5 793 GEM_AGENT_STATUS 1079 5 794 Register Call Summary for Register GEM_AGENT_STATUS 1080 5 795 IA_EDMA Register Mapping Summary 1080 5 796 EDMA_AGENT_STATUS 1080 5 797 Register Call Summary for Register EDMA_AGENT_STATUS 1081 5 798 IA_SEQ Register Mapping Summary 1081 5 799 SEQ_AGENT_STATUS 1082 5 800 Register Call Summary for...

Page 108: ...era ISP VPBE Preview Image Cropping by Preview Functions 1212 6 41 Camera ISP VPBE Resizer Use Constraints 1213 6 42 Camera ISP VPBE Resizer Arrangement of the Filter Coefficients 1217 6 43 Camera ISP VPBE Resizer Input Size Calculations 1218 6 44 Camera ISP VPBE Resizer Processing Example for 1 2 56 Horizontal Resize 1223 6 45 Camera ISP Histogram White Balance Field to Pattern Assignments 1226 6...

Page 109: ...egister Call Summary for Register ISP_SYSCONFIG 1304 6 86 ISP_SYSSTATUS 1304 6 87 Register Call Summary for Register ISP_SYSSTATUS 1305 6 88 ISP_IRQ0ENABLE 1305 6 89 Register Call Summary for Register ISP_IRQ0ENABLE 1307 6 90 ISP_IRQ0STATUS 1308 6 91 Register Call Summary for Register ISP_IRQ0STATUS 1311 6 92 ISP_IRQ1ENABLE 1311 6 93 Register Call Summary for Register ISP_IRQ1ENABLE 1314 6 94 ISP_...

Page 110: ... 6 138 Register Call Summary for Register CBUFFx_WINDOWSIZE 1337 6 139 CBUFFx_THRESHOLD 1337 6 140 Register Call Summary for Register CBUFFx_THRESHOLD 1337 6 141 CBUFFx_ADDRy 1338 6 142 Register Call Summary for Register CBUFFx_ADDRy 1338 6 143 CBUFF_VRFB_CTRL 1338 6 144 Register Call Summary for Register CBUFF_VRFB_CTRL 1339 6 145 ISP_CCP2 Register Summary 1340 6 146 CCP2_REVISION 1341 6 147 Regi...

Page 111: ... 1364 6 187 Register Call Summary for Register CCP2_LCx_DAT_SIZE 1364 6 188 CCP2_LCx_DAT_PING_ADDR 1365 6 189 Register Call Summary for Register CCP2_LCx_DAT_PING_ADDR 1365 6 190 CCP2_LCx_DAT_PONG_ADDR 1365 6 191 Register Call Summary for Register CCP2_LCx_DAT_PONG_ADDR 1365 6 192 CCP2_LCx_DAT_OFST 1366 6 193 Register Call Summary for Register CCP2_LCx_DAT_OFST 1366 6 194 CCP2_LCM_CTRL 1366 6 195 ...

Page 112: ...Register CCDC_SDR_ADDR 1383 6 235 CCDC_CLAMP 1384 6 236 Register Call Summary for Register CCDC_CLAMP 1384 6 237 CCDC_DCSUB 1385 6 238 Register Call Summary for Register CCDC_DCSUB 1385 6 239 CCDC_COLPTN 1385 6 240 Register Call Summary for Register CCDC_COLPTN 1387 6 241 CCDC_BLKCMP 1387 6 242 Register Call Summary for Register CCDC_BLKCMP 1388 6 243 CCDC_FPC 1388 6 244 Register Call Summary for ...

Page 113: ...283 Register Call Summary for Register HIST_PID 1405 6 284 HIST_PCR 1405 6 285 Register Call Summary for Register HIST_PCR 1405 6 286 HIST_CNT 1406 6 287 Register Call Summary for Register HIST_CNT 1406 6 288 HIST_WB_GAIN 1407 6 289 Register Call Summary for Register HIST_WB_GAIN 1407 6 290 HIST_Rn_HORZ 1407 6 291 Register Call Summary for Register HIST_Rn_HORZ 1408 6 292 HIST_Rn_VERT 1408 6 293 R...

Page 114: ...H3A_AFCOEF110 1419 6 333 H3A_AFCOEF132 1420 6 334 Register Call Summary for Register H3A_AFCOEF132 1420 6 335 H3A_AFCOEF154 1420 6 336 Register Call Summary for Register H3A_AFCOEF154 1420 6 337 H3A_AFCOEF176 1421 6 338 Register Call Summary for Register H3A_AFCOEF176 1421 6 339 H3A_AFCOEF198 1421 6 340 Register Call Summary for Register H3A_AFCOEF198 1421 6 341 H3A_AFCOEF1010 1422 6 342 Register ...

Page 115: ... PRV_WB_DGAIN 1437 6 382 PRV_WBGAIN 1437 6 383 Register Call Summary for Register PRV_WBGAIN 1438 6 384 PRV_WBSEL 1438 6 385 Register Call Summary for Register PRV_WBSEL 1440 6 386 PRV_CFA 1440 6 387 Register Call Summary for Register PRV_CFA 1440 6 388 PRV_BLKADJOFF 1441 6 389 Register Call Summary for Register PRV_BLKADJOFF 1441 6 390 PRV_RGB_MAT1 1441 6 391 Register Call Summary for Register PR...

Page 116: ...54 6 432 Register Call Summary for Register RSZ_OUT_SIZE 1455 6 433 RSZ_IN_START 1455 6 434 Register Call Summary for Register RSZ_IN_START 1456 6 435 RSZ_IN_SIZE 1456 6 436 Register Call Summary for Register RSZ_IN_SIZE 1456 6 437 RSZ_SDR_INADD 1456 6 438 Register Call Summary for Register RSZ_SDR_INADD 1457 6 439 RSZ_SDR_INOFF 1457 6 440 Register Call Summary for Register RSZ_SDR_INOFF 1457 6 44...

Page 117: ...er Call Summary for Register RSZ_VFILT32 1467 6 481 RSZ_VFILT54 1468 6 482 Register Call Summary for Register RSZ_VFILT54 1468 6 483 RSZ_VFILT76 1468 6 484 Register Call Summary for Register RSZ_VFILT76 1468 6 485 RSZ_VFILT98 1469 6 486 Register Call Summary for Register RSZ_VFILT98 1469 6 487 RSZ_VFILT1110 1469 6 488 Register Call Summary for Register RSZ_VFILT1110 1469 6 489 RSZ_VFILT1312 1470 6...

Page 118: ...ary for Register SBL_GLB_REG_6 1486 6 530 SBL_GLB_REG_7 1486 6 531 Register Call Summary for Register SBL_GLB_REG_7 1487 6 532 SBL_CCDC_WR_0 1487 6 533 Register Call Summary for Register SBL_CCDC_WR_0 1488 6 534 SBL_CCDC_WR_1 1488 6 535 Register Call Summary for Register SBL_CCDC_WR_1 1488 6 536 SBL_CCDC_WR_2 1489 6 537 Register Call Summary for Register SBL_CCDC_WR_2 1489 6 538 SBL_CCDC_WR_3 1489...

Page 119: ...02 6 578 SBL_RSZ1_WR_1 1502 6 579 Register Call Summary for Register SBL_RSZ1_WR_1 1503 6 580 SBL_RSZ1_WR_2 1503 6 581 Register Call Summary for Register SBL_RSZ1_WR_2 1503 6 582 SBL_RSZ1_WR_3 1504 6 583 Register Call Summary for Register SBL_RSZ1_WR_3 1504 6 584 SBL_RSZ2_WR_0 1504 6 585 Register Call Summary for Register SBL_RSZ2_WR_0 1505 6 586 SBL_RSZ2_WR_1 1505 6 587 Register Call Summary for ...

Page 120: ...r Call Summary for Register SBL_CSIA_WR_3 1518 6 628 SBL_CSIB_WR_0 1518 6 629 Register Call Summary for Register SBL_CSIB_WR_0 1518 6 630 SBL_CSIB_WR_1 1519 6 631 Register Call Summary for Register SBL_CSIB_WR_1 1519 6 632 SBL_CSIB_WR_2 1519 6 633 Register Call Summary for Register SBL_CSIB_WR_2 1520 6 634 SBL_CSIB_WR_3 1520 6 635 Register Call Summary for Register SBL_CSIB_WR_3 1520 6 636 SBL_SDR...

Page 121: ...er CSI2_CTx_DAT_PONG_ADDR 1548 6 677 CSI2_CTx_IRQENABLE 1548 6 678 Register Call Summary for Register CSI2_CTx_IRQENABLE 1549 6 679 CSI2_CTx_IRQSTATUS 1550 6 680 Register Call Summary for Register CSI2_CTx_IRQSTATUS 1551 6 681 CSI2_CTx_CTRL3 1551 6 682 Register Call Summary for Register CSI2_CTx_CTRL3 1551 6 683 CAMERA_ISP_CSI2_REGS2 Registers Mapping Summary 1552 6 684 CSI2_CTx_TRANSCODEH 1552 6 ...

Page 122: ...ing Parameters 1661 7 32 HS to LP Timing Parameters 1663 7 33 Extra NULL Packet Header 1663 7 34 Extra NULL Packet Payload 1664 7 35 DSI PLL Operation Modes When Not Locked 1686 7 36 16 Bit Interface Configuration 24 Bit Mode 1689 7 37 Read Write Function Description 1690 7 38 Minimum Cycle Time for CSx WE Always Asserted 1690 7 39 100 100 Color Bar Table 1691 7 40 VENC_S_CARR Register Recommended...

Page 123: ...ration 1782 7 76 Vertical Horizontal Accumulator Phase 1784 7 77 Up Sampling Vertical Filter Coefficients Three Taps 1785 7 78 Up Sampling Vertical Filter Coefficients Five Taps 1785 7 79 Up Sampling Horizontal Filter Coefficients Five Taps 1785 7 80 Down Sampling Vertical Filter Coefficients Three Taps 1786 7 81 Down Sampling Vertical Filter Coefficients Five Taps 1787 7 82 Down Sampling Horizont...

Page 124: ...1818 7 129 Register Call Summary for Register DSS_SYSCONFIG 1819 7 130 DSS_SYSSTATUS 1819 7 131 Register Call Summary for Register DSS_SYSSTATUS 1819 7 132 DSS_IRQSTATUS 1819 7 133 Register Call Summary for Register DSS_IRQSTATUS 1820 7 134 DSS_CONTROL 1820 7 135 Register Call Summary for Register DSS_CONTROL 1821 7 136 DSS_CLK_STATUS 1821 7 137 Register Call Summary for Register DSS_CLK_STATUS 18...

Page 125: ...r Register DISPC_GFX_SIZE 1845 7 180 DISPC_GFX_ATTRIBUTES 1845 7 181 Register Call Summary for Register DISPC_GFX_ATTRIBUTES 1847 7 182 DISPC_GFX_FIFO_THRESHOLD 1847 7 183 Register Call Summary for Register DISPC_GFX_FIFO_THRESHOLD 1847 7 184 DISPC_GFX_FIFO_SIZE_STATUS 1847 7 185 Register Call Summary for Register DISPC_GFX_FIFO_SIZE_STATUS 1848 7 186 DISPC_GFX_ROW_INC 1848 7 187 Register Call Sum...

Page 126: ...DISPC_VIDn_CONV_COEF3 1862 7 227 Register Call Summary for Register DISPC_VIDn_CONV_COEF3 1863 7 228 DISPC_VIDn_CONV_COEF4 1863 7 229 Register Call Summary for Register DISPC_VIDn_CONV_COEF4 1863 7 230 DISPC_DATA_CYCLEk 1863 7 231 Register Call Summary for Register DISPC_DATA_CYCLEk 1864 7 232 DISPC_VIDn_FIR_COEF_Vi 1864 7 233 Register Call Summary for Register DISPC_VIDn_FIR_COEF_Vi 1864 7 234 DI...

Page 127: ...ATA_CYCLE3_i 1880 7 277 Register Call Summary for Register RFBI_DATA_CYCLE3_i 1880 7 278 RFBI_VSYNC_WIDTH 1881 7 279 Register Call Summary for Register RFBI_VSYNC_WIDTH 1881 7 280 RFBI_HSYNC_WIDTH 1881 7 281 Register Call Summary for Register RFBI_HSYNC_WIDTH 1881 7 282 VENC_REV_ID 1882 7 283 Register Call Summary for Register VENC_REV_ID 1882 7 284 VENC_STATUS 1882 7 285 Register Call Summary for...

Page 128: ...C_HTRIGGER_VTRIGGER 1896 7 328 VENC_SAVID_EAVID 1896 7 329 Register Call Summary for Register VENC_SAVID_EAVID 1897 7 330 VENC_FLEN_FAL 1897 7 331 Register Call Summary for Register VENC_FLEN_FAL 1897 7 332 VENC_LAL_PHASE_RESET 1897 7 333 Register Call Summary for Register VENC_LAL_PHASE_RESET 1898 7 334 VENC_HS_INT_START_STOP_X 1898 7 335 Register Call Summary for Register VENC_HS_INT_START_STOP_...

Page 129: ...SCONFIG 1910 7 372 DSI_SYSSTATUS 1910 7 373 Register Call Summary for Register DSI_SYSSTATUS 1911 7 374 DSI_IRQSTATUS 1911 7 375 Register Call Summary for Register DSI_IRQSTATUS 1913 7 376 DSI_IRQENABLE 1914 7 377 Register Call Summary for Register DSI_IRQENABLE 1915 7 378 DSI_CTRL 1915 7 379 Register Call Summary for Register DSI_CTRL 1918 7 380 DSI_COMPLEXIO_CFG1 1919 7 381 Register Call Summary...

Page 130: ...VCn_TE 1946 7 424 DSI_VCn_LONG_PACKET_HEADER 1947 7 425 Register Call Summary for Register DSI_VCn_LONG_PACKET_HEADER 1947 7 426 DSI_VCn_LONG_PACKET_PAYLOAD 1948 7 427 Register Call Summary for Register DSI_VCn_LONG_PACKET_PAYLOAD 1948 7 428 DSI_VCn_SHORT_PACKET_HEADER 1948 7 429 Register Call Summary for Register DSI_VCn_SHORT_PACKET_HEADER 1949 7 430 DSI_VCn_IRQSTATUS 1949 7 431 Register Call Su...

Page 131: ...ATUS_0 1978 8 18 OCP_IRQSTATUS_1 1978 8 19 Register Call Summary for Register OCP_IRQSTATUS_1 1978 8 20 OCP_IRQSTATUS_2 1979 8 21 Register Call Summary for Register OCP_IRQSTATUS_2 1979 8 22 OCP_IRQENABLE_SET_0 1979 8 23 Register Call Summary for Register OCP_IRQENABLE_SET_0 1980 8 24 OCP_IRQENABLE_SET_1 1980 8 25 Register Call Summary for Register OCP_IRQENABLE_SET_1 1980 8 26 OCP_IRQENABLE_SET_2...

Page 132: ...rget and Agent Programming 2016 9 28 L3 External Input Flags 2018 9 29 L3_SI_FLAG_STATUS_0 for Application Error 2019 9 30 L3_SI_FLAG_STATUS_1 for Debug Error 2020 9 31 Error Clearing 2024 9 32 MReqInfo Parameter Example 2025 9 33 Instance Summary 2028 9 34 Initiator Agent Common Register Summary 2029 9 35 Initiator Agent Common Register Summary 2029 9 36 Initiator Agent Common Register Summary 20...

Page 133: ...tion Mechanism Common Register Summary 2043 9 76 Protection Mechanism Common Register Summary 2044 9 77 Protection Mechanism Common Register Summary 2044 9 78 L3_PM_ERROR_LOG 2044 9 79 Register Call Summary for Register L3_PM_ERROR_LOG 2045 9 80 L3_PM_CONTROL 2045 9 81 Register Call Summary for Register L3_PM_CONTROL 2046 9 82 L3_PM_ERROR_CLEAR_SINGLE 2046 9 83 Register Call Summary for Register L...

Page 134: ...or Analysis Mode 2076 9 122 Protection Violation Error Identification 2077 9 123 Unsupported Command Address Hole Error Identification 2077 9 124 Reset TA and Module 2077 9 125 Time Out Configuration 2078 9 126 Firewall Configuration 2078 9 127 L4 Core Instance Summary 2078 9 128 L4 Per Instance Summary 2079 9 129 L4 Emu Instance Summary 2080 9 130 L4 WKUP Instance Summary 2080 9 131 L4 IA Registe...

Page 135: ...R_TA Common Register Summary 2090 9 172 PER_TA Common Register Summary 2091 9 173 PER_TA Common Register Summary 2091 9 174 PER_TA Common Register Summary 2091 9 175 EMU_TA Common Register Summary 2091 9 176 EMU_TA Common Register Summary 2092 9 177 WKUP_TA Common Register Summary 2092 9 178 WKUP_TA Common Register Summary 2092 9 179 L4_TA_COMPONENT_L 2093 9 180 Register Call Summary for Register ...

Page 136: ...EGMENT_i_L 2103 9 222 L4_AP_SEGMENT_i_L Reset Values 2103 9 223 L4_AP_SEGMENT_i_H 2104 9 224 Register Call Summary for Register L4_AP_SEGMENT_i_H 2104 9 225 L4_AP_SEGMENT_i_H Reset Values 2105 9 226 L4_AP_PROT_GROUP_MEMBERS_k_L 2105 9 227 Register Call Summary for Register L4_AP_PROT_GROUP_MEMBERS_k_L 2105 9 228 L4_AP_PROT_GROUP_MEMBERS_k_H 2105 9 229 Register Call Summary for Register L4_AP_PROT_...

Page 137: ...5 NAND Interface Bus Operations Summary 2193 10 26 NOR Interface Bus Operations Summary 2194 10 27 GPMC Instance Summary 2195 10 28 GPMC Registers Mapping Summary 2195 10 29 GPMC_REVISION 2196 10 30 Register Call Summary for Register GPMC_REVISION 2196 10 31 GPMC_SYSCONFIG 2196 10 32 Register Call Summary for Register GPMC_SYSCONFIG 2197 10 33 GPMC_SYSSTATUS 2197 10 34 Register Call Summary for Re...

Page 138: ... for Register GPMC_ECC_CONFIG 2218 10 79 GPMC_ECC_CONTROL 2218 10 80 Register Call Summary for Register GPMC_ECC_CONTROL 2218 10 81 GPMC_ECC_SIZE_CONFIG 2219 10 82 Register Call Summary for Register GPMC_ECC_SIZE_CONFIG 2220 10 83 GPMC_ECCj_RESULT 2220 10 84 Register Call Summary for Register GPMC_ECCj_RESULT 2221 10 85 GPMC_BCH_RESULT0_i 2221 10 86 Register Call Summary for Register GPMC_BCH_RESU...

Page 139: ...SMS_RG_ENDj 2305 10 128 Register Call Summary for Register SMS_RG_ENDj 2305 10 129 SMS_CLASS_ARBITER0 2306 10 130 Register Call Summary for Register SMS_CLASS_ARBITER0 2306 10 131 SMS_CLASS_ARBITER1 2307 10 132 Register Call Summary for Register SMS_CLASS_ARBITER1 2307 10 133 SMS_CLASS_ARBITER2 2308 10 134 Register Call Summary for Register SMS_CLASS_ARBITER2 2308 10 135 SMS_INTERCLASS_ARBITER 230...

Page 140: ...176 Register Call Summary for Register SDRC_MR_p 2327 10 177 SDRC_EMR2_p 2327 10 178 Register Call Summary for Register SDRC_EMR2_p 2328 10 179 SDRC_ACTIM_CTRLA_p 2328 10 180 Register Call Summary for Register SDRC_ACTIM_CTRLA_p 2328 10 181 SDRC_ACTIM_CTRLB_p 2328 10 182 Register Call Summary for Register SDRC_ACTIM_CTRLB_p 2329 10 183 SDRC_RFR_CTRL_p 2329 10 184 Register Call Summary for Register...

Page 141: ...gister DMA4_CCRi 2387 11 38 DMA4_CLNK_CTRLi 2388 11 39 Register Call Summary for Register DMA4_CLNK_CTRLi 2388 11 40 DMA4_CICRi 2388 11 41 Register Call Summary for Register DMA4_CICRi 2390 11 42 DMA4_CSRi 2390 11 43 Register Call Summary for Register DMA4_CSRi 2392 11 44 DMA4_CSDPi 2392 11 45 Register Call Summary for Register DMA4_CSDPi 2393 11 46 DMA4_CENi 2394 11 47 Register Call Summary for R...

Page 142: ...egister INTCPS_SYSCONFIG 2424 12 12 INTCPS_SYSSTATUS 2424 12 13 Register Call Summary for Register INTCPS_SYSSTATUS 2424 12 14 INTCPS_SIR_IRQ 2424 12 15 Register Call Summary for Register INTCPS_SIR_IRQ 2425 12 16 INTCPS_SIR_FIQ 2425 12 17 Register Call Summary for Register INTCPS_SIR_FIQ 2425 12 18 INTCPS_CONTROL 2425 12 19 Register Call Summary for Register INTCPS_CONTROL 2426 12 20 INTCPS_PROTE...

Page 143: ... 10 Band Gap Voltage and Temperature Sensor Signals Description 2472 13 11 ADC Code Versus Temperature 2473 13 12 Static Device Configuration Registers 2474 13 13 MSuspendMux Control Registers 2475 13 14 IVA2 2 Boot Registers 2475 13 15 IVA2 2 Boot Modes 2476 13 16 PBIAS Control Register 2476 13 17 Temperature Sensor Register 2476 13 18 Signal Integrity Parameter Control Registers 2476 13 19 DS Pa...

Page 144: ...plexed on WKUPOBSMUX7 2511 13 56 Internal Signals Multiplexed on WKUPOBSMUX8 2512 13 57 Internal Signals Multiplexed on WKUPOBSMUX9 2513 13 58 Internal Signals Multiplexed on WKUPOBSMUX10 2514 13 59 Internal Signals Multiplexed on WKUPOBSMUX11 2515 13 60 Internal Signals Multiplexed on WKUPOBSMUX12 2516 13 61 Internal Signals Multiplexed on WKUPOBSMUX13 2517 13 62 Internal Signals Multiplexed on W...

Page 145: ...ter Call Summary for Register CONTROL_PROT_ERR_STATUS_DEBUG 2586 13 108 CONTROL_STATUS 2586 13 109 Register Call Summary for Register CONTROL_STATUS 2586 13 110 CONTROL_GENERAL_PURPOSE_STATUS 2587 13 111 Register Call Summary for Register CONTROL_GENERAL_PURPOSE_STATUS 2587 13 112 CONTROL_RPUB_KEY_H_0 2587 13 113 Register Call Summary for Register CONTROL_RPUB_KEY_H_0 2587 13 114 CONTROL_RPUB_KEY_...

Page 146: ... Call Summary for Register CONTROL_DEBOBS_1 2598 13 156 CONTROL_DEBOBS_2 2599 13 157 Register Call Summary for Register CONTROL_DEBOBS_2 2599 13 158 CONTROL_DEBOBS_3 2599 13 159 Register Call Summary for Register CONTROL_DEBOBS_3 2599 13 160 CONTROL_DEBOBS_4 2600 13 161 Register Call Summary for Register CONTROL_DEBOBS_4 2600 13 162 CONTROL_DEBOBS_5 2600 13 163 Register Call Summary for Register C...

Page 147: ...T_CODE 2618 13 205 Type Value For CONTROL_MODEM_GPMC_BOOT_CODE 2618 13 206 CONTROL_MODEM_SMS_RG_ATT1 2618 13 207 Register Call Summary for Register CONTROL_MODEM_SMS_RG_ATT1 2618 13 208 Type Value For CONTROL_MODEM_SMS_RG_ATT1 2618 13 209 CONTROL_MODEM_SMS_RG_RDPERM1 2619 13 210 Register Call Summary for Register CONTROL_MODEM_SMS_RG_RDPERM1 2619 13 211 Type Value For CONTROL_MODEM_SMS_RG_RDPERM1 ...

Page 148: ...G_FREQ 2629 13 252 CONTROL_USBHOST_DPLL_SPREADING_FREQ 2629 13 253 Register Call Summary for Register CONTROL_USBHOST_DPLL_SPREADING_FREQ 2629 13 254 CONTROL_AVDAC1 2629 13 255 Register Call Summary for Register CONTROL_AVDAC1 2630 13 256 CONTROL_AVDAC2 2630 13 257 Register Call Summary for Register CONTROL_AVDAC2 2631 13 258 CONTROL_CAMERA_PHY_CTRL 2631 13 259 Register Call Summary for Register C...

Page 149: ...LBOX_MSGSTATUS_m 2660 14 15 Register Call Summary for Register MAILBOX_MSGSTATUS_m 2661 14 16 MAILBOX_IRQSTATUS_u 2661 14 17 Register Call Summary for Register MAILBOX_IRQSTATUS_u 2661 14 18 MAILBOX_IRQENABLE_u 2662 14 19 Register Call Summary for Register MAILBOX_IRQENABLE_u 2662 15 1 Power Domains of the MMU Instances 2666 15 2 Power Domains of the MMU Instances 2666 15 3 Reset Domains of the MM...

Page 150: ...MU_FAULT_AD 2699 16 1 Input Output Description 2705 16 2 Clock Power and Reset Domains for GP Timers 2707 16 3 GP Timer PRCM Clock Selection Bits 2707 16 4 GP Timer PRCM Clock Control Bits 2707 16 5 IDLEMODE Settings 2708 16 6 CLOCKACTIVITY Settings 2709 16 7 Timer Interrupt Names and Processor IRQ Mapping 2711 16 8 Value Loaded in GPTi TCRR to Generate 1 ms Tick 2716 16 9 Prescaler Timer Reload V...

Page 151: ...51 Register Call Summary for Register TCVR 2744 16 52 TOCR 2744 16 53 Register Call Summary for Register TOCR 2744 16 54 TOWR 2744 16 55 Register Call Summary for Register TOWR 2745 16 56 WD Timers Default State for GP and EMU devices 2746 16 57 Clock Power and Reset Domains for WDTs 2747 16 58 WDT PRCM Clock Control Bits 2748 16 59 IDLEMODE Settings 2748 16 60 CLOCKACTIVITY Settings 2749 16 61 WD...

Page 152: ...Summary for Register REG_32KSYNCNT_CR 2766 17 1 HS I2 C Input Output 2770 17 2 HS I2 C Input Output 2776 17 3 HS I2 C Input Output Description for I2C4 2779 17 4 HS I2 C Power Management Modes 2784 17 5 HS I2 C State of the Interface and Functional Clocks When the Module is in Idle Mode 2784 17 6 HS I2 C Wake Up Events 2785 17 7 HS I2 C DMA Requests 2787 17 8 HS I2 C Interrupt Requests 2787 17 9 H...

Page 153: ... 2835 17 49 I2C_BUFSTAT 2836 17 50 Register Call Summary for Register I2C_BUFSTAT 2836 17 51 I2C_OA1 2836 17 52 Register Call Summary for Register I2C_OA1 2837 17 53 I2C_OA2 2837 17 54 Register Call Summary for Register I2C_OA2 2837 17 55 I2C_OA3 2837 17 56 Register Call Summary for Register I2C_OA3 2837 17 57 I2C_ACTOA 2838 17 58 Register Call Summary for Register I2C_ACTOA 2838 17 59 I2C_SBLOCK ...

Page 154: ...ests to System DMA 2888 19 17 UART DMA Requests to IVA2 2 Subsystem DMA 2889 19 18 Wake Up Requests From PRCM 2889 19 19 TX FIFO Trigger Level Setting Summary 2892 19 20 RX FIFO Trigger Level Setting Summary 2892 19 21 UART IrDA CIR Register Access Mode Programming Using LCR_REG 2898 19 22 Sub Configuration_Mode_A Mode Summary 2899 19 23 Sub Configuration_Mode_B Mode Summary 2899 19 24 Sub Operati...

Page 155: ...5 XON2_ADDR2_REG 2948 19 66 Register Call Summary for Register XON2_ADDR2_REG 2948 19 67 XOFF1_REG 2948 19 68 Register Call Summary for Register XOFF1_REG 2948 19 69 TCR_REG 2949 19 70 Register Call Summary for Register TCR_REG 2949 19 71 MSR_REG 2949 19 72 Register Call Summary for Register MSR_REG 2950 19 73 SPR_REG 2950 19 74 Register Call Summary for Register SPR_REG 2950 19 75 XOFF2_REG 2951 ...

Page 156: ...114 Register Call Summary for Register SYSC_REG 2968 19 115 SYSS_REG 2968 19 116 Register Call Summary for Register SYSS_REG 2968 19 117 WER_REG 2969 19 118 Register Call Summary for Register WER_REG 2970 19 119 CFPS_REG 2970 19 120 Register Call Summary for Register CFPS_REG 2970 19 121 RXFIFO_LVL_REG 2971 19 122 Register Call Summary for Register RXFIFO_LVL_REG 2971 19 123 TXFIFO_LVL_REG 2971 19...

Page 157: ... for Register MCSPI_SYST 3043 20 34 MCSPI_MODULCTRL 3044 20 35 Register Call Summary for Register MCSPI_MODULCTRL 3044 20 36 MCSPI_CHxCONF 3045 20 37 Register Call Summary for Register MCSPI_CHxCONF 3048 20 38 MCSPI_CHxSTAT 3048 20 39 Register Call Summary for Register MCSPI_CHxSTAT 3049 20 40 MCSPI_CHxCTRL 3050 20 41 Register Call Summary for Register MCSPI_CHxCTRL 3050 20 42 MCSPI_TXx 3051 20 43...

Page 158: ... Effect on Transmit Clock and MCBSPLP CLKX Pin 3148 21 34 Using McBSP Pins for General Purpose I O 3150 21 35 Selection of the SIDETONE Input and Output Channels 3153 21 36 McBSP Instance Summary 3154 21 37 McBSP1 Registers Mapping Summary 3154 21 38 McBSP5 Registers Mapping Summary 3155 21 39 McBSP2 Registers Mapping Summary 3156 21 40 McBSP3 Registers Mapping Summary 3157 21 41 McBSP4 Registers ...

Page 159: ...er MCBSPLP_XCERD_REG 3182 21 86 MCBSPLP_RCERE_REG 3182 21 87 Register Call Summary for Register MCBSPLP_RCERE_REG 3183 21 88 MCBSPLP_RCERF_REG 3183 21 89 Register Call Summary for Register MCBSPLP_RCERF_REG 3183 21 90 MCBSPLP_XCERE_REG 3184 21 91 Register Call Summary for Register MCBSPLP_XCERE_REG 3184 21 92 MCBSPLP_XCERF_REG 3184 21 93 Register Call Summary for Register MCBSPLP_XCERF_REG 3185 21...

Page 160: ...Call Summary for Register MCBSPLP_STATUS_REG 3203 21 134 ST_REV_REG 3204 21 135 Register Call Summary for Register ST_REV_REG 3204 21 136 ST_SYSCONFIG_REG 3204 21 137 Register Call Summary for Register ST_SYSCONFIG_REG 3204 21 138 ST_IRQSTATUS_REG 3205 21 139 Register Call Summary for Register ST_IRQSTATUS_REG 3205 21 140 ST_IRQENABLE_REG 3205 21 141 Register Call Summary for Register ST_IRQENABLE...

Page 161: ...cks 3263 22 35 High Speed USB Controller L3 Master Interface Clock 3264 22 36 USBTLL Module Interface Clock 3264 22 37 High Speed USB Host Controller PRCM Clock Control Bits 3265 22 38 High Speed USB Host Controller MIDLEMODE Settings 3266 22 39 High Speed USB Host Controller SIDLEMODE Settings 3267 22 40 High Speed USB Host Controller CLOCKACTIVITY Settings 3267 22 41 USBTLL Module PRCM Clock Con...

Page 162: ...3298 22 83 Register Call Summary for Register ULPI_FUNCTION_CTRL_i 3298 22 84 ULPI_FUNCTION_CTRL_SET_i 3299 22 85 Register Call Summary for Register ULPI_FUNCTION_CTRL_SET_i 3299 22 86 ULPI_FUNCTION_CTRL_CLR_i 3299 22 87 Register Call Summary for Register ULPI_FUNCTION_CTRL_CLR_i 3300 22 88 ULPI_INTERFACE_CTRL_i 3300 22 89 Register Call Summary for Register ULPI_INTERFACE_CTRL_i 3301 22 90 ULPI_IN...

Page 163: ...PI_UTMI_VCONTROL_EN_CLR_i 3316 22 131 Register Call Summary for Register ULPI_UTMI_VCONTROL_EN_CLR_i 3317 22 132 ULPI_UTMI_VCONTROL_STATUS_i 3317 22 133 Register Call Summary for Register ULPI_UTMI_VCONTROL_STATUS_i 3317 22 134 ULPI_UTMI_VCONTROL_LATCH_i 3317 22 135 Register Call Summary for Register ULPI_UTMI_VCONTROL_LATCH_i 3318 22 136 ULPI_UTMI_VSTATUS_i 3318 22 137 Register Call Summary for R...

Page 164: ...Summary for Register HCPERIODCURRENTED 3333 22 180 HCCONTROLHEADED 3333 22 181 Register Call Summary for Register HCCONTROLHEADED 3333 22 182 HCCONTROLCURRENTED 3333 22 183 Register Call Summary for Register HCCONTROLCURRENTED 3334 22 184 HCBULKHEADED 3334 22 185 Register Call Summary for Register HCBULKHEADED 3334 22 186 HCBULKCURRENTED 3334 22 187 Register Call Summary for Register HCBULKCURRENT...

Page 165: ...TBASE 3352 22 229 Register Call Summary for Register PERIODICLISTBASE 3352 22 230 ASYNCLISTADDR 3352 22 231 Register Call Summary for Register ASYNCLISTADDR 3353 22 232 CONFIGFLAG 3353 22 233 Register Call Summary for Register CONFIGFLAG 3353 22 234 PORTSC_i 3353 22 235 Register Call Summary for Register PORTSC_i 3355 22 236 INSNREG00 3355 22 237 Register Call Summary for Register INSNREG00 3356 2...

Page 166: ...nabling High Speed With CMD6 3421 24 28 MMCHS_SYSCTL Value 3421 24 29 Setting Block Length 3421 24 30 Setting Number of Blocks 3422 24 31 CMD25 Issuing 3422 24 32 CMD18 Issuing 3423 24 33 Instance Summary 3423 24 34 MMC SD SDIO Register Summary 3423 24 35 MMCHS_SYSCONFIG 3424 24 36 Register Call Summary for Register MMCHS_SYSCONFIG 3425 24 37 MMCHS_SYSSTATUS 3426 24 38 Register Call Summary for Re...

Page 167: ...egister Call Summary for Register MMCHS_AC12 3457 24 77 MMCHS_CAPA 3458 24 78 Register Call Summary for Register MMCHS_CAPA 3459 24 79 MMCHS_CUR_CAPA 3460 24 80 Register Call Summary for Register MMCHS_CUR_CAPA 3460 24 81 MMCHS_REV 3461 24 82 Register Call Summary for Register MMCHS_REV 3461 25 1 I O Pin Description 3468 25 2 Clocks 3470 25 3 Interrupts 3473 25 4 Wake Up Signals 3474 25 5 GPIO Cha...

Page 168: ...EBOUNCENABLE 3501 25 46 Register Call Summary for Register GPIO_DEBOUNCENABLE 3501 25 47 GPIO_DEBOUNCINGTIME 3502 25 48 Register Call Summary for Register GPIO_DEBOUNCINGTIME 3502 25 49 GPIO_CLEARIRQENABLE1 3502 25 50 Register Call Summary for Register GPIO_CLEARIRQENABLE1 3503 25 51 GPIO_SETIRQENABLE1 3503 25 52 Register Call Summary for Register GPIO_SETIRQENABLE1 3503 25 53 GPIO_CLEARIRQENABLE2...

Page 169: ...dard Device Requests Supported 3540 26 29 Blocks and Sectors Searched on Non XIP Memories 3543 26 30 XIP Timing Parameters 3544 26 31 NAND Timing Parameters 3545 26 32 Supported NAND Devices 3546 26 33 Fourth NAND ID Data Byte 3547 26 34 ID2 Byte Description 3551 26 35 Bad Block Mark Locations in NAND Spare Areas 3552 26 36 Hamming Code Parity Bit Locations 3553 26 37 Master Boot Record Structure ...

Page 170: ...es 3609 27 28 CPU1 Timestamped Message 3610 27 29 CPU1 Message 3610 27 30 CPU2 Timestamped Message 3610 27 31 CPU2 Message 3611 27 32 Ownership Commands 3613 27 33 Claim Bits 3613 27 34 FIFO Data Organization 3615 27 35 Test Pattern Format 3615 27 36 Simple Test Pattern 3616 27 37 Walking Test Pattern 3616 27 38 sdti_clk Divider Value 3617 27 39 SDTI Memory Mapping 3617 27 40 Channel Access Exampl...

Page 171: ...VICE_ID 3632 27 74 DEVICE_TYPE_REG 3632 27 75 Register Call Summary for Register DEVICE_TYPE_REG 3632 27 76 PERIPHERAL_ID4 3632 27 77 Register Call Summary for Register PERIPHERAL_ID4 3633 27 78 PERIPHERAL_ID5 3633 27 79 Register Call Summary for Register PERIPHERAL_ID5 3633 27 80 PERIPHERAL_ID6 3634 27 81 Register Call Summary for Register PERIPHERAL_ID6 3634 27 82 PERIPHERAL_ID7 3634 27 83 Regis...

Page 172: ...ck Signals 3659 A 5 IVA2 2 Subsystem EDMA Request Mapping 3660 A 6 IVA2 2 Interrupt Mappings 3660 A 7 Camera ISP Functions 3663 A 8 IO Description 3663 A 9 Display Subsystem I O Pins 3666 A 10 L3 Initiator Agents 3668 A 11 L3 Target Agents 3668 A 12 L4 Core Initiator Agent 3669 A 13 L4 Core Target Agents 3669 A 14 L4 PER Initiator Agent 3669 A 15 L4 PER Target Agents 3670 A 16 GPMC I O Description...

Page 173: ...ns After a Warm Reset 3701 B 1 Camera ISP I O Description 3705 B 2 GPMC I O Description 3706 B 3 UART I O Description 3707 B 4 UART IrDA CIR Instance Summary 3707 B 5 McSPI I O Description 3708 B 6 GPIO Channel Description 3709 B 7 Core Control Module Pad Configuration Register Fields 3712 B 8 WKUP Control Module Pad Configuration Register Fields 3722 173 SWPU177N December 2009 Revised November 20...

Page 175: ...s The following link connects to TI community resources Linked contents are provided AS IS by the respective contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki Established to assist developers using the many Embedded Processors from Texas Instruments to get star...

Page 176: ...cessing DSP products 800 336 5236 Or write to Texas Instruments Incorporated Market Communications Manager MS 736 P O Box 1443 Houston Texas 77251 1443 Order Texas Instruments documentation Call the CRC 1 hotline 800 336 5236 1 Texas Instruments Customer Response Center 176 Read This First SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 177: ... case the user at his own expense will be required to take whatever measures may be required to correct this interference Information About Cautions and Warnings This book may contain cautions and warnings CAUTION This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment WARNING This is an example of a warning state...

Page 178: ...bit field UART UASR 4 0 For a bit call Module name Register name pos Bit name bit for example UART UASR 5 BIT_BY_CHAR bit Bit name bit Module name Register name pos for example BIT_BY_CHAR bit UART UASR 5 To help the reader navigate the document each register call is hyperlinked to its register description in the register manual section After each register description a table summarizes all hyperl...

Page 179: ...by g_p g_pSDMA_LogicalChan Function Starts with the module name PRCM_SetupClocks ArmIntC_MaskInterrupts Typedef Ends with _t PRCM_Struct_t Definition Starts with the module name and is followed by the define SMS_ERR_TYPE volatileUint32 0x680080F4 register name define MCBSP2_RCR1_REG volatile Uint32 0x4807401C Enumeration Starta with the module name Typedef enum DMA_Mode_Label INPUT_MODE OUTPUT_MOD...

Page 180: ... in a sub process subroutine or another set of flow charts General I O function information available for processing input or Data or I O recording of processed information output Terminal point in a flow chart start stop halt delay or interrupt may Terminator show exit from a closed subroutine Annotation Additional descriptive clarification comment On page connector reference Exit to or entry fro...

Page 181: ...word for which you want to search 4 Click Search 5 The results appear in page order and if applicable show a few words of context Each result displays an icon to identify the type of occurrence All other searchable areas display the Search Result icon 6 To display the page that contains a search result click an item in the Results list The occurrence is highlighted 7 To navigate to the next result...

Page 182: ...E TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES LOST PROFITS LOSS OF USE LOSS OF DATA OR ANY INCIDENTAL CONSEQUENTIAL DIRECT INDIRECT OR SPECIAL DAMAGES WHETHER UNDER CONTRACT TORT WARRANTY OR OTHERWISE ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY...

Page 183: ...ffiliated companies in the United States and other countries DiskOnChip is a trademark of M Systems OpenGL is a trademark of Silicon Graphics Inc OpenVG is a trademark of Khronous Group Inc SD is a registered trademark of Toshiba Corporation eSD is a trademark of SD Association MMC and eMMC are trademarks of MultiMediaCard Association SonicsMX Sonics3220 are trademarks or registered trademarks of ...

Page 184: ... 6 Camera ISP Chapter 7 Display Subsystem Chapter 10 Memory Subsystem Chapter 11 SDMA Chapter 13 System Control Module Chapter 19 UART IrDA CIR Chapter 22 High Speed USB Host Subsytem and High Speed USB OTG Controller Chapter 26 Initialization Added Appendix A OMAP36x1 Multimedia Device 4 Public Version of OMAP36xx Multimedia Device Silicon Revision 1 1 Technical Reference Manual version E SWPU177...

Page 185: ...pacted by changes between version H and version I Chapter 1 Introduction Chapter 2 MemoryMapping Chapter 3 Power Reset and Clock Management Chapter 6 Camera Image Signal Processor Chapter 7 Display Subsystem Chpater 10 Memory Subsystem Chapter 21 Multichannel Buffered Serial Port Chapter 26 Initialization 9 Public Version of OMAP36xx Multimedia Device Silicon Revision 1 x Technical Reference Manua...

Page 186: ...Device in CUS Package Removed the PRELIMINARY banner Device is now in production 13 Public Version of OMAP36xx Multimedia Device Silicon Revision 1 x Technical Reference Manual version N SWPU177 Chapters impacted by changes between version M and version N Chapter 1 Introduction Chapter 3 Power Reset and Clock Management Chapter 6 Camera Image Signal Processor Chapter 7 Display Subsystem Chapter 13...

Page 187: ...ent is strictly for wireless cellular software developers using OMAP3630 application processors which are not available for the broad market through authorized distributors Topic Page 1 1 Overview 188 1 2 Environment 189 1 3 Description 191 1 4 POP Concept 197 1 5 OMAP36xx Family 198 1 6 Device Identification 200 187 SWPU177N December 2009 Revised November 2010 Introduction Copyright 2009 2010 Tex...

Page 188: ...SGX530 subsystem for 2D and 3D graphics acceleration to support display and gaming effects Camera image signal processor ISP2P that supports multiple formats and interfacing options to a wide variety of image sensors Display subsystem with a wide variety of features for multiple concurrent image manipulation and a programmable interface supporting a wide variety of displays The display subsystem a...

Page 189: ...nt The device is associated with a power integrated circuit IC TI provides a global solution with the TWL50xx device Figure 1 1 is an overview of a nonexhaustive environment for the OMAP36xx device 189 SWPU177N December 2009 Revised November 2010 Introduction Copyright 2009 2010 Texas Instruments Incorporated ...

Page 190: ... DSI I2C2 TWL50xx HSUSB0 I2C4 SR I2C1 HDQ or UART4 McBSP2 McBSP3 TI WL128x WLAN BT FM GPS FM 76 108 MHz SDMMC2 UART2 USB3 UART1 Mobile TV DSS S VIDEO Y C CVIDEO CSI2 CAM ISP CCPV2 or CSI1 2 I2C3 NC Cellular subsystem intro_177 001 JTAG SDRC DDR 200MHz 2CS 32bit LS LENS HR 8Mpx MIPI CSI2 LR 5Mpx SMIA CCP2 MOTOR IRIS FLASH Camera subsystem Public Version Environment www ti com Figure 1 1 OMAP36xx Hi...

Page 191: ...h speed I C 2 5xMcBSP 2x with sidetone audio buffer 4xMcSPI 6xGPIO 3xHigh speed MMC SDIO HDQ 1Wire 1xMailbox 11xGP timers 2xwatchdog timers 32K Sync timer intro_swpu177 002 HS USB host with USB TLL on chip Camera subsystem 2xSmartReflex Public Version www ti com Description 1 3 Description The device is offered in different packages For more information see Section 1 5 OMAP36xx Family Figure 1 2 i...

Page 192: ...ache 32 byte cache line configurable as cache or memory mapped The possible values are 0 KB cache 32 KB memory 4 KB cache 28 KB memory 8 KB cache 24 KB memory 16 KB cache 16 KB memory 32 KB cache 0 KB memory L1D data 32 KB 2 way set associative cache 4 byte cache line configurable as cache or memory mapped The possible values are 0 KB cache 32 KB memory 4 KB cache 28 KB memory 8 KB cache 24 KB mem...

Page 193: ... chip memory configuration offers memory resources for program and data storage 120 KB ROM 64 KB single access SRAM 1 3 4 External Memory Interfaces The device includes two external memory interfaces supporting the stacking of a multichip memory package using the generic POP interface General purpose memory controller GPMC NOR flash NAND flash with ECC Hamming code calculation SRAM and pseudo SRAM...

Page 194: ...grained task switching load balancing and power management Programmable high quality image anti aliasing Advanced geometry DMA driven operation for minimum CPU interaction Fully virtualized memory addressing for OS operation in a unified memory architecture Advanced and standard 2D operations for example vector graphics block level transfers raster operations etc 32K stride support Camera ISP2P su...

Page 195: ...tive body bias Retention until access memories 1 3 8 Peripherals The device supports a comprehensive set of peripherals to provide flexible and high speed interfacing and on chip programming resources Universal asynchronous receiver transmitter UART 1 2 4 Three general serial communication interfaces UART 3 UART IrDA SIR up to FIR TV remote control interface CIR Multichannel buffered serial port 1...

Page 196: ...hronization timer 32 kHz clock timer General purpose input output GPIO Six 32 bit GPIO controllers Mailbox MPU IVA2 2 interprocessor communications six in stacked mode two in stand alone mode ICR only in stacked mode Control module I O multiplexing and chip configuration control 196 Introduction SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 197: ...cted directly to the two memory interfaces GPMC and SDRC of the POP device through the POP interface present at the top For more information about the interconnect between the stacked memory package and the POP device see Chapter 10 Memory Subsystem Figure 1 3 shows the concept of the POP solution and Figure 1 4 shows stacked memory package on the POP device Figure 1 3 POP Concept Figure 1 4 Stack...

Page 198: ...de power to a top memory device or provide specific memory signals from the bottom BGA to the POP interface NOTE It is possible to monitor the DDR SDRAM temperature if the memory multichip package allows the temperature sensing option A feedthrough is used to lower the temperature sensing dedicated signal to make a connection with a GPIO For more information about DDR SDRAM temperature sensing man...

Page 199: ...vices are offered in 515 ball plastic ball grid array s PBGA suffix CBP CBC and in 423 ball s PBGA suffix CUS packages For more information see Table 1 3 and Appendix A OMAP36xx Multimedia Devices in CUS Package Table 1 2 lists the available OMAP36xx family packages and their features Table 1 2 OMAP36xx Packages Package Type CBP CBC CBK CUS CYN Size mm 12 12 14 14 14 14 16 16 12 12 Ball count 515 ...

Page 200: ...s are read only accessed ports that are programmed into eFuses FARM FROM The device type and some options can be read in the CONTROL CONTROL_PRODUCTION_ID register Table 1 4 CONTROL_PRODUCTION_ID Address Offset 0x0000 0208 Physical Address 0x4830 A208 Instance GENERAL Description This register shows the device type and some available options Type R 72 71 64 63 9 8 7 6 5 4 3 2 1 0 127 RESERVED RESE...

Page 201: ...SIZE MPU subsystem L2 cache size R 0x 0x0 0KB 0x1 Reserved 0x2 128KB 0x3 256KB 9 3 RESERVED Reserved R 0x 2 IVA2_DSP IVA2 2 DSP R 0x 0x0 DSP of IVA2 2 is available 0x1 DSP of IVA2 2 is not available 1 0 RESERVED Reserved R 0x Table 1 6 and Table 1 7 describe the identification registers For the memory space address of the test chip level TAP device see Chapter 2 Memory Mapping Table 1 6 Device Ide...

Page 202: ...IDCODE 27 12 0xB891 Table 1 9 Revision Number Value Silicon Type Bit Field Value ES1 0 CONTROL CONTROL_IDCODE 31 28 0x0 ES1 1 CONTROL CONTROL_IDCODE 31 28 0x1 ES1 2 CONTROL CONTROL_IDCODE 31 28 0x2 Table 1 10 CONTROL_IDCODE Register Value Silicon Type Bit Field Value OMAP36xx ES1 0 CONTROL CONTROL_IDCODE 31 0 0x0B89 102F OMAP36xx ES1 1 CONTROL CONTROL_IDCODE 31 0 0x1B89 102F OMAP36xx ES1 2 CONTROL...

Page 203: ... high tier device In unavailable modules and features the memory area is reserved read is undefined and write can lead to unpredictable behavior Topic Page 2 1 Introduction 204 2 2 Global Memory Space Mapping 206 2 3 L3 and L4 Memory Space Mapping 209 2 4 IVA2 2 Subsystem Memory Space Mapping 218 203 SWPU177N December 2009 Revised November 2010 Memory Mapping Copyright 2009 2010 Texas Instruments ...

Page 204: ... for SDRAM memories such as regular SDR SDRAM single data rate regular JEDEC DDR1 memory double data rate low power SDR SDRAM and mobile DDR SDRAM For more information see Chapter 10 Memory Subsystem The L3 interconnect allows the sharing of resources such as peripherals and external or on chip memories among all the initiators of the platform The L4 interconnects control access to the peripherals...

Page 205: ...2C3 UART1 UART2 McBSP1 McBSP5 GPTIMER10 GPTIMER11 Mailbox McSPI1 McSPI2 McSPI3 McSPI4 MMC SD SDIO1 MMC SD SDIO2 HDQ 1 Wire ICR camera ISP HS USB OTG MODEM INTC MPU INTC MMC SD SDIO3 L4 interconnect emulation L4 interconnect wake up GPTIMER1 WDT2 GPIO1 32KTIMER External peripherals ports External and stacked memories External peripherals ports L3 interconnect L4 USB HS OTG L4 L4 L4 L4 OCM RAM Emula...

Page 206: ...s0 to gpmc_ncs7 are available in the first quarter Q0 of the addressing space to access NOR NAND flash and SRAM memories The chip selects have a programmable start address and programmable size 16 32 64 or 128MB in a total memory space of 1GB SDRC space Two SDRC chip selects sdrc_ncs0 and sdrc_ncs1 are available on the third quarter Q2 of the addressing space to access SDRAM memories The chip sele...

Page 207: ...d 0x5001 0000 0x53FF FFFF 65 472KB Reserved L4 emulation 64MB Emulation L4 Emu 0x5400 0000 0x547F FFFF 8MB See Table 2 6 Reserved 0x5480 0000 0x57FF FFFF 56MB Reserved Reserved 64MB Reserved Reserved 0x5800 0000 0x5BFF 0FFF 64MB Reserved IVA2 2 64MB IVA2 2 subsystem subsystem IVA2 2 0x5C00 0000 0x5EFF FFFF 48MB IVA2 2 subsystem See subsystem Table 2 8 Reserved 0x5F00 0000 0x5FFF FFFF 16MB Reserved...

Page 208: ...S CS0 SDRAM 4 0x8000 0000 0x9FFF FFFF 512MB SDRC SMS CS1 SDRAM 4 0xA000 0000 0xBFFF FFFF 512MB SDRC SMS Q3 Reserved 512MB Reserved 1GB Reserved 0xC000 0000 0xDFFF FFFF 512MB Reserved for future use SDRC SMS 512MB SDRC SMS SDRC SMS 0xE000 0000 0xFFFF FFFF 512MB SDRC SMS virtual address virtual space 1 Address space 1 4 Chip select 0 and chip select 1 spaces are configurable in the 1 GB SDRC SMS spa...

Page 209: ...get agent configuration registers RT Register target global configuration registers PM Protection mechanism firewalls configuration registers SI Global sideband signal configuration registers For more information see Chapter 9 Interconnect This section describes all modules and features in the high tier device In unavailable modules and features the memory area is reserved read is undefined and wr...

Page 210: ...port agent configuration Reserved 0x6800 7000 0x6800 FFFF 36 Reserved RT PM 0x6801 0000 0x6801 03FF 1 Register target port protection Reserved 0x6801 0400 0x6801 23FF 8 Reserved GPMC PM 0x6801 2400 0x6801 27FF 1 GPMC target port protection OCM RAM PM 0x6801 2800 0x6801 2BFF 1 OCM RAM target port protection OCM ROM PM 0x6801 2C00 0x6801 2FFF 1 OCM ROM target port protection D2D PM 0x6801 3000 0x680...

Page 211: ... Display subsystem top Display subsystem top 0x4805 0400 0x4805 07FF 1KB Display controller Display controller 0x4805 0800 0x4805 0BFF 1KB RFBI Remote frame buffer interface 0x4805 0C00 0x4805 0FFF 1KB Video encoder RFBI Video encoder VENC 0x4805 1000 0x4805 1FFF 4KB L4 interconnect Reserved 0x4805 2000 0x4805 5FFF 16KB Reserved sDMA 0x4805 6000 0x4805 6FFF 4KB Module 0x4805 7000 0x4805 7FFF 4KB L...

Page 212: ...x4809 EFFF 4KB Reserved 0x4809 F000 0x4809 FFFF 4KB Reserved Reserved 0x480A 0000 0x480A AFFF 44KB Reserved HS USB OTG 0x480A B000 0x480A BFFF 4KB Module 0x480A C000 0x480A CFFF 4KB L4 interconnect MMC SD SDIO3 0x480A D000 0x480A DFFF 4KB Module 0x480A E000 0x480A EFFF 4KB L4 interconnect Reserved 0x480A F000 0x480A FFFF 4KB Reserved Reserved 0x480B 0000 0x480B 0FFF 4KB Reserved 0x480B 1000 0x480B...

Page 213: ...p Memory Space Mapping Device Name Start Address End Address Size KB Description Hex Hex L4 Wakeup 0x4830 0000 0x4833 FFFF 256 Reserved 0x4830 0000 0x4830 5FFF 24 Reserved Power and reset manager 0x4830 6000 0x4830 7FFF 8 Module region A Power manager 0x4830 8000 0x4830 87FF 2 Module region B 1 Reset manager 0x4830 8800 0x4830 8FFF 2 Reserved 0x4830 9000 0x4830 9FFF 4 L4 interconnect Reserved 0x48...

Page 214: ...x4902 2FFF 4KB Module audio for codec 0x4902 3000 0x4902 3FFF 4KB L4 interconnect McBSP3 0x4902 4000 0x4902 4FFF 4KB Module Bluetooth voice data 0x4902 5000 0x4902 5FFF 4KB L4 interconnect McBSP4 0x4902 6000 0x4902 6FFF 4KB Module digital baseband voice data 0x4902 7000 0x4902 7FFF 4KB L4 interconnect McBSP2 sidetone 0x4902 8000 0x4902 8FFF 4KB Module 0x4902 9000 0x4902 9FFF 4KB L4 interconnect Mc...

Page 215: ...ng The L4 Emu interconnect is an 8 MB space composed of the L4 Emu interconnect configuration registers and module registers Table 2 6 describes the mapping of the registers for the L4 Emu interconnect NOTE All memory spaces described as modules provide direct access to the module registers outside the L4 Emu interconnect All other accesses are internal to the L4 Emu interconnect Table 2 6 L4 Emul...

Page 216: ... domain 3 0x5471 9000 0x5471 9FFF 4KB L4 interconnect Reserved 0x5471 A000 0x5471 FFFF 24KB Reserved 32KTIMER 0x5472 0000 0x5472 0FFF 4KB Module WKUP domain 3 0x5472 1000 0x5472 1FFF 4KB L4 interconnect Reserved 0x5472 2000 0x5472 7FFF 24KB Reserved L4 Wakeup configuration 0x5472 8000 0x5472 87FF 2KB AP WKUP domain 3 0x5472 8800 0x5472 8FFF 2KB IP L4 Core 0x5472 9000 0x5472 9FFF 4KB LA 0x5472 A000...

Page 217: ... interconnect 8 16 32 L4 Core interconnect 8 16 32 Clock manager 32 Power and reset manager 32 System control module 8 16 32 ICR chassis mode only 32 32KTIMER 16 32 GPIO 8 16 32 GPTIMER 16 32 WDTIMER 16 32 I2C 8 16 HDQ 1 Wire 32 McBSP 32 Sidetone 8 16 32 McSPI 8 16 32 UART 8 16 32 MMC SD SDIO 32 Mailbox 8 16 32 MPU INTC 16 32 MODEM INTC chassis mode only 16 32 SR 8 16 32 217 SWPU177N December 2009...

Page 218: ... 2 subsystem also contains a local interconnect with its own memory space mapping that can be accessed only by the DSP and the video accelerator and sequencer in the IVA2 2 subsystem For more information about this video accelerator sequencer local interconnect and its memory space mapping see Chapter 5 IVA2 2 Subsystem 2 4 1 IVA2 2 Subsystem Internal Memory and Cache Allocation 2 4 1 1 IVA2 2 Sub...

Page 219: ...e allocated to cache there is no more memory mapped L1P After reset the L1D RAM is used as an 80 KB memory mapped RAM The L1D RAM can be programmed in the C64x DSP data memory controller to allocate 0 default 4 8 16 or 32KB to cache When 32KB are allocated to cache 48KB are still allocated to the memory mapped L1D After reset L2 is used as a 96 KB memory mapped RAM L2 can be programmed to allocate...

Page 220: ...A2 2 contains 96KB of L2 RAM The L2 RAM can be configured to allocate up to 64KB to the L2 cache When the L1P and L1D caches are configured to be inactive default configuration DSP accesses to the L2 RAM are accomplished directly and thus suffer the L2 latency When the L1P and L1D RAM are configured to be active DSP program accesses to L2 RAM are always serviced by the L1P cache controller if code...

Page 221: ...5C00 0000 0x5CFF FFFF 16MB Reserved 0x5C00 0000 0x5C7D FFFF 8064KB Reserved L2 ROM 0x5C7E 0000 0x5C7E 3FFF 16KB IVA2 2 internal memories Reserved 0x5C7E 4000 0x5C7F 7FFF 80KB Reserved L2 RAM 0x5C7F 8000 0x5C7F FFFF 32KB IVA2 2 internal memories L2 RAM cache 0x5C80 0000 0x5C80 FFFF 64KB IVA2 2 internal memories Reserved 0x5C81 0000 0x5CDF FFFF 6080KB Reserved L1P RAM cache 0x5CE0 0000 0x5CE0 7FFF 3...

Page 222: ...onfiguration 0x01C0 0000 0x01C0 FFFF 64 DMA transfer engine control registers TPTC0 configuration 0x01C1 0000 0x01C1 03FF 1 DMA transfer scheduler 0 control registers TPTC1 configuration 0x01C1 0400 0x01C1 07FF 1 DMA transfer scheduler 1 control registers Reserved 0x01C1 0800 0x01C1 FFFF 62 Reserved SYSC configuration 0x01C2 0000 0x01C2 0FFF 4 SYSC module control registers WUGEN configuration 0x01...

Page 223: ...ncer configuration registers Reserved 0x0009 0800 0x0009 3FFF 14 Reserved SEQ DMEM 0x0009 4000 0x0009 4FFF 4 Video sequencer data memory Reserved 0x0009 5000 0x0009 7FFF 12 Reserved SEQ IMEM 0x0009 8000 0x0009 9FFF 8 Video sequencer instruction memory Reserved 0x0009 A000 0x0009 BFFF 8 Reserved Video sysc 0x0009 C000 0x0009 CFFF 4 Video system controller Reserved 0x0009 D000 0x0009 FFFF 12 Reserve...

Page 224: ...ption Hex Hex Reserved 0x10F1 8000 0x10FF FFFF 928 Reserved Memories and peripherals 1 0x1100 0000 0xFFFF FFFF 3 915 776 Controlled by the IVA2 2 MMU to access memories and peripherals external to the IVA2 2 subsystem 1 For more information see Chapter 5 IVA2 2 Subsystem 224 Memory Mapping SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 225: ...ration ensure that power domains of unavailable features and modules are switched off and clocks are cut off Topic Page 3 1 Introduction to Power Managements 226 3 2 PRCM Overview 239 3 3 PRCM Environment 242 3 4 PRCM Integration 246 3 5 PRCM Functional Description 251 3 6 PRCM Basic Programming Model 397 3 7 PRCM Use Cases and Tips 447 3 8 PRCM Register Manual 459 225 SWPU177N December 2009 Revis...

Page 226: ...requirements 3 1 2 Power Management Techniques The following sections describe the state of the art power management techniques supported by the device NOTE The values in Figure 3 1 through Figure 3 4 which show power management techniques are hypothetical only They do not represent valid test results on the device 3 1 2 1 Dynamic Voltage and Frequency Scaling Dynamic voltage and frequency scaling...

Page 227: ...tage allowed for a frequency When applying DVFS a processor or system always runs at the lowest OPP that meets the performance requirement at a given time The user determines the optimal OPP for a given task and then switches to that OPP to save power 3 1 2 2 SmartReflex Adaptive Voltage Scaling AVS SmartReflex is a power management technique for automatic control of the operating voltage of a mod...

Page 228: ...is technique consists of maximizing the idle period of the system to reduce its power consumption Figure 3 3 compares energy consumption with and without DPS Figure 3 3 Comparison of Energy Consumed With Without DPS Figure 3 3 compares the power consumption behavior for the same device operation without DPS left side of the figure and with DPS right side of the figure When operating without DPS th...

Page 229: ...ng transistor body bias technique Forward Body Bias FBB for operating clock frequency boost for operation at higher operating performance points OPPs ABB is based on the process corner and the current OPP This is configured in the eFuse at the device characterization and is not continuously updated A dedicated LDO VBBLDO is used to produce the voltage bias 3 1 2 7 Combining Power Management Techni...

Page 230: ...n in Figure 3 4 are for explanation only They do not correspond to validated OPPs of the device Figure 3 4 Performance Level and Applied Power Management Techniques 3 1 3 Architectural Blocks for Power Management The device supports the power management techniques through three architectural blocks the power clock and voltage domains A domain is a group of modules or subsections of the device that...

Page 231: ...k Domain Table 3 1 lists the two possible states of the clock domain Table 3 1 States of a Clock Domain State Description Active The domain clock is running Idle The domain clock is stopped or gated 3 1 3 2 Power Domain A power domain is a section of the device with independent and dedicated power rails see Figure 3 6 A power domain can be turned on off without affecting the other parts of the dev...

Page 232: ...e lowered to its retention value The logic is not functional but is retained Depending on software settings Varray can keep its active value if needed by another memory array in another power domain or be lowered and the arrayon switch can be open or closed depending on the power domain this can be hardwired As a consequence the memory content can be retained or lost Open switch retention OSWR COR...

Page 233: ...ption and then be switched back to normal operating voltage when a wake up event is received 3 1 4 Device Power Management Architecture The device architecture integrates the power management architectural blocks for power management support It is composed of scalable switchable voltage domains their voltage can be controlled and switchable power domains Figure 3 8 shows the general hierarchical a...

Page 234: ...pendently In this state memory is not operational but the content is retained with minimized leakage This feature lets power consumption be reduced when the device is in sleep mode while maintaining memory contents for fast context restore The logic and memory standby feature is software controllable The device supports a clock distribution and control architecture which is described in the follow...

Page 235: ... among the modules From the PRCM module standpoint a functional clock is directly distributed to the related modules through a dedicated clock tree It is identified with an _FCLK suffix NOTE At the module level the interface clocks are always fed by the interface clock outputs of the PRCM module The functional clocks are fed by a PRCM functional clock output or a PRCM interface clock output In the...

Page 236: ...r in the technical reference manual for the corresponding device module If the module is set to smart idle mode it terminates its current operations then acknowledges the idle request to the PRCM module If the module is set to force idle mode it acknowledges immediately regardless of its state Because pending transfers interrupts and DMA requests can be lost special software care must be taken If ...

Page 237: ...ommand that defines the change in the output voltage of the SMPS required to bring it to the desired voltage level The voltage command is sent to the voltage controller which passes it to the power IC through the dedicated I2 C interface The power IC then adjusts the output voltage of the SMPS according to the command In this way the SmartReflex module dynamically adjusts the SMPS voltage to compe...

Page 238: ... the error value and determines the new voltage command to be sent to the SMPS to return the voltage to within the limits The new voltage command is sent to the voltage controller which passes the command to the SMPS and acknowledges its reception In automatic mode the software does not intervene in voltage control the entire loop is handled by the hardware modules 238 Power Reset and Clock Manage...

Page 239: ...ake up dependencies of power domains Support for hardware controlled autogating of module clocks Memory retention capability for preserving memory contents in low power sleep mode Scalable voltage and frequency support for the processors CORE and peripherals for DVFS SmartReflex adaptive voltage scaling for real time performance adjustments Support for low power device off mode input output I O pa...

Page 240: ... vdd_mpu_iva vdd_core vdda_sram LDO VDD3 ctrl VDD4 VDD5 Generic voltage domain Domain voltage Power control logic CORE power domain VDD1 VDD2 sys_off_mode sys_clkout2 sys_clkout1 prcm 010 sys_nvmode1 LDO vdda_wkup_bg_bb i2c4_scl sys_nvmode2 i2c4_sda System control module sys_xtalin sys_xtalgnd Public Version PRCM Overview www ti com Figure 3 11 PRCM Overview 240 Power Reset and Clock Management SW...

Page 241: ...e control Monitoring and handling wake up events Controlling system clock reset input sources Managing and distributing clocks and resets with high granularity Handling power up sequences Debug and emulation features Controlling external supply voltage regulation through dedicated high speed HS I2 C interface CM implementation of RFFs to support DPS 241 SWPU177N December 2009 Revised November 2010...

Page 242: ...t The PRCM module receives the external reset clock and power signals Figure 3 12 shows the interface of the PRCM module with external reset clock and power sources Figure 3 12 PRCM Functional External Interface Detailed View NOTE In the remainder of this chapter power IC refers to a peripheral power source IC that is interfaced with the device It receives power control commands voltage scaling an...

Page 243: ...iption Module Reset Value sys_boot6 I Boot oscillator mode control Unknown 2 sys_32k I 32 kHz clock input Unknown 3 sys_xtalout O Oscillator output 0 sys_xtalin I Main input clock Crystal oscillator clock only at 12 13 16 8 or 19 2 Unknown MHz or CMOS digital clock at 12 13 16 8 19 2 26 or 38 4 MHz sys_clkreq I O Clock request to from device for system clock HiZ 1 4 sys_clkout1 O Configurable outp...

Page 244: ...ion can be used at a time An additional clock input sys_altclk provides a precise clock source for 54 MHz 48 MHz or other frequencies for example 59 MHz or 49 04 MHz for VDAC For more information about external clock signals see Section 3 5 3 5 External Clock Controls 3 3 2 External Reset Signals The device supports two reset signals power on sys_nrespwron and warm reset sys_nreswarm sys_nrespwron...

Page 245: ... control the device voltage levels The voltage level of the scalable voltage sources in the external power IC can be scaled by sending commands to the power IC through this interface The PRCM module can also command the power IC to switch the device voltages off when the device is in off mode and activate them when it wakes up Figure 3 16 shows the power control interface for the external power IC...

Page 246: ... WKUP L4 interconnect In addition to the L4 interconnect the PRCM internal module interface contains the following A set of signals for idle wake up control for each module Clocks and reset signals Power control signals switches and memories to the power domains Interrupts to the MPU subsystem and IVA2 2 subsystem INTCs Voltage error commands from the SmartReflex modules Digital phase locked loop ...

Page 247: ...ule x2 CORE power domain Generic power domain x18 Logic Error MPU_INTC IVA2 2 WUGEN PRCM_MPU_IRQ PRCM_IVA_IRQ prcm 016 vdd_mpu_iva vdd_core vdda_sram LDO VDD3 VDD4 VDD5 Domain voltage VDD1 VDD2 LDO vdda_wkup_bg_bb Public Version www ti com PRCM Integration Figure 3 17 PRCM Integration To significantly reduce leakage in sleep modes SLM strategy and to optimize active power consumption DPS strategy ...

Page 248: ...SmartReflex engine domain DPLL1 domain MPU DPLL domain DPLL power domains DPLL2 domain IVA2 DPLL domain DPLL4 domain Peripherals DPLL domain DPLL3 domain CORE DPLL domain prcm 017 USBHOST domain DPLL5 domain domain Peripherals DPLL2 Public Version PRCM Integration www ti com Figure 3 18 Device Power Domains Each power domain is fed through an independent switch controlled by the PRM module In this...

Page 249: ...CM Subsystem Reset Signal PRM PRM_RSTPWRON CM CM_RSTPWRON_RET The PRM module is reset by the cold reset signal PRM_RSTPWRON The CM module is reset by assertion of the CM_RSTPWRON_RET signal The CM logic is reset on Any global cold reset A CORE power domain transition from off to on The PRM logic is reset on any global cold reset CM and PRM registers that are sensitive to a warm reset are also rese...

Page 250: ...PRCM Reset Signals 3 4 1 3 Interrupt Requests The PRCM module can generate two interrupts PRCM_MPU_IRQ Mapped to the MPU INTC module M_IRQ_11 interrupt line PRCM_IVA_IRQ Mapped to the IVA2 2 WUGEN module IVA2_IRQ 12 interrupt line 250 Power Reset and Clock Management SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 251: ...encing the release of resets and ensures a safe reset of the entire power domain Figure 3 20 is an overview of the reset manager interface with a generic power domain in the device Figure 3 20 Reset Manager Interface With Generic Power Domain Resets can be generated by hardware sources or software control For a module that can be reset by software control a software reset bit is implemented in its...

Page 252: ...cold reset in modules that require them For a global warm reset the PRCM module performs the following sequence 1 Applies a warm reset on all the modules including modules built with RFFs 2 Applies a warm reset on the external modem interface 3 Drives the sys_nreswarm reset output low and holds it for a specified length of time programmed in the PRCM PRM_RSTTIME 7 0 RSTTIME1 bit field 4 All ongoin...

Page 253: ...ion Figure 3 21 Reset Sources Overview 3 5 1 3 1 Global Reset Sources Table 3 7 lists the global reset sources of the device The global reset source signals received by the reset manager trigger the reset of all the device modules For all hardware reset signals the source of the reset is identified for the software reset signals the reset triggering bit is identified Table 3 7 Global Reset Sources...

Page 254: ...r domain transition from off or retention state to active state H C IVA2_DOM_RST PRCM H C NEON_DOM_RST PRCM H C SGX_DOM_RST PRCM H C CORE_DOM_RST PRCM H C PER_DOM_RST PRCM H C CAM_DOM_RST PRCM H C DSS_DOM_RST PRCM H C DPLL1_DOM_RST PRCM H C DPLL2_DOM_RST PRCM H C DPLL3_DOM_RST PRCM H C DPLL4_DOM_RST PRCM H C DPLL5_DOM_RST PRCM S W IVA2_SW_RST1 PRCM RM_RSTCTRL_IVA2 0 IVA2 2 DSP reset control RST1_I...

Page 255: ...WRON and one or more reset RST signals These signals behave as follows On any global or local cold reset RST and RSTPWRON are asserted On any global or local warm reset only RST is asserted The CORE power domain receives two additional retention logic reset signals retention reset RST_RET and power on retention reset RSTPWRON_RET These signals behave as follows On any global cold reset or wakeup f...

Page 256: ..._RST2 I PRM Resets the IVA2 2 MMU IVA2_RST3 I PRM Resets the video sequencer module IVA2_RSTPWRON I PRM Performs a power on reset on the IVA2 2 subsystem Active on a cold reset only IVA2_RSTDONE O PRM Release condition of the IVA_RST1 and RST2 Generated by the IVA2 2 subsystem at the end of the initialization sequence 1 I Input O Output 2 Source for an input signal and destination for an output si...

Page 257: ...e CAM power domain has one reset input signal see Table 3 14 Table 3 14 CAM Power Domain Reset Signal Name I O 1 Source Reset Domain CAM_RST I PRM Resets the entire camera subsystem 1 I Input O Output 3 5 1 5 7 USBHOST Power Domain The USBHOST power domain has one reset input signal see Table 3 15 Table 3 15 USBHOST Power Domain Reset Signal Name I O 1 Source Reset Domain USBHOST_RST I PRM Resets ...

Page 258: ...IMER3 modules PER_RST_RET I PRCM Resets the GPIO 2 6 modules 1 I Input O Output 3 5 1 5 11 SmartReflex Power Domain The SmartReflex power domain has one reset input signal see Table 3 19 Table 3 19 SmartReflex Power Domain Reset Signal Name I O 1 Source Reset Domain SR_RST I PRCM Resets the SR1 and SR2 modules 1 I Input O Output 3 5 1 5 12 DPLL Power Domains The DPLL power domains for DPLL1 DPLL2 ...

Page 259: ... Reset Interface Any global reset source internal or external causes sys_nreswarm_out to be driven and maintained at the boundary of the device for at least the amount of time configured in the PRCM PRM_RSTTIME 7 0 RSTTIME1 bit field This ensures that the device and its related peripherals are reset together NOTE Because the system warm reset output is implemented on a bidirectional pad any input ...

Page 260: ... the power domain is active It also provides reset status for the following global reset signals Global cold reset Global warm reset There is one reset activity status signal for each of the following power domains CAM CORE DSS EMU SGX IVA2 MPU NEON PER USBHOST These signals are asserted high on assertion of any source of reset on the domain and logged For information about the SCM see Chapter 13 ...

Page 261: ... logic sys_nreswarm_out VDD1_VM_RST GLOBAL_SW_RST DPLL3_SW_RST VDD2_VM_RST Registers warm reset prcm 023 Public Version www ti com PRCM Functional Description Figure 3 24 Device Reset Manager Overview 261 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 262: ...eset manager 3 IVA2_RST3 IVA2_DOM_RST IVA2_SW_RST2 MPU_DOM_RST IVA2_SW_RST3 CORE_DOM_RET_RST Global warm reset CORE_RST_RET BAD_DEVICE_RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE domain reset manager 4 USBTLL_RST CORE_DOM_RST prcm 024 Public Version PRCM Functional Description www ti com Figure 3 25 Power Domain Re...

Page 263: ...RST CORE_DOM_RET_RST CORE_DOM_RET_RST CORE_DOM_RET_RST prcm 025 PER domain reset manager 2 PER_RST_RET PER_DOM_RET _RST CORE_DOM_RET_RST USBHOST domain reset manager USBHOST_RST USB_DOM_RST CORE_DOM_RET_RST Public Version www ti com PRCM Functional Description Figure 3 26 Power Domain Reset Management Part 2 263 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyrigh...

Page 264: ...USE_RSTPWRON EFUSE_DOM_RST DPLL4_DOM_RST DPLL3_DOM_RST DPLL2_DOM_RST DPLL1_DOM_RST PRM reset manager PRM_RSTPWRON Global power on reset BAD_DEVICE_RST prcm 026 DPLL5 domain reset manager DPLL5_RSTPWRON DPLL5_DOM_RST SR_DOM_RST SR_RST domain reset manager SMARTREFLEX Public Version PRCM Functional Description www ti com Figure 3 27 Power Domain Reset Management Part 3 264 Power Reset and Clock Mana...

Page 265: ...RST1 IVA2_RST2 IVA2_RST3 IVA2_RSTPWRON SGX SGX_RST CORE CORE_RST CORE_RSTPWRON CORE_RST_RET CORE_RSTPWRON_RET CM_RSTPWRON_RET USBTLL_RST WKUP WKUP_RST SYNCT_RST PER PER_RST PER_RST_RET DSS DSS_RST CAM CAM_RST USBHOST USBHOST_RST DPLL1 DPLL1_RSTPWRON DPLL2 DPLL2_RSTPWRON DPLL3 DPLL3_RSTPWRON DPLL4 DPLL4_RSTPWRON DPLL5 DPLL5_RSTPWRON SR SR_RST EFUSE EFUSE_RSTPWRON 1 The shaded blocks identify the po...

Page 266: ...DPLL3_ BAD_ IVA2_SW_ IVA2_SW_ IVA2_SW_ RET_RST RET_RST SW_RST DEVICE_ RST1 RST2 RST3 RESET MPU MPU_RST NEON NEON_RST IVA2 IVA2_RST1 IVA2_RST2 IVA2_RST3 IVA2_RSTPWRON SGX SGX_RST CORE CORE_RST CORE_RST_RET CORE_RSTPWRON_RET CM_RSTPWRON_RET USBTLL_RST WKUP WKUP_RST SYNCT_RST PER PER_RST PER_RST_RET DSS DSS_RST CAM CAM_RST USBHOST USBHOST_RST DPLL1 DPLL1_RSTPWRON DPLL2 DPLL2_RSTPWRON 1 The shaded blo...

Page 267: ...DOM_ DPLL3_ BAD_ IVA2_SW_ IVA2_SW_ IVA2_SW_ RET_RST RET_RST SW_RST DEVICE_ RST1 RST2 RST3 RESET DPLL3 DPLL3_RSTPWRON DPLL4 DPLL4_RSTPWRON DPLL5 DPLL5_RSTPWRON SR SR_RST EFUSE EFUSE_RSTPWRON BANDGAP BANDGAP_RSTPWRON Device pad output sys_nreswarm_out 267 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 268: ...RST DPLL1_ALWON_FCLK MPU_CLK MPU_RST Signal color coding PRCM input PRCM output Other 1 5 4 6 7 8 9 11 12 10 13 14 2 3 15 prcm 096 vdds_mem vdda_sram vdda_dpll_per DPLL 1 2 3 4 5 _ RSTPWRON Public Version PRCM Functional Description www ti com 3 5 1 9 Reset Sequences 3 5 1 9 1 Power Up Sequence Figure 3 28 shows the power up sequence Figure 3 28 Power Up Sequence 268 Power Reset and Clock Manageme...

Page 269: ...mory LDO stabilization 6 Global resets are released Global power on reset and global warm reset are extended remain asserted on release of the external power on reset until the following conditions are met Voltages are stable in the processor power domains CORE power domain and WKUP power domain System clock is stable Internal memory LDO is stable Device reset manager counter overflows set up by t...

Page 270: ...8 V The VDD2 voltage domain vdd_core power rail is regulated at 1 0 V The VDD1 voltage domain vdd_mpu_iva power rail is regulated at 1 2 V The VDD3 VDD4 and VDD5 voltage domains are regulated at 1 2 V The system is running Resets are released CORE DPLL and processor DPLL are locked Figure 3 29 shows the global warm reset sequence 270 Power Reset and Clock Management SWPU177N December 2009 Revised ...

Page 271: ...R_CLK PER_RST Signal color coding PRCM input PRCM output Other BYPASS 5 4 3 2 1 prcm 097 BYPASS Public Version www ti com PRCM Functional Description Figure 3 29 Warm Reset Sequence The steps of a global warm reset sequence are as follows 1 On assertion of the warm reset source The device reset manager resets part of the device by asserting the global warm reset The external warm reset sys_nreswar...

Page 272: ... scaling was performed before the assertion of the warm reset 3 The CORE domain is released from reset warm sensitive modules in CORE power domain 4 The MPU_CLK clock is running 5 The MPU power domain is released from reset The MPU boots NOTE The IVA2 power domain is held under reset after global warm reset by assertion of the software source of the reset Power domains such as PER DSS CAM SGX and ...

Page 273: ...x4 0x0 0x001 0x201 0x301 0x701 11 10 8 9 12 5 7 prcm 029 functional clock Video seqencer Public Version www ti com PRCM Functional Description Figure 3 30 IVA2 2 Subsystem Power Up Reset Sequence The sequence is 1 Software enables the IVA2 2 subsystem clock 273 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 274: ...1 status bit is updated accordingly on release of the IVA2_RST1 reset signal 10 DSP software enables the video sequencer SEQ clock 11 DSP software clears the PRCM RM_RSTCTRL_IVA2 2 RST3_IVA2 bit The PRM waits for reset manager 3 in the IVA2 power domain to time out 12 After reset manager 3 times out the PRM can release the IVA2_RST3 reset signal The SEQ boots 13 The PRCM RM_RSTST_IVA2 10 IVA2_SW_R...

Page 275: ...6 5 7 11 prcm 030 functional clock Video sequencer Public Version www ti com PRCM Functional Description Figure 3 31 IVA2 Software Reset Sequence The sequence is 1 DSP software puts the SEQ in idle and can safely assert the IVA2 power domain software reset 2 The PRM module asserts the IVA2_RST3 reset asynchronously 275 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management C...

Page 276: ...VA2 power domain to time out 12 After reset manager 1 times out the PRM module releases the IVA2_RST1 reset signal The DSP boots 13 The PRCM RM_RSTST_IVA2 8 IVA2_SW_RST1 status bit is updated accordingly on release of the IVA2_RST1 reset signal 14 DSP software enables the SEQ clock 15 DSP software clears the PRCM RM_RSTCTRL_IVA2 2 RST3_IVA2 bit The PRM module waits for reset manager 3 in the IVA2 ...

Page 277: ... 10 0 0x000 0x002 0x7 0x0 5 prcm 031 functional clock Video sequencer Public Version www ti com PRCM Functional Description Figure 3 32 IVA2 Global Warm Reset Sequence The sequence is 1 A global warm reset source is asserted see sys_nreswarm in Figure 3 32 277 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 278: ...eset manager times out 7 The MPU boots and the MPU software sequence shown in Section 3 5 1 9 4 from point 6 starts 3 5 1 9 6 IVA2 Power Domain Wake Up Cold Reset Sequence This section describes the cold reset sequence of the IVA2 2 subsystem when the IVA2 power domain transitions from retention to on power state The assumptions are The MPU is running All sources of reset to the IVA2 are released ...

Page 279: ... IVA2_RST2 IVA2_RST1 IVA2_RST3 RM_RSTST_IVA2 10 0 0x0 0x4 0x4 0x0 8 9 10 11 12 13 14 15 16 17 18 0x7E075 0x404 0x0 5 prcm 032 functional clock Video sequencer Public Version www ti com PRCM Functional Description Figure 3 33 IVA2 Power Domain Power Transition Reset Sequence The sequence is 1 DSP software puts the SEQ in inactive state 279 SWPU177N December 2009 Revised November 2010 Power Reset an...

Page 280: ...l There are two alternate sequences The DSP is held under reset when exiting retention power state This is done when the MPU software writes 1 to the PRCM RM_RSTCTRL_IVA2 0 RST1_IVA2 bit In this case the MPU software must clear this bit to 0 to reboot the DSP The DSP and MMU are held under reset when exiting retention power state the MPU software writes 1 to the PRCM RM_RSTCTRL_IVA2 0 RST1_IVA2 an...

Page 281: ...he hardware features are fully controlled by the PRM part of the PRCM module These features are Device partitioning into 18 power domains Device partitioning into several voltage domains communicating through level shifters Logic power switch control RFF control Memory power switch control Embedded LDOs SRAMs wakeup emulation control I O off mode control Level shifter control External power IC con...

Page 282: ...oning To substantially reduce leakage in sleep modes SLM strategy and to optimize active power consumption savings DPS strategy the device is segmented into 18 power domains MPU Application processor NEON Multimedia coprocessor IVA2 DSP SGX Graphics engine CORE Interconnect memory controllers peripherals and clock management DSS Display subsystem CAM Camera controller PER Low power use case periph...

Page 283: ... ICECrusher CS MPU async bridge master NEON NEON coprocessor IVA2 IVA2 2 DSP IVA2 async bridge 1 master IVA2 async bridge 2 slave Video sequencer SEQ SGX SGX subsystem CORE GPMC USB TLL GPTIMER 10 11 HDQ 1 Wire HS USB I2C 1 2 3 ICR IVA2 2 async bridge 1 slave IVA2 2 async bridge 2 master IVA2 2 WUGEN MAILBOXES McBSP 1 5 McSPI 1 2 3 4 MMC SD SDIO 1 2 3 MPU async bridge slave MPU INTC OCM_RAM OCM_RO...

Page 284: ...DSS USBHOST and EMU power domain memories have their own voltage and power control independent of the logic However the user must ensure that memory states are programmed consistently with the logic state MPU L1 cache memory does not have an independent control and is supplied with the MPU logic CORE memory banks 3 4 5 and 6 are associated to the domain power state and controlled with the domain l...

Page 285: ...made only to retention state without explicitly stating whether it is CSWR or OSWR then the description applies to the two retention states In CSWR and OSWR memories are put in retention or can also be switched off 3 5 2 1 6 Power State Transitions For each power domain the PRM manages all transitions controlling domain clocks domain resets domain logic power switches memory power switches and mem...

Page 286: ...wer mode and ensure correct functioning 3 5 2 1 8 Isolation Between Power Domains When switching a power domain from one state to another the PRCM module automatically manages domain output isolation to prevent electrical damage This mechanism is hardware supervised and does not require software action 3 5 2 2 Power Domain Implementation 3 5 2 2 1 Device Power Domains Table 3 27 summarizes the pow...

Page 287: ...martReflex SR1 SR2 Logic on off EFUSE eFuse farm none MPU DPLL DPLL1 Logic on off IVA2 2 DPLL DPLL2 Logic on off CORE DPLL DPLL3 Logic on off Peripherals DPLL DPLL4 Logic on off Peripherals DPLL2 DPLL5 Logic on off NOTE BB Back bias or local memory retention OSWR Open switch retention CSWR Closed switch retention LDO retention All memories are in BB mode and the memory array is dropped down Logic ...

Page 288: ...pter 13 System Control Module 3 5 2 2 3 Power Domain State Transition Rules As previously described a power domain can reach different states These states are linked to the power applied to the domain and to the domain clock activity Any power state transition always depends on and starts with power domain clock activity control Any active clock in a power domain sets the domain as active see Sect...

Page 289: ...mains see Section 3 5 4 Idle and Wake Up Management and Section 3 6 Basic Programming Model 3 5 2 2 5 2 Power Domain Software Controls If all conditions are met to initiate a power domain state transition all the modules are idle standby and the related clocks are shut down the PRCM module automatically manages the transition according to the following settings Dependencies setting The PRCM CM_SLE...

Page 290: ...PRCM PM_EVGENCTRL_MPU PRCM PM_EVGENONTIM_MPU and PRCM PM_EVGENOFFTIM_MPU let the MPU power domain be switched between on and off or placed in inactive mode The PRCM PM_EVGENONTIM_MPU and PRCM PM_EVGENOFFTIM_MPU registers set the durations of the on and off modes respectively For details see Section 3 6 Basic Programming Model and Section 3 8 PRCM Registers Manual 290 Power Reset and Clock Manageme...

Page 291: ...l 3 5 3 1 Overview The PRCM module provides control for clock generation division distribution synchronization and gating It distributes the clock sources to all modules in the device The device level clock generation is handled by an internal oscillator the system clock oscillator and DPLLs clock division and gating are handled by the PRM and the CM sections of the PRCM module Figure 3 35 shows t...

Page 292: ... clock Ensures proper communication between any module and the system interconnects level 3 L3 or level 4 L4 In most cases the interface clock supplies the interface and registers of the module For some modules the interface clock is also used as the functional clock Functional clock Supplies the functional part of a module or subsystem In some cases a module or subsystem can require several funct...

Page 293: ...ocal system clock crystal oscillator In the latter case a crystal is connected between the sys_xtalout and sys_xtalin device pins The sys_boot 6 pin sets the oscillator operating mode see Figure 3 14 The source system clock can be 12 13 16 8 19 2 26 or 38 4 MHz and can be divided by 2 to provide the standard system clock frequencies using internal system clock divider configuration in the PRCM PRM...

Page 294: ... be divided by 2 4 8 or 16 and its off state polarity is programmable This output is active only when the CORE power domain is active Also the selected source clock must be enabled by software Enabling sys_clkout2 does not automatically request the required source clock 3 5 3 2 3 Summary Table 3 29 summarizes the external clock I O Table 3 29 External Clock I Os Name I O 1 Source Destination Descr...

Page 295: ...VA2_CLK SYS_CLK L3_ICLK L4_ICLK 32K_FCLK 48M_FCLK 12M_FCLK 96M_FCLK DSS_TV_CLK CORE_CLK COREX2_CLK prcm 036 120M_FCLK DPLL5 PER2 Public Version www ti com PRCM Functional Description Figure 3 37 Internal Clock Sources 295 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 296: ...in It supplies most of the clocks in the device Some of the device clocks sourced by SYS_CLK are always powered clocks are present even when the CORE power domain is in off state SYS_CLK is also the source of the WKUP power domain interface clocks It also handles the gating and distribution of the 96 MHz clock from DPLL4 to the CM and PER power domain modules Figure 3 38 is a functional overview o...

Page 297: ...LL4_ALWON_FCLK DPLL5_ALWON_FCLK CM_SYS_CLK SYS_CLK CM_32K_CLK 32K_FCLK Divider 1 2 prcm 037 PRM_192M_ALWON_CLK CM_96M_FCLK 96M_ALWON_FCLK DPLL4 EFUSE_ALWON_FCLK SR_ALWON_FCLK USBTLL_SAR_FCLK USBHOST_SAR_FCLK Divider 1 2 SGX_192M_FCLK Public Version www ti com PRCM Functional Description Figure 3 38 PRM Clock Generator 297 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Managemen...

Page 298: ... and L4 interface clocks supply the device interconnects and all module interface clocks The L4 clock is divided for USB full speed clock limitation at 50 MHz and to supply the reset managers PRM in the WKUP power domain The clocks derived from CORE_CLK are fully balanced over the device The 96M_FCLK 48M_FCLK and 12M_FCLK clocks are functional unbalanced clocks for a number of modules in the CORE ...

Page 299: ...S_CLK DPLL3_M2_CLK DPLL3_M2X2_CLK DPLL4_M2_CLK DPLL4_M3_CLK DSS_TV_FCLK 12M_FCLK 48M_FCLK 96M_FCLK COREX2_CLK DPLL2_FCLK DPLL1_FCLK CORE_CLK L3_ICLK L4_ICLK RM_ICLK to PRM prcm 038 CM_96M_FCLK DPLL5 DPLL5_M2_CLK 120M_FCLK mux CM_SYS_CLK Public Version www ti com PRCM Functional Description Figure 3 39 CM Clock Generator Functional Overview 299 SWPU177N December 2009 Revised November 2010 Power Res...

Page 300: ...4 PER DPLL5 PER2 NOTE This chapter discusses only DPLL1 to DPLL5 because they are directly controlled by the PRCM module Chapter 7 Display Subsystem discusses the DPLLs in the display subsystem The DPLLs are of two types Type A DPLLs are DPLL1 DPLL2 DPLL3 and DPLL5 Type B DPLL is DPLL4 300 Power Reset and Clock Management SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instr...

Page 301: ... not locked and generating the high frequency clock For example DPLL1 and DPLL2 receive the high frequency bypass clock from the DPLL3 output and the reference clock from the PRM module When the DPLL has only one clock input it uses that clock input as the reference clock and bypass clock For example DPLL3 and DPLL5 receive only one input clock from PRM module and it is used as the reference and t...

Page 302: ...t output dividers for simultaneous generation of multiple output clocks with different frequencies 3 5 3 3 3 1 1 DPLL1 MPU and DPLL2 IVA2 DPLL1 and DPLL2 are in the MPU and IVA2 2 subsystems respectively The DPLLs supply the source clocks for their respective subsystems which use the source clocks to internally generate all subsystem clocks DPLL1 and DPLL2 each use a reference clock DPLL1_ALWON_FC...

Page 303: ...h frequency bypass clock and it uses the reference clock as the low frequency bypass clock DPLL3 supplies the source clock for all interfaces and a few functional clocks for the device modules It is also the source of the emulation trace clock While the CORE power domain is on the output of DPLL3 can be used as HS bypass clock input to DPLL1 and DPLL2 3 5 3 3 3 1 3 DPLL5 Peripherals Figure 3 42 is...

Page 304: ...LL5_ALWON_FCLK which is the SYS_CLK from the PRM DPLL5 does not receive a high frequency bypass clock and it uses the reference clock as the low frequency bypass clock DPLL5 generates clocks for the peripherals supplying five clock sources 120 MHz functional clock to the peripheral domain modules 304 Power Reset and Clock Management SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 ...

Page 305: ...y generates one main clock according to the following equation CLKOUT Fref x M N 1 where M is a 12 bit multiplier and N is a 7 bit divider NOTE When M is set to 0 or 1 the DPLL is forced to bypass mode The internal clock CLKOUT of the DPLL can then be used to generate five independent output clocks CLKOUT_M2 CLKOUT M2 CLKOUT_M3 CLKOUT M3 CLKOUT_M4 CLKOUT M4 CLKOUT_M5 CLKOUT M5 CLKOUT_M6 CLKOUT M6 ...

Page 306: ...tput clock is effectively gated or running For an explanation of the DPLL multiplier divider settings and gating controls see Section 3 5 3 6 DPLL Control Each clock generating DPLL of the device has the following features Independent power domain Control by the CM Fed by always on SYS_CLK with independent gating control for the SYS_CLK Analog part supplied by a dedicated power supply VDDPLL and V...

Page 307: ...tios 1 6 5 DPLL4 does not receive a high frequency bypass clock and it uses the reference clock as the low frequency bypass clock DPLL4 generates clocks for the peripherals supplying five clock sources 96 MHz always on source clock for the PRM 54 MHz to TV DAC Display functional clock Camera sensor clock Emulation trace clock The clock outputs to the DSS PER and EMU power domains are always on 307...

Page 308: ...l Internal Source Clock Generator Description 32K_FCLK sys_32k input pin PRM SYS_CLK Oscillator PRM System clock Serves as primary source clock of the device Also used as functional and interface clock for PRM DSS_TV_CLK DPLL4 sys_altclk input pin CM DSS TV clock 120M_FCLK DPLL5 CM 96M_FCLK DPLL4 CM 48M_FCLK DPLL4 sys_altclk input pin CM 12M_FCLK DPLL4 sys_altclk input pin CM PRM_192M_ALWON_C DPLL...

Page 309: ... DPLL1 which generates MPU_CLK All clocks are then locally generated by the clock generator in the MPU subsystem Figure 3 45 shows the clocking scheme in the MPU power domain Figure 3 45 MPU Power Domain Clocking Scheme NOTE ARM_FCLK is sourced by MPU_CLK and has the same frequency For more information about ARM_FCLK see Chapter 4 MPU Subsystem 3 5 3 4 1 2 IVA2 Power Domain The PRCM module does no...

Page 310: ...s and features in the high tier device To save power ensure that power domains of unavailable features and modules are switched off and clocks are cut off The SGX subsystem interface clock is sourced by the L3 clock The functional clock source can be selected between CORE_CLK COREX2_CLK CM_96M_FCLK and SGX_192M_FCLK When the functional clock source is CORE_CLK its frequency can be divided by 2 3 4...

Page 311: ...ral functional clocks 12 48 96 MHz system and 32 kHz that feed its peripherals and modules with following exception The McBSP 1 and McBSP 5 modules can be clocked by CORE_96M_FCLK from the CM or from an external clock MCBSP_CLKS The SCM manages the selection between the two sources For more information about the SCM see Chapter 13 System Control Module Figure 3 48 through Figure 3 50 show the cloc...

Page 312: ..._L4_ICLK MPU Async slave IVA Async 1 slave IVA Async 2 master OCM ROM OCM RAM ICR Public Version PRCM Functional Description www ti com Figure 3 48 CORE Clock Signals Part 1 312 Power Reset and Clock Management SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 313: ...0_FCLK GPT11_FCLK PRM MUX From system control module EMU async bridge MMC 1 2 3 Wake up power domain GPTIMER 10 11 Temp sensor x2 USB TLL USBTLL_SAR_FCLK 120M_FCLK CORE_120M_FCLK CORE_32K_FCLK Public Version www ti com PRCM Functional Description Figure 3 49 CORE Clock Signals Part 2 313 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instrum...

Page 314: ...unctional Description www ti com Figure 3 50 CORE Clock Signals Part 3 3 5 3 4 1 5 EFUSE Power Domain Figure 3 51 shows the clock signals and their relationships in the EFUSE power domain 314 Power Reset and Clock Management SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 315: ...nd on device wakeup from off mode During this procedure the PRM enables the EFUSE_ALWON_FCLK clock 3 5 3 4 1 6 DSS Power Domain This section describes all modules and features in the high tier device To save power ensure that power domains of unavailable features and modules are switched off and clocks are cut off Figure 3 52 shows the clock signals and their relationships in the DSS power domain ...

Page 316: ... be a division by 1 to 16 of the frequency of the DPLL4 synthesized clock DSS2_ALWON_FCLK The gated SYS_CLK Used mainly for display in low power refresh modes DSS_TV_FCLK Required when TV output is activated 3 5 3 4 1 7 CAM Power Domain This section describes all modules and features in the high tier device To save power ensure that power domains of unavailable features and modules are switched of...

Page 317: ...tem interface is clocked with the L3 and L4 clocks CAM_L3_ICLK and CAM_L4_ICLK respectively CAM_L3_ICLK is also used as the main functional clock The functional clock CAM_MCLK is provided by DPLL4 to supply the external sensor 3 5 3 4 1 8 USBHOST Power Domain Figure 3 54 shows the clock signals and their relationships in the USBHOST power domain 317 SWPU177N December 2009 Revised November 2010 Pow...

Page 318: ...ested simultaneously Therefore they are gated independently based on the configuration of the CM_FCLKEN_USBHOST 0 EN_USBHOST1 and CM_FCLKEN_USBHOST 1 EN_USBHOST2 bits The HS USB host subsystem gets an additional functional clock from the PRM USBHOST_SAR_FCLK It is dedicated to the save and restore mechanism and is automatically gated enabled by the PRM based on the HS USB host save and restore bit...

Page 319: ... on clock The voltage controller module in the PRM receives SYS_CLK as its functional clock The dedicated SmartReflex I2C4 module implemented in the voltage controller uses the same functional clock SYS_CLK The PRM receives SYS_CLK as the L4 interface clock For all other modules of the WKUP power domain the L4 interface clock WKUP_L4_ICLK is derived from SYS_CLK Communication between the WKUP powe...

Page 320: ...rals and modules All the functional clocks except 48M_FCLK are permanently supplied so that the peripherals can be used during low power scenarios even when the CORE power domain is off Figure 3 56 shows the clock distribution scheme in the PER power domain The McBSP 2 3 and 4 modules can be clocked by a clock from PRM PER_96M_FCLK or from an external clock MCBSP_CLKS This clock must be permanentl...

Page 321: ... Version www ti com PRCM Functional Description Figure 3 57 SMARTREFLEX Clock Signals 3 5 3 4 1 12 DPLL Domains The PRCM module provides clock sources for the five DPLLs as shown in Figure 3 58 321 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 322: ...ON_FCLK DPLL4_M2X2_CLK DPLL4_M3X2_CLK DPLL4_M4X2_CLK DPLL4_M5X2_CLK DPLL4_M6X2_CLK PRM CM MPU power domain WKUP power domain CORE power domain DPLL1 MPU DPLL2 IVA2 DPLL3 CORE DPLL4 PER DPLL5 power domain DPLL5 PER2 DPLL5_ALWON_FCLK DPLL5_M2X2_CLK prcm 054 Public Version PRCM Functional Description www ti com Figure 3 58 DPLL Clock Signals 322 Power Reset and Clock Management SWPU177N December 2009...

Page 323: ...mal SGX subsystem SGX_L3_ICLK CM Normal CORE CORE_ 120M_FCLK CM Normal USB TLL CORE_ 96M_FCLK CM Normal McBSP 1 5 MMC 1 2 3 I2C 1 2 3 CORE_48M_FCLK CM Normal UART 1 2 McSPI 1 4 CORE_12M_FCLK CM Normal HDQ GPT10_FCLK CM Normal GPTIMER10 GPT11_FCLK CM Normal GPTIMER11 USBTLL_SAR_FCLK PRM Normal USB TLL CM_32K_CLK PRM Normal Temperature sensor x2 MMC 1 2 3 CORE_L3_ICLK CM Normal L3 interconnect SDMA ...

Page 324: ... SR1 SR2 EFUSE EFUSE_ALWON_FCLK PRM Always on eFuse farm DPLL1 DPLL1_ALWON_FCLK PRM Always on DPLL1 DPLL1_FCLK CM Normal DPLL2 DPLL2_ALWON_FCLK PRM Always on DPLL2 DPLL2_FCLK CM Normal DPLL3 DPLL3_ALWON_FCLK PRM Always on DPLL3 DPLL4 DPLL4_ALWON_FCLK PRM Always on DPLL4 DPLL5 DPLL5_ALWON_FCLK PRM Always on DPLL5 NOTE Modules supplied only by the L3 interface clock MPU asynchronous bridge IVA2 2 as...

Page 325: ...MER 10 11 GPTn_FCLK 32 kHz or system clock ICR WDTIMER2 WKUP_32K_FCLK 32 kHz WDTIMER3 PER_32K_ALWON_FCLK 32 kHz GPIO1 WKUP_32K_FCLK 32 kHz GPIO 2 6 PER_32K_ALWON_FCLK 32 kHz 32 kHz sync timer 32K_FCLK 32 kHz p Bandgap temp sensor 32K_FCLK 32 kHz p System control CORE_L4_ICLK L4_ICLK 3 5 3 5 External Clock Controls Because the use of sys_32k and sys_altclk is described in Section 3 5 3 3 1 PRM and ...

Page 326: ...in The clock is not requested internally Hi Z by the device or externally external device peripheral Note Input is not driven from outside of device in this case 0 0 1 1 Input output buffer in The clock is requested externally Hi Z 0 1 0 1 Output The clock is requested internally 0 1 1 1 Output The clock is requested internally and externally Note The pad is driven both by device and from outside ...

Page 327: ... the system clock Table 3 36 System Clock Operation Modes AUTOEXTCLKMODE System Clock Mode Oscillator Mode Description 0x0 Always active mode Master The oscillator is kept active even when the clock is not requested by the device internally all device clocks are inactive or externally the sysclkreq input signal is not asserted Bypass The sys_clkreq output signal is permanently asserted by the devi...

Page 328: ...nly Asserted Asserted Active Input and output Asserted System clock is requested driven internally by internally and externally device and externally by peripheral Bypass Not asserted x 2 Bypass Input and output External clock System clock is not when external request state requested internally request is not sys_clkreq input has no asserted or input effect when external request is asserted Assert...

Page 329: ...ignal when the clock is gated is controllable by programming the PRCM CM_POLCTRL 0 CLKOUT2_POL bit 3 5 3 6 DPLL Control The PRCM module allows the configuration of the output clock frequencies of the DPLLs by setting their multipliers and dividers It also allows control of the operating mode of the DPLLs and automatic recalibration mode 3 5 3 6 1 DPLL Multiplier and Divider Factors DPLL clock outp...

Page 330: ...gers the return transition For automatic transition automatic mode must be enabled by programming the PRCM CM_AUTOIDLE_PLL or the PRCM CM_AUTOIDLE_PLL_ processor_name registers Table 3 40 describes the manual and automatic control of the DPLL power modes by the PRCM module Table 3 40 DPLL Power Mode Support Mode DPLL1 DPLL2 DPLL3 DPLL4 DPLL5 Locked Software request Software request Software reques...

Page 331: ...odes is enabled 3 5 3 6 3 DPLL Low Power Mode The DPLL can operate in a low power mode by reducing the operating frequency range This reduces the power consumption of the DPLL In this mode however there is a period and phase jitter effect The DPLL can enter this mode only if the targeted lock frequency of the DPLL is less than 600 MHz This implies locking or relocking the DPLL to a new targeted lo...

Page 332: ...table range the DPLL asserts a recalibration flag For example a large temperature drift can cause the DPLL to lose its lock and require recalibration When the DPLL locks at a temperature within the 080 degrees Celsius range the maximum temperature drift is approximately 55 degrees Celsius When DPLL starts at a negative temperature the maximum temperature drift is higher If the DPLL locks at 30 deg...

Page 333: ...libration feature PRCM PRM_IRQENABLE_MPU 5 CORE_DPLL_RECAL Enable disable the CORE DPLL recalibration interrupt to MPU PRCM PRM_IRQSTATUS_MPU 5 CORE_DPLL_ST Status of the CORE DPLL recalibration interrupt DPLL4 PER PRCM CM_CLKEN_PLL 19 Enable disable the PER DPLL automatic recalibration EN_PERIPH_DPLL_DRIFTGUARD feature PRCM PRM_IRQENABLE_MPU 6 Enable disable the PER DPLL recalibration interrupt P...

Page 334: ...g selection The clock is selectable among several possible source clocks for a module The gating control depends on the software programming of the CM_CLKSEL_ domain_name type of register The clock request of the module or domain must be set by the CM_CLKSEL bit GC gating control The functional interface clock is required by a single module across the power domain The gating control depends only o...

Page 335: ...ctive when OSC_SYS_CLK is active PRCM PRM_POLCTRL 2 CLKOUT_POL and sys_clkout1 is enabled and sys_clkreq is sys_clkreq asserted SYS_CLK Running Activated after clksetup_count_overflow Active when OSC_SYS_CLK is active and the SYS_CLK setup time is up CM_SYS_CLK Running PRCM CM_CLKSEL_CORE 6 CLKSEL_GPT10 Active if it is the source clock of the PRCM CM_CLKSEL_CORE 7 CLKSEL_GPT11 GPT10_FCLK or GPT11_...

Page 336: ...rogrammed to power down the oscillator when the device enters retention or off mode In this condition all the clock trees in the device must be gated and the four DPLLs DPLL1 DPLL2 DPLL3 and DPLL4 must enter stop mode before this transition can occur SYS_CLK is gated under the same conditions as the oscillator output clock but it is enabled only after the oscillator stabilizes Oscillator stabiliza...

Page 337: ...kout2 CORE_CLK GC PRCM CM_CLKEN_PLL 18 16 EN_PERIPH_DPLL PRCM CM_AUTOIDLE_PLL 5 3 AUTO_PERIPH_DPLL DPLL4_ALWON_FCLK PRCM CM_CLKSEL2_PLL 19 8 PERIPH_DPLL_MULT PRCM CM_CLKSEL2_PLL 6 0 PERIPH_DPLL_DIV PRCM CM_CLKSEL_DSS 12 8 CLKSEL_TV PRCM CM_CLKSEL3_PLL 4 0 DIV_96M 120M_FCLK prcm 057 PRCM CM_CLKEN2_PLL 2 0 EN_PERIPH2_DPLL PRCM CM_AUTOIDLE2_PLL 2 0 AUTO_PERIPH2_DPLL PRCM CM_CLKSEL4_PLL 6 0 PERIPH2_DP...

Page 338: ...CLK is active DPLL4_M3_CLK Stopped CM_CLKSEL1_PLL SOURCE_54M and If the dependent clocks are active the clock depends on the clock gating conditions of is active DSS_TV_CLK is a dependent DPLL4_M2_CLK and DSS_TV_CLK clock if set by the register configuration 120M_FCLK Stopped CM_FCLKEN_USBHOST 1 EN_USBHOST2 If any of the dependent clocks CM_FCLKEN3_CORE 2 EN_USBTLL CORE_120M_FCLK or USBHOST_12M_FC...

Page 339: ...automatic active AUTO_IVA2_DPLL control and enabled in lock mode while the PRCM CM_CLKEN_PLL_IVA2 2 0 IVA2 power domain goes into retention or EN_IVA2_DPLL and IVA2 power off mode Also gated if DPLL is set to domain power state low power stop or bypass mode DPLL2_FCLK Stopped DPLL3_ALWON_FCLK Running PRCM CM_AUTOIDLE_PLL 2 0 Gated if the DPLL is set to automatic active AUTO_CORE_DPLL control and e...

Page 340: ...navailable features and modules are switched off and clocks are cut off Figure 3 64 shows the clock controls for the SGX power domain Figure 3 64 SGX Power Domain Clock Controls Table 3 49 lists the clock gating controls for the SGX power domain Table 3 49 SGX Power Domain Clock Gating Controls Clock Name Reset Clock Gating Control Gating Description SGX_FCLK Stopped PRCM CM_FCLKEN_SGX 1 EN_SGX Ga...

Page 341: ...CM_FCLKEN1_CORE 14 EN_UART2 PRCM CM_FCLKEN1_CORE 19 EN_McSPI2 PRCM CM_FCLKEN1_CORE 20 EN_McSPI3 PRCM CM_FCLKEN1_CORE 13 EN_UART1 CORE_96M_FCLK 48M_FCLK CL PRCM CM_FCLKEN1_CORE 10 EN_McBSP5 PRCM CM_FCLKEN1_CORE 15 EN_I2C1 PRCM CM_FCLKEN1_CORE 16 EN_I2C2 PRCM CM_FCLKEN1_CORE 18 EN_McSPI1 PRCM CM_FCLKEN1_CORE 24 EN_MMC1 CORE_48M_FCLK CL PRCM CM_FCLKEN1_CORE 21 EN_McSPI4 prcm 061 PRCM CM_FCLKEN1_CORE ...

Page 342: ...MAPCTRL PRCM CM_ICLKEN1_CORE 7 EN_MAILBOXES PRCM CM_ICLKEN1_CORE 21 EN_MCSPI4 PRCM CM_AUTOIDLE1_CORE 20 AUTO_MCSPI3 PRCM CM_ICLKEN1_CORE 4 EN_HSOTGUSB PRCM CM_AUTOIDLE1_CORE 4 AUTO_HSOTGUSB PRCM CM_ICLKEN1_CORE 1 EN_SDRC Software control Source selection division prcm 062 PRCM CM_ICLKEN1_CORE 2 EN_USBTLL PRCM CM_AUTOIDLE3_CORE 2 AUTO_USBTLL PRCM CM_AUTOIDLE1_CORE 30 AUTO_MMC3 Public Version PRCM F...

Page 343: ...and Gated when the save restore bit is set to 0 PM_PWSTCTRL_CORE 4 or when the CORE power domain is in off SAVEANDRESTORE state after the save operation completes or in on state after the restore operation completes CORE_120M_FCLK Stopped CM_FCLKEN3_CORE 0 EN_USBTLL Gated when the enable bit is set to 0 or and DPLL5 operating mode the DPLL5 is in stop or bypass mode 3 5 3 7 7 EFUSE Power Domain Cl...

Page 344: ...Control Gating Description DSS1_ALWON_FCLK Stopped PRCM CM_FCLKEN_DSS 0 EN_DSS1 Gated when the enable bit is set to 0 DSS2_ALWON_FCLK Stopped PRCM CM_FCLKEN_DSS 1 EN_DSS2 Gated when the enable bit is set to 0 DSS_TV_FCLK Stopped PRCM CM_FCLKEN_DSS 2 EN_TV Gated when the enable bit is set to 0 DSS_L3_ICLK Stopped PRCM CM_ICLKEN_DSS 0 EN_DSS Gated when PRCM CM_AUTOIDLE_DSS 0 Enable bit is set to 0 A...

Page 345: ...w ti com PRCM Functional Description Figure 3 69 CAM Power Domain Clock Controls Table 3 53 CAM Power Domain Clock Gating Controls Clock Name Reset Clock Gating Control Gating Description CAM_MCLK Stopped PRCM CM_FCLKEN_CAM 0 EN_CAM Gated when the enable bit is set to 0 CAM_L3_ICLK Stopped PRCM CM_ICLKEN_CAM 0 EN_CAM Gated when PRCM CM_AUTOIDLE_CAM 0 AUTO_CAM Enable bit is set to 0 Enable autoidle...

Page 346: ...pped USBHOST_SAR_FCL Stopped PRCM PM_PWSTCTRL_USBHOST 4 Gated when the save restore bit is set K SAVEANDRESTORE to 0 or when the power domain is in off state after the save operation completes or in on state after the restore operation completes 3 5 3 7 11 WKUP Power Domain Clock Controls Figure 3 71 shows the clock controls for the WKUP power domain Table 3 55 lists the clock gating controls for ...

Page 347: ..._PER 14 EN_GPIO3 PRCM CM_FCLKEN_PER 13 EN_GPIO2 PRCM CM_FCLKEN_PER 12 EN_WDT3 PER_32K_ALWON_FCLK SYS_CLK Source selection division PRCM CM_FCLKEN_PER 17 EN_GPIO6 GPT3_ALWON_FCLK GPT4_ALWON_FCLK GPT5_ALWON_FCLK GPT6_ALWON_FCLK GPT7_ALWON_FCLK GPT8_ALWON_FCLK GPT9_ALWON_FCLK CL PRCM CM_FCLKEN_PER 1 EN_MCBSP3 PRCM CM_FCLKEN_PER 0 EN_MCBSP2 PRCM CM_FCLKEN_PER 2 EN_MCBSP4 PER_96M_FCLK 96M_ALWON_FCLK CL...

Page 348: ...UTO_GPIO4 PRCM CM_AUTOIDLE_PER 14 AUTO_GPIO3 PRCM CM_AUTOIDLE_PER 13 AUTO_GPIO2 PRCM CM_AUTOIDLE_PER 12 AUTO_WDT3 PRCM CM_AUTOIDLE_PER 11 AUTO_UART3 PRCM CM_AUTOIDLE_PER 10 AUTO_GPT9 PRCM CM_AUTOIDLE_PER 9 AUTO_GPT8 PRCM CM_AUTOIDLE_PER 8 AUTO_GPT7 PRCM CM_AUTOIDLE_PER 7 AUTO_GPT6 PRCM CM_AUTOIDLE_PER 6 AUTO_GPT5 PRCM CM_AUTOIDLE_PER 5 AUTO_GPT4 PRCM CM_AUTOIDLE_PER 2 AUTO_MCBSP4 PRCM CM_AUTOIDLE_...

Page 349: ... PRCM CM_FCLKEN_PER 8 EN_GPT7 Gated when the enable bit is set to 0 GPT8_ALWON_FCLK Stopped PRCM CM_FCLKEN_PER 9 EN_GPT8 Gated when the enable bit is set to 0 GPT9_ALWON_FCLK Stopped PRCM CM_FCLKEN_PER 10 EN_GPT9 Gated when the enable bit is set to 0 PER_L4_ICLK Stopped PRCM CM_ICLKEN_PER EN_ GPIO 2 6 Gated when WDT3 UART 3 4 GPT 2 9 MCBSP 2 4 and All enable bits are set to 0 PRCM CM_AUTOIDLE_PER ...

Page 350: ...alues 3 5 3 8 1 Processor Clock Configurations The processor OPPs are identified as the pair of VDD1 operating voltage level and processor clock frequency Five generic processor OPPs can be defined as 1 OPP1G2 VDD1 v3 MPU_CLK fmpu4 IVA2_CLK fiva3 2 OPP1G VDD1 v3 MPU_CLK fmpu3 IVA2_CLK fiva3 3 OPP130 VDD1 v2 MPU_CLK fmpu2 IVA2_CLK fiva2 4 OPP100 VDD1 v1 MPU_CLK fmpu1 IVA2_CLK fiva1 5 OPP50 VDD1 v0 ...

Page 351: ...K MPU subsystem internal module ARM_FCLK 2 ARM_FCLK 2 clocks 3 5 3 8 2 Interface and Peripheral Functional Clock Configurations The interface clock OPPs are identified as the pair of VDD2 operating voltage level and the device interface clocks frequencies The DPLL3 CORE DPLL generates the CORE_CLK which serves as the source clock for the L3_ICLK and L4_ICLK interface clocks of the device The CORE_...

Page 352: ... 3 61 Functional Clock Configuration Controls Module Clock Reference Divider Factor Configuration Bits Clock SGX SGX_FCLK CORE_CLK DIV_SGX 2 3 4 PRCM CM_CLKSEL_SGX 2 0 CLKSEL_SGX 6 COREX2_CLK DIV2_SGX 3 5 PRCM CM_CLKSEL_SGX 2 0 CLKSEL_SGX SGX_192M_FC PRCM CM_CLKSEL_SGX 2 0 CLKSEL_SGX LK CM_96M_FCLK PRCM CM_CLKSEL_SGX 2 0 CLKSEL_SGX MPU HS DPLL1_FCLK CORE_CLK DIV_DPLL1 1 2 PRCM CM_CLKSEL1_PLL_MPU 2...

Page 353: ...the power domain Similarly a wake up dependency ensures that a power domain wakes up when any of its dependent power domains wakes up The PRCM module automatically handles the sequence clock gating conditions and power switching for each power domain based on the configured dependencies between the domains and the clock control bits of the modules Figure 3 75 shows the sleep wake up transition of ...

Page 354: ...unctional and interface clocks in the module are directly mapped to the module clock controller The domain clock controller gathers information from the following All module clock controllers of the power domain The domain power controller The domain wake up controller The other power domain control blocks The domain clock controller informs the domain power controller when all conditions for the ...

Page 355: ...ON All functional and interface clocks in the power domain are shut down when the sleep conditions are met The power domain is idle and is not functional Retention The power domain is idle and part or all of the logic and memory of the domain is switched to retention mode Off The domain is idled and all the logic and memory in the domain are switched off The power domain state transition can be se...

Page 356: ...rate a synchronous or asynchronous wake up event based on the mode configurations For more information about the interrupt capability of a module see the module chapter The ability of a module to generate a wake up event depends on the power state of the power domain in which the module resides If the power domain is inactive the functional and interface clocks of the domain are gated only the asy...

Page 357: ...ot acknowledged Voltage processor 1 PRCM N A Yes Voltage processor 1 and voltage MPU 2 processor 2 status Device wake up event PRCM N A Yes Any PAD wake up event when MPU CORE domain is off Table 3 64 NEON Power Domain Wake Up Events Internal Wake Up Source PRCM Software Control Wake Interrupt Type Interrupt to Events Module Up Event MPU domain PRCM PM_WKDEP_NEON Yes No N A dependency Forced wake ...

Page 358: ...Event Interrupt Type Interrupt to Events MPU domain PRCM Hardware set Yes No N A dependency always enabled IVA2 domain PRCM Yes No N A dependency CAM domain PRCM Yes No N A dependency DSS domain PRCM Yes No N A dependency USBHOST domain PRCM Yes No N A dependency PER domain PRCM Yes No N A dependency SGX domain PRCM Yes No N A dependency WKUP domain PRCM Yes No N A dependency HS USB OTG HS USB OTG...

Page 359: ... register Yes No N A dependency WKUP domain PRCM PM_WKDEP_CAM register Yes No N A dependency Forced transition PRCM CM_CLKSTCTRL_CAM Yes Wake up transition is complete MPU state wakeup register Table 3 70 USBHOST Power Domain Wake Up Events Internal Source PRCM Software Control Wake Up Interrupt Type Interrupt to Wake Up Events Module Event MPU domain PRCM PM_WKDEP_USBHOST Yes No N A dependency re...

Page 360: ...T3 wakeup UART3 Yes No N A UART4 wakeup UART4 Yes No N A GPIO2 wakeup GPIO 2 Yes No N A GPIO3 wakeup GPIO 3 Yes No N A GPIO4 wakeup GPIO 4 Yes No N A GPIO5 wakeup GPIO 5 Yes No N A GPIO6 wakeup GPIO 6 Yes No N A Forced transition PRCM CM_CLKSTCTRL_PER Yes Wake up transition is complete MPU state wakeup register Table 3 72 EMU Power Domain Wake Up Events Internal Source PRCM Software Control Wake U...

Page 361: ...ny new transitions All target modules in the clock domain are in idle mode and have no pending transitions If the power domain depends on another power domain that is has a sleep dependency the clock domains of the other power domain must be muted A clock domain is said to be muted when all its public initiator modules that is the initiator modules of the clock domain that can generate interconnec...

Page 362: ...ncies are enabled the PER domain can go to idle mode only if the MPU IVA2 and CORE L3 clock domains are idle If all software dependencies are disabled the PER domain can go to idle mode provided that the CORE L3 clock domain is muted no access to the PER domain can be pending Table 3 75 summarizes the programmable and hardwired sleep dependencies among the domains NOTE The first row of the table i...

Page 363: ...le RW Read and write N A Not applicable 3 5 4 5 2 Wake Up Dependencies A wake up dependency allows a power domain to wake up from off retention or inactive state to on state when another power domain wakes up from off retention or inactive state to on state For example power domain one PD1 provides a service to power domain two PD2 which creates a dependency between the two domains When the depend...

Page 364: ...urable For the processor power domains MPU and the IVA2 power domain when the wake up dependency with other power domains is software programmable that is with the USBHOST PER CORE and WKUP power domains two registers may need be configured PM_WKDEP_ domain and PM_ processor GROUPSEL_ domain The PM_WKDEP_ domain register serves only to enable disable the global wake up dependency of the processor ...

Page 365: ... CORE_L3 1 0 1 0 0 1 1 1 N A 1 0 1 CORE_L4 1 0 1 0 0 0 0 0 0 N A 0 1 CORE_CM 1 0 1 0 0 1 1 1 1 1 N A 1 WKUP WKUP 1 0 1 0 0 0 1 1 1 1 0 N A Notes RW Software wakeup dependency dependency by PM_WKDEP_ register RW Software wakeup dependency dependency by PM_WKDEP_ and PM_ GRPSEL_ registers RW Software wakeup dependency dependency by PM_ GRPSEL_ registers 1 Hardware wakeup dependency dependency always...

Page 366: ...to the power domain When the domain modules acknowledge the sleep request the functional and interface clocks to the modules are gated 2 The PRCM module enables the SAR_FCLK functional clock and initiates the save sequence for the module SAR_FCLK is gated when the save sequence completes 3 The PRCM module switches the power domain state to off power state When a wake up event occurs the PRCM modul...

Page 367: ...omain reset 5 prcm 092 Functional clock Interface clock USB HOST USB TLL ON OFF ON Public Version www ti com PRCM Functional Description Figure 3 77 Save and Restore Sequence 367 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 368: ...power state completes 3 5 4 6 2 USB TLL SAR Sequences 3 5 4 6 2 1 Save Sequence on Sleep Transition A precondition to the save sequence on sleep transition is that the save and restore mechanism is enabled the PRCM PM_PWSTCTRL_CORE 4 SAVEANDRESTORE bit is set to 1 The sequence is initiated when the power domain switches from ON to Open Switch Retention OSWR or OFF power state 1 When the CORE power...

Page 369: ...es DPLL3 recalibration event MPU 5 CORE_DPLL_ST MPU 5 CORE_DPLL_ RECAL_EN PRM_IRQSTATUS_ PRM_IRQENABLE_ PRCM_MPU_IRQ Yes DPLL4 recalibration event MPU 6 PERIPH_DPLL_ST MPU 6 PERIPH_DPLL_ RECAL_EN PRM_IRQSTATUS_ PRM_IRQENABLE_ PRCM_MPU_IRQ Yes DPLL2 recalibration event MPU 7 MPU_DPLL_ST MPU 7 MPU_DPLL_ RECAL_EN PRM_IRQSTATUS_ PRM_IRQENABLE_ PRCM_MPU_IRQ Yes DPLL1 recalibration event MPU 8 IVA2_DPLL...

Page 370: ..._IRQSTATUS_ PRM_IRQENABLE_ PRCM_MPU_IRQ Yes Slave address in an I2 C MPU 22 VC_ MPU 22 VC_ frame sent by the voltage SAERR_ST SAERR_EN controller not acknowledged by the power IC device PRM_IRQSTATUS_ PRM_IRQENABLE_ PRCM_MPU_IRQ Yes Register address in an MPU 23 VC_ MPU 23 VC_ I2 C frame sent by the RAERR_ST RAERR_EN voltage controller not acknowledged by the power IC device PRM_IRQSTATUS_ PRM_IRQ...

Page 371: ...ke up transition completion PRM_IRQSTATUS_IVA2 2 PRM_IRQENABLE_IVA2 2 PRCM_IVA_IRQ Yes DPLL2 recalibration required IVA2_DPLL_ST IVA2_DPLL_RECAL_EN NOTE The software must first read the event flag to determine the cause of the interrupt and then write 1 to it to clear the flag 3 5 6 PRCM Voltage Management Functional Description This section describes the voltage domains and voltage control archit...

Page 372: ...ew of Device Voltage Domains The device is split into voltage domains Three voltage domains for logic VDD1 VDD2 and VDD3 Two voltage domains for memory VDD4 and VDD5 Two voltage domains for PLLs and analog cells VDDPLL and VDDPLL_PER Voltage domain for the I Os This partition of the voltage domains ensures independent voltage control of each voltage domain through dedicated SMPS or LDO Functionall...

Page 373: ... VDDS VDDPLL and MMC VDDS are either controlled directly by the external device or software controlled through an I2 C interface independent of the PRM Figure 3 79 is an overview of PRCM voltage control 373 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 374: ... CSIPHY2 vdds_sim SIM LDO I Os 1 8 3 V MMC_VDDS LDO vdda_dpll_dll VDDPLL DPLL1 DPLL2 DPLL3 VDDPLL_PER DPLL4 DPLL5 LDO vdda_dac VDDADAC Control module vdda_sram vdds 5 1 vdds_mem vdds_mmc1 vdda_dpll_per 5 sys_nvmode1 sys_nvmode2 i2c4_scl i2c4_sda SDRC I Os GPMC I Os Public Version PRCM Functional Description www ti com Figure 3 79 Overview of Device Voltage Distribution NOTE Memory I Os 1 8 V are n...

Page 375: ...ssor memories vdda_sram All memories in retention VDD1 is in OPP50 or OPP100 VDD1 in OPP130 VDD5 voltage domain Off HW CORE SGX CAM DSS PER USBHOST vdda_sram and EMU memories Retention VDD2 is in OPP50 or OPP100 VDDS voltage domain Always on None I Os vdds VDDADAC voltage domain Software driven only 2 SW Video DAC vdda_dac VDDPLL voltage domain Always on 2 None Analog part of DPLL1 DPLL2 and DPLL3...

Page 376: ...mains of 0 VDD1 are in AUTO_OFF inactive 0 retention or off state Retenti Software DPLL1 and DPLL2 N A AUTO_SLEE ON or ON or Retention ON or on controlled are in Stop mode P 0 retention Overdriven retention power AUTO_RET domains of 1 VDD1 are in AUTO_OFF retention or 0 off state and of VDD2 are in INACTIVE retention or off state Off Software All DPLLs are in No longer AUTO_SLEE Off SLEEP Off Off ...

Page 377: ...n refer to the PRM_VOLTCTRL 0 AUTO_SLEEP PRM_VOLTCTRL 1 AUTO_RET and PRM_VOLTCTRL 2 AUTO_OFF bits Table 3 83 Remaining Voltage Domain Dependencies Voltage Condition VDDS External memory I Os VDDADAC VDDPLL VDDPLL_PER CSIB No dependency with other device voltages DSI CSIPHY2 SIM MMC_VDDS 3 5 6 4 Voltage Control Architecture The PRM is split over several blocks that manage the different voltage sour...

Page 378: ...roller I2 C mode or by sending the sys_nvmode1 and sys_nvmode2 control signals direct control mode The FSMs control voltage level switching based on the power state of the device The FSMs in the PRM also control SRAM and wake up LDOs sleep mode for analog cells and level shifters A device FSM sequences the memory wakeup voltage and I O FSMs during the device off sleep and wake up transitions NOTE ...

Page 379: ... PRM is configured by the PRCM PRM_POLCTRL 0 EXTVOL_POL bit which is active low by default When the signal goes low a lower voltage is supplied and when it goes high a higher voltage is supplied The VMODE voltage control is enabled by setting the PRM PRM_VOLTCTRL 4 SEL_VMODE bit and is triggered when the device switches between low power retention or off mode and normal on mode Figure 3 81 is an e...

Page 380: ...ge domains An arbitration scheme in the voltage controller manages concurrent requests on multiple ports Externally the voltage controller interfaces to a power IC through a dedicated I2 C interface I2C4 To reduce the latency of voltage changes the voltage controller is configurable to run in HS I2 C mode Each internal port has a handshake to indicate when the I2 C frame that results from the requ...

Page 381: ... 3 82 SmartReflex Integration SmartReflex voltage control in the device is implemented for simultaneous control of two independent voltage sources One SmartReflex module controls the VDD1 voltage while the second one is dedicated to VDD2 control Each SmartReflex module is connected to a voltage processor Voltage commands from both voltage processors are passed to a voltage control which sends them...

Page 382: ... SRCLKLENGTH bit field allows the setting of the frequency divider ratio between the SR_ALWON_FCLK and the SR_CLK It is calculated using Equation 1 SRn SRCONFIG 21 12 SRCLKLENGTH f SR_ALWON_FCLK 2 f SR_CLK 1 Where f SR_ALWON_FCLK is the frequency of the SR_ALWON_FCLK and f SR_CLK is the desired SR_CLK frequency To accurately use the target values programmed for SmartReflex modules in the device th...

Page 383: ...um and average values The minimum maximum and average values of the samples of the first sensor can be read from the SRn SENMIN 15 0 SENNMIN SRn SENMAX 15 0 SENNMAX and SRn SENAVG 15 0 SENNAVG bit fields For the sample values of the second sensor the minimum maximum and average values can be read from the SRn SENMIN 31 16 SENPMIN SRn SENMAX 31 16 SENPMAX and SRn SENAVG 31 16 SENPAVG bit fields The...

Page 384: ...c hardware voltage control the voltage processor interrupt iSRn ERRCONFIG 22 VPBOUNDSINTENABLE is enabled and the SmartReflex module interrupts the voltage processor module when the error crosses the error limits In this case the MPU interrupts can also be enabled to allow the software to monitor the SmartReflex module behavior With manual software voltage control the voltage processor interrupt r...

Page 385: ...15 8 RNSENP SRn NVALUERECIPROCAL 7 0 RNSENN The eFuse values of these parameters can be read from the corresponding registers of the SCM The SCM registers associated with the parameters SENPGAIN SENNGAIN RNSENP and RNSENN of the SR1 module are CONTROL CONTROL_FUSE_OPP50_VDD1 CONTROL CONTROL_FUSE_OPP100_VDD1 CONTROL CONTROL_FUSE_OPP130_VDD1 CONTROL CONTROL_FUSE_OPP1G_VDD1 CONTROL CONTROL_FUSE_OPP1G...

Page 386: ...rtReflex module by clearing its interrupt The voltage processor is enabled by the PRCM PRM_VPn_CONFIG 0 VPENABLE bit Voltage Processor Interrupts The voltage processor uses the PRCM_MPU_IRQ M_IRQ_11 interrupt line of the MPU INTC to interrupt the MPU Table 3 86 and Table 3 87 list the interrupt sources in the voltage processor module and their enable and status bits Table 3 86 Voltage Processor In...

Page 387: ...MPU 10 VP1_OPPCHANGEDONE_EN VP1_OPPCHANGEDONE_ST Voltage Processor Status The status of the voltage processor is represented by the following PRCM PRM_VPn_VOLTAGE 7 0 Current voltage for SMPS Value of the current voltage level requested by VPVOLTAGE the voltage processor PRCM PRM_VPn_STATUS 0 VPINIDLE VP in inactive state The voltage processor is in idle mode Voltage Processor Parameters The follo...

Page 388: ...SMPS The SmartReflex module voltage processor voltage controller and SMPS implement a simple handshake protocol based on a request acknowledge mechanism see Figure 3 85 1 The SmartReflex module generates a VP interrupt clears to 0 when the average error crosses the minimum or maximum error bounds 2 The average VDDx error is passed to the voltage processor when automatic voltage control is enabled ...

Page 389: ...g cells when the device enters off mode 3 5 6 6 1 ABB LDOs Control ABB LDO supports two voltage modes BYPASS mode In this mode the x_ABB LDO is bypassed and outputs the VDD_x_L voltages x refers to MPU and IVA This mode is activated when FBB is not required or when voltage domain enters low power mode FBB mode is enabled when the device is at highest OPP OPP1G The PRCM provides the PRM_LDO_ABB_CTR...

Page 390: ...These modes are managed automatically by hardware PRM 3 5 6 6 3 Wake Up and Emulation Voltage Control The embedded wake up LDO VDD3 supplies both WKUP and EMU power domains It is permanently active and feeds the WKUP power domain continuously An embedded switch allows the PRM to control power to the EMU power domain This switch is closed on a software request command when a debug session starts or...

Page 391: ...ice is in off mode The off mode scheme is based on the following components of the device I O pads SCM Figure 3 86 is an overview of the I O pad off mode scheme In this mode the I O pads of the device form a daisy chain The I O pad logic at the two ends of the chain is connected to the PRM When a wake up event WUEVT occurs on an enabled I O pad in the chain the event is propagated through the chai...

Page 392: ...the corresponding I O must be enabled before transitioning the PER domain to a nonfunctional state This typically happens when the device is programmed to enter OFF state During off mode only six pins of the GPIO module in the WAKEUP domain are wake up capable therefore the I O wake up scheme must be enabled for the other 26 I Os before transitioning to OFF state The I O wake up scheme can be enab...

Page 393: ... In OFF state however the logic and memories are switched off and the RFFs are not saved NOTE If the PER power domain is kept on while the CORE power domain is in RETENTION state all I O wake up enable EVT_EN signals signals to the I O pads related to the PER power domain inputs must be disabled by clearing the CONTROL CONTROL_PADCONF_ IOpad 14 WAKEUPENABLE bit in the SCM in this case wake up even...

Page 394: ... A daisy chain wake up event always causes the MPU to restart and boot Other independent wake up events activated in off mode for example a GPIO wake up event always cause the CORE power domain to be activated The MPU is wakened if a wake up dependency has been set by the user or if the modem generates an interrupt to the MPU 3 5 7 4 Device Off Mode Sequences Device off mode sequencing requires pr...

Page 395: ...IC updates VDD1 to its previously programmed value 13 Upon reception of the I2C4 transaction acknowledge and after waiting for the VDD1 regulator setup time counter to expire the PRM_VOLTSETUP1 15 0 SETUPTIME1 bit field the PRM sends the off command for VDD2 to the voltage controller Through I2C4 the voltage controller requests the power IC to set VDD2 to the voltage corresponding to PRM_VC_CMD_VA...

Page 396: ...r VDD1 to the voltage controller Through I2C4 the voltage controller requests the power IC to set VDD1 to set the voltage corresponding to the PRM_VC_CMD_VAL_0 31 24 ON bit field If vmode legacy mode is used the voltage controller deasserts sys_nvmode1 and the power IC restores VDD1 to its previously programmed value At this point VDD1 ramps up the reset is not yet asserted on VDD1 logic 6 It wait...

Page 397: ...p time The two counts are started in parallel 6 When both timers expire the following steps happen in parallel Reset is asserted on the MPU and CORE power domains The MPU and CORE power domains are powered up The PRM restarts the CORE and processor memory LDOs The PRM powers up all analog cells in the VDD1 and VDD2 domains 3 6 PRCM Basic Programming Model The PRCM module supports an extensive set ...

Page 398: ...me sent by the voltage controller not acknowledged by the power IC device Register address in an I2 C frame sent by the voltage controller not acknowledged by the power IC device Last byte of an I2 C frame issued from the bypass port or the voltage manager FSM ports sent by the voltage controller not acknowledged by the power IC device The end of on time period and end of off time period events of...

Page 399: ...e PRM triggers the interrupt line dedicated to the IVA2 processor when the MPU performs a force wake up transition on the IVA2 domain This interrupt is triggered under the same conditions as that of the MPU The PRM triggers an IVA2 2 interrupt if the DPLL recalibration flag is set and the corresponding interrupt enable bit in the PRM_IRQENABLE_ processor_name register is set to 1 The recalibration...

Page 400: ...off time register Off time duration setting 3 6 1 5 Output Signal Polarity Control Registers 3 6 1 5 1 CM_POLCTRL CM Polarity Control Register The CM_POLCTRL register allows the setting of the polarity of sys_clkout2 when gated disabled sys_clkout2 can be gated to a low level or a high level depending on the software programming of this register Figure 3 87 shows the normal behavior of sys_clkout2...

Page 401: ...he polarity of the external signals controlled by the PRM It contains the following polarity control bits OFFMODE_POL Polarity of sys_off_mode CLKOUT_POL Polarity of sys_clkout1 CLKREQ_POL Polarity of sys_clkreq EXTVOL_POL Polarity of both sys_nvmode signals sys_nvmode1 and sys_nvmode2 At device power up the reset values of polarity settings are OFFMODE_POL 1 and CLKREQ_POL 1 For details about usi...

Page 402: ...n time after the clock is turned on again SYSCLKDIV Input divider 1 2 of the system clock 3 6 2 1 2 PRM_CLKSETUP Source Clock Setup Register The source clock setup register allows the setting of the setup time of the oscillator system clock based on the number of 32 kHz clock cycles This duration corresponds to the time required by the oscillator to stabilize before propagating the system clock Be...

Page 403: ...es of the DPLL Selection of the fast bypass clock CORE_CLK or CORE_CLK 2 in bypass mode Configuration of DPLL output clock divider values M2 factor The device has four DPLL clock selection registers for DPLL1 and DPLL2 CM_CLKSEL1_PLL_MPU DPLL1 multiplier divider and fast bypass clock selection CM_CLKSEL2_PLL_MPU DPLL1 output clock divider selection CM_CLKSEL1_PLL_IVA2 DPLL2 multiplier divider and ...

Page 404: ...8 MPU_DPLL_MULT bit field resets to 0 3 6 2 3 4 CM_CLKEN_PLL DPLL Enable Register The DPLL enable register allows control of DPLL3 DPLL4 and DPLL5 It allows an immediate setting of the DPLLs This register controls the following features of the two DPLLs DPLL operation mode Low power bypass fast relock bypass and lock modes for DPLL3 Low power bypass and lock modes for DPLL4 Programmable automatic ...

Page 405: ...ctivity status for the functional clocks can be The functional 96 MHz clock is active or not The functional 48 MHz clock is active or not The functional 12 MHz clock is active or not The functional 54 MHz clock is active or not The functional 96 MHz clock and all other functional clocks derived from it are active only when DPLL4 is locked and the clock is required The functional 48 MHz and 12 MHz ...

Page 406: ...output clock The device includes the following clock select registers CM_CLKSEL_CORE L3 and L4 interconnects and GPTIMER10 and 11 functional clocks CM_CLKSEL_CAM Camera subsystem functional clock CM_CLKSEL_DSS DSS functional clock 1 and TV functional clock CM_CLKSEL_PER GPTIMER2 3 4 5 6 7 8 and 9 functional clocks CM_CLKSEL_SGX SGX subsystem functional clock CM_CLKSEL_WKUP GPTIMER1 functional cloc...

Page 407: ...3_CORE CORE domain peripherals set CM_ICLKEN_CAM Camera subsystem CM_ICLKEN_DSS DSS subsystem CM_ICLKEN_PER PER domain peripherals set CM_ICLKEN_SGX SGX subsystem CM_ICLKEN_WKUP WKUP domain peripherals set CM_ICLKEN_USBHOST HS USB Host subsystem This register has an immediate effect causing the source of the interface clock to be effectively cut if the appropriate bit is cleared and no module requ...

Page 408: ...LE_WKUP WKUP domain peripherals set CM_AUTOIDLE_USBHOST HS USB Host subsystem NOTE For SmartReflex1 and 2 IVA2 2 and GFX modules the automatic idle mode is always enabled and is not software controllable 3 6 2 4 5 CM_IDLEST_ domain_name Idle Status Register The idle status register allows checking whether a target module is in idle mode or if an initiator module is in standby mode Software must no...

Page 409: ...oftware forces a sleep transition on a power domain otherwise the forced domain will be wakened immediately because of the wake up dependency The device has the following clock state control registers CM_CLKSTCTRL_MPU MPU subsystem clock domain CM_CLKSTCTRL_CORE L3 L4 and D2D clock domains CM_CLKSTCTRL_CAM Camera subsystem clock domain CM_CLKSTCTRL_DSS DSS clock domain CM_CLKSTCTRL_PER Peripherals...

Page 410: ...ST_IVA2 IVA2 2 clock domain activity CM_CLKSTST_SGX Graphics subsystem clock activity CM_CLKSTST_EMU Emulation clock activity CM_CLKSTST_USBHOST USBHOST clock activity 3 6 2 4 8 CM_SLEEPDEP_ domain_name Sleep Dependency Control Register The sleep dependency control register allows the enabling or disabling of the sleep transition dependency of a power domain with respect to other power domains The...

Page 411: ...in the register enables disables the wake up event from the module to the PRCM module The device has the following wake up enable registers PM_WKEN1_CORE and PM_WKEN3_CORE CORE domain modules wake up control PM_WKEN_DSS Display subsystem DSS wake up control PM_WKEN_PER Peripheral domain modules wake up control PM_WKEN_WKUP WKUP domain modules wake up control PM_WKEN_USBHOST HS USB Host subsystem w...

Page 412: ...ake up dependency register allows the enabling disabling of a wake up dependency between power domains When a domain wakes up it can wake up another domain The device has the following wake up dependency registers PM_WKDEP_MPU MPU power domain wake up dependency with the following domains CORE IVA2 WKUP DSS PER PM_WKDEP_DSS DSS power domain wake up dependency with the following domains MPU IVA2 WK...

Page 413: ...er The device has the following processor group selection registers PM_MPUGRPSEL1_CORE and PM_MPUGRPSEL3_CORE CORE power domain modules MPU wake up control PM_IVA2GRPSEL1_CORE and PM_IVA2GRPSEL3_CORE CORE power domain modules IVA2 wake up control PM_MPUGRPSEL_PER PER power domain modules MPU wake up control PM_IVA2GRPSEL_PER PER power domain modules IVA2 wake up control PM_MPUGRPSEL_WKUP WKUP powe...

Page 414: ...control registers PRM_RSTCTRL This register allows control of the assertion of the global software reset and the DPLL3 software reset These bits are automatically cleared Assertion of the DPLL3 software reset triggers a device global cold reset The reset condition of this register depends on the bit field The RST_GS bit is set on any global source of reset warm or cold The RST_DPLL3 bit is set onl...

Page 415: ...ly the RM_RSTST_CORE RM_RSTST_IVA2 and PRM_RSTST registers log software sources of reset Each bit of these registers is set on the effective release of the respective reset signal 415 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 416: ...r management PM_PWSTCTRL_USBHOST USBHOST domain power management MPU domain power management has the following features The power state is programmable to on retention and off states Logic and L1 cache state are switchable to off and retention states when the power domain is in retention state L2 cache state is switchable to off and retention states when the power domain is in retention state L2 c...

Page 417: ... switchable to off and retention states when the power domain is in retention state L1 flat memory state is switchable to off and retention states when the power domain is in retention state L2 cache state is switchable to off and retention states when the power domain is in retention state L2 flat memory state is switchable to off and retention states when the power domain is in retention state L...

Page 418: ...nsition from ON power state to inactive off or retention and from inactive off or retention power states to on power state The memory power state is updated by performing a dynamic memory change the PM_PWSTCTRL_ domain_name MEMORYCHANGE bit Software clears the PM_PREPWST_ domain_name register this forces a memory change to the same value The device has the following power state status registers PM...

Page 419: ...he previous power state status register for the CORE power domain indicates the previous domain logic on or off and memory banks 1 and 2 on retention or off power state The previous power state status registers for the SGX DSS CAM PER NEON USBHOST and EMU power domains indicate the previous domain on inactive retention or off power state The SGX power domain does not require a memory power state s...

Page 420: ...M_VOLTSETUP1 register is used when the device exits the off mode and manages the sequencing of the voltage regulation steps the PRM_VOLTCTRL 3 SEL_OFF bit is set to 0 The PRM_VOLTSETUP2 register has the following bit field OFFMODESETUPTIME The number of 32 kHz clock cycles for the overall setup time of the power management IC when coming back from off mode The PRM_VOLTSETUP2 register is used only ...

Page 421: ... device cold boot up sequence 3 6 5 1 3 PRM_VOLTCTRL Voltage Source Control Register This register allows control of the power IC The following are the register bit fields AUTO_SLEEP Automatically sends the sleep command when the voltage domain is in the appropriate standby mode AUTO_RET Automatically sends the retention command when the voltage domain is in the appropriate standby mode AUTO_OFF A...

Page 422: ... sets of voltage level commands for each of the four power states on low power retention and off for the power IC The voltage commands depend on the power IC device used 3 6 5 2 5 PRM_VC_CH_CONF Voltage Controller Channel Configuration Register This register consists of a set of select bits for the VDD1 and VDD2 channels the slave address command register address voltage register address and volta...

Page 423: ...ter allows the configuration of the voltage processor module It controls the following features of the voltage processor Enable disable the voltage processor Force a voltage update into the power IC device Initialize the power IC device initial VDD value into the voltage processor Enable disable the time out capability of the voltage processor Set the power IC initial VDD value Set the error to vo...

Page 424: ...e trying to reprogram the voltage processor Unlike other voltage processor status events logged as a source of an interrupt on the MPU the event logged in this register is not a cause of the interrupt The device has the following voltage processor status registers PRM_VP1_STATUS PRM_VP2_STATUS 3 6 6 Generic Programming Examples 3 6 6 1 Clock Control The module clock management is controlled throug...

Page 425: ...ed or disabled by writing the dedicated bit in the CM_FCLKEN_ domain_name register This bit has a direct effect on the clock activity The functional clock is turned on if the bit is enabled and the clock is not yet active The functional clock is turned off if the bit is disabled and the clock is not required by any other module Figure 3 90 Functional Clock Basic Programming Model The functional cl...

Page 426: ...t has a direct effect on the clock activity The interface clock is turned on if the bit is enabled and the clock is not yet active The interface clock is turned off if the bit is disabled and the clock is not required by any other module The interface clock can be automatically enabled or disabled by the PRCM module based on hardware conditions This automatic clock activity control mode is enabled...

Page 427: ...Programming Model Figure 3 92 Interface Clock Basic Programming Model The frequency ratio between the CORE_CLK the L3_ICLK and the L4_ICLK is configured by setting the corresponding CM_CLKSEL_CORE register bit fields This configuration must be done before switching DPLL3 to lock mode In this way the clock ratio is switched while DPLL3 is operating at system clock frequency and then only DPLL3 is s...

Page 428: ...TRL_ domain CLKTR CTRL_ clock domain bit field to 0x1 Power domain is in ON power state Program next power state of the power domain by setting corresponding PM_PWSTCTRL_ domain POWERSTATE bit field Public Version PRCM Basic Programming Model www ti com The CM_CLKSTST_ domain register identifies whether a power domain or a clock domain within the power domain is accessible A domain is inaccessible...

Page 429: ...AUTOIDLE_PLL_ processor register It takes effect only if the processor DPLL is locked the CM_CLKEN_PLL_ processor register is set in lock mode The HS bypass clock for the processor DPLL can be The DPLL3 output clock CORE_CLK The DPLL3 output clock CORE_CLK divided by 2 The HS bypass clock is selected by programming the CM_CLKSEL1_PLL_ processor register The software can read the CM_IDLEST_PLL_ pro...

Page 430: ...EL2_PLL_ processor 4 0 processor _DPLL_CLKOUT_DIV bit field Set DPLL to LOCK mode No Yes Set corresponding CM_CLKEN_PLL_ processor 2 0 EN_ processor _DPLL bit field to 0x7 Set corresponding CM_CLKEN_PLL_ processor 2 0 EN_ processor _DPLL bit field to 0x5 Set DPLL to BYPASS mode No Yes DPLL AUTOIDLE mode is enabled Yes No Idle conditions satisfied Yes No No End DPLL in LOCK mode and clock is runnin...

Page 431: ... chart in Figure 3 95 shows the control sequence of the module wake up event This procedure consists of the following steps 1 Program the PRCM module to consider the wake up event 2 Switch to idle mode and wait for the wake up event 3 Wake up on the wake up event and activate the module functional clock 4 Acknowledge the wake up event The peripheral that can generate a wake up event must be attach...

Page 432: ...ng CM_FCLKEN_ domain register Peripheral in wake up event wait mode prcm 084 Public Version PRCM Basic Programming Model www ti com Figure 3 95 Wake up Basic Programming Model A power domain A can have a functional dependency on a power domain B Thus when power domain A wakes up it may be necessary to wake up power domain B This wake up dependency is hardcoded for the CORE power domain but is prog...

Page 433: ...led Min Max Avg disabled Error generator block disabled Interrupt generator block disabled Interrupts masked Set Module Idle state clock activity Public Version www ti com PRCM Basic Programming Model Figure 3 96 SmartReflex Initialization Flow Chart After the device power on reset is complete the SmartReflex module is disabled and its functional clock is gated 1 Clock setting Setting the clock co...

Page 434: ... generator setting The error generator setting consists of setting the four reference value parameters according the current OPP and then enabling the error generator SRn NVALUERECIPROCAL 23 20 SENPGAIN Configured according to the values read for the current operating voltage level from the SCM register SRn NVALUERECIPROCAL 19 16 SENNGAIN See Section 3 5 6 5 4 5 Parameter Configuration SRn NVALUER...

Page 435: ...e interrupt when the enabled interrupt conditions occur SRn SRCONFIG 11 SR_EN 0x1 Enable the SmartReflex module NOTE Each time the device configuration is changed for instance the OPP is switched after this initial configuration phase completes the module must be disabled 3 6 6 5 Voltage Processor Initialization Basic Programming Model Figure 3 97 is a flow chart of the voltage processor initializ...

Page 436: ...assert it in the FSM Set the voltage slew rate for the positive and negative voltage steps Enable voltage processor interrupts 3 Enable interrupts prcm UC 007 Voltage processor disabled Public Version PRCM Basic Programming Model www ti com Figure 3 97 Voltage Processor Initialization Flow Chart 1 Error to voltage converter setting The error to voltage converter setting consists of configuring the...

Page 437: ...the initial voltage into the voltage processor FSM PRCM PRM_VPn_VSTEPMIN 23 8 Slew rate of the negative voltage step of the SMPS SMPSWAITTIMEMIN PRCM PRM_VPn_VSTEPMAX 23 8 Slew rate of the positive voltage step of the SMPS SMPSWAITTIMEMAX 3 Enable interrupts The interrupt generator setting consists of setting the error weight and the minimum maximum error limits Then depending on operational requi...

Page 438: ...ask the VP1 minimum VDD interrupt PRCM PRM_IRQENABLE_MPU 16 0x0 Mask the VP2 OPP change done interrupt VP2_OPPCHANGEDONE_EN Default 0x1 Unmask the VP2 OPP change done interrupt PRCM PRM_IRQENABLE_MPU 10 VP1_ 0x0 Mask the VP1 OPP change done interrupt OPPCHANGEDONE_EN Default 0x1 Unmask the VP1 OPP change done interrupt 4 Enable the module In the final phase of configuration the voltage processor m...

Page 439: ...RM_VC_I2C_CFG MCODE Yes No I C in repeated start 2 operation Clear PRM_VC_I2C_CFG SREN to 0 5 I C Configuration 2 Two power ICs supported Yes Yes Set PRM_VC_CH_CONF RACENx to 1 Voltage FSMx uses voltage register address to send voltage commands No VDDx will use register slave address 0 for power IC NOTE In process 5 x in the bit names e g SAx Voltage channel names e g VDDx and the Voltage FSMs nam...

Page 440: ...cted power ICs PRCM PRM_VC_SMPS_CMD_RA 23 16 CMDRA1 4 Set configuration pointers for the VDD channels The configuration pointers allow the selection of one of four configurations for each voltage channel VDD1 and VDD2 Two slave I2 C interfaces slave address Two voltage configuration registers Two command configuration registers Two power mode voltage levels PRCM PRM_VC_CH_CONF 16 SA1 Slave address...

Page 441: ...ODE Master code for I2 C HS preamble PRCM PRM_VC_I2C_CFG 3 HSEN 0x0 Switch to F S mode PRCM PRM_VC_I2C_CFG 4 SREN 0x0 Disable repeated start operation 441 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Copyright 2009 2010 Texas Instruments Incorporated ...

Page 442: ...et SmartReflex and voltage processor interrupts Enable voltage processor OPP change done interrupt Yes Is Voltage Processor OPP Change Done interrupt to MPU generated No 4 Enable modules End b Switching from VDDx Vx Fx to VDDy Vy Fy where Fx Fy Enable SmartReflex VP bounds interrupt Set the SmartReflex error generator parameters corresponding to target OPPy Disable all SmartReflex interrupts to MP...

Page 443: ...ent OPP values read for the SCM register SRn NVALUERECIPROCAL 19 16 SENNGAIN See Section 3 5 6 5 4 5 Parameter Configuration SRn NVALUERECIPROCAL 15 8 RNSENP SRn NVALUERECIPROCAL 7 0 RNSENN SRn SRCONFIG 9 ERRORGENERATORENABLE 0x1 Enable the error generator 3 Set SmartReflex and voltage processor interrupts To automatically adjust the voltage from OPPx level to OPPy level the voltage processor inte...

Page 444: ...n_ OPPCHANGEDONE_ST Read On read if this bit is 0x1 the OPP change is complete PRCM PRM_IRQSTATUS_MPU VPn_ OPPCHANGEDONE_ST 0x1 Writing 0x1 clears the interrupt status bit 3 6 6 8 Changing OPP Using Only the Voltage Processor Module The device OPP change for the VDD1 or VDD2 voltage domains can also be handled through an alternate method of using only the voltage processor module In this case the ...

Page 445: ...del Figure 3 100 Voltage Processor OPP Change Flow Chart When switching from the current OPP to a target OPP if the clock frequency of the target OPP is less than that of current OPP the DPLL is first switched to the lower frequency of target OPP and only then the voltage scaling is initiated However if the clock frequency of the target OPP is greater than that of current OPP voltage scaling is in...

Page 446: ...een on and off or placed in idled mode This is intended to implement an efficient activity modulation of the MPU power state with minimum software support When the event generator is activated the PRCM module ensures that the CORE power domain always follows the MPU power domain activity The PRCM PM_EVGENONTIM_MPU and PRCM PM_EVGENOFFTIM_MPU registers of the event generator counter allow the confi...

Page 447: ... The DVFS power management technique consists of running a module at the lowest operating point frequency voltage that strictly meets the performance requirement at a given time In the device DVFS consists of dynamically switching the voltages and operating frequencies of the device subsections modules to ensure that power consumption is minimized Figure 3 101 is an overview of DVFS management in ...

Page 448: ...ublic Version PRCM Use Cases and Tips www ti com Figure 3 102 VDD1 and VDD2 Voltage Domain Modules and Clock Sources Both VDD1 and VDD2 voltage domains support different operations and the clocks in these voltage domains can be scaled according to the operating performance points as explained in Section 3 5 3 8 3 7 1 2 TWL5030 DVFS Support Architecture 3 7 1 2 1 SMPS The TWL5030 contains two Smart...

Page 449: ...nds a second I2 C data byte which the TWL5030 loads into the register that is addressed The command to the TWL5030 is executed when the particular internal register is loaded with the desired value the TWL5030 acknowledges the byte immediately before loading the register Figure 3 103 shows the I2 C communication protocol for the device and the TWL5030 Figure 3 103 DeviceTWL5030 I2 C Communication ...

Page 450: ... Voltage Control Registers continued Bit Function Description Reset Value 6 0 VSEL Output voltage 0x30 Output voltage VSEL 12 5 mV 0 6 V According to the reset value of the register the VDDx is active and set to 1 2 V where x can be 1 or 2 For more information about the TWL5030 see the TWL5030 technical reference manual 3 7 1 3 DVFS Using SmartReflex This use case describes the initialization sequ...

Page 451: ...for VDD1 and OPP100 is selected as the initial operating point for VDD2 the corresponding reciprocal reference value parameters are read from the corresponding eFuse data see Section 3 5 6 5 4 5 Parameter Configuration SRn NVALUERECIPROCAL 23 20 SENPGAIN Configured according to the settings in eFuse SRn NVALUERECIPROCAL 19 16 SENNGAIN for the current operating voltage level SRn NVALUERECIPROCAL 15...

Page 452: ...oup ID5 of TWL5030 Set the voltage data configuration register address to that of the VDD1_SR_CONTROL and VDD2_SR_CONTROL registers of the TWL5030 PRCM PRM_VC_SMPS_VOL_RA 7 0 VOLRA0 0x0 VDD1_SR_CONTROL register address PRCM PRM_VC_SMPS_VOL_RA 23 16 VOLRA1 0x1 VDD2_SR_CONTROL register address By default the voltage controller pointers are configured to use the corresponding slave and register addre...

Page 453: ...on SR1 NVALUERECIPROCAL 15 8 RNSENP SR1 NVALUERECIPROCAL 7 0 RNSENN SR1 SRCONFIG 9 ERRORGENERATORENABLE 0x1 Enable the error generator The OPP change done interrupt of voltage processor1 and the voltage processor bounds interrupt of the SmartReflex1 module are enabled The remaining interrupts of the voltage processor and SmartReflex modules can be masked SR1 ERRCONFIG 22 VPBOUNDSINTENABLE 0x1 Enab...

Page 454: ...nge is complete and the voltage is stable PRCM PRM_IRQSTATUS_MPU 10 VP1_ Read On read if this bit is 0x1 the OPP change is complete OPPCHANGEDONE_ST PRCM PRM_IRQSTATUS_MPU 10 VP1_ 0x1 Writing 0x1 clears the Interrupt status bit OPPCHANGEDONE_ST Enable the voltage processor1 interrupt for automatic SmartReflex1 operation SR1 ERRCONFIG 22 VPBOUNDSINTENABLE 0x1 Enable the voltage processor bounds int...

Page 455: ...The SmartReflex2 module sends the OPP change done interrupt when the OPP change is complete and the voltage is stable PRCM PRM_IRQSTATUS_MPU 16 VP2_ Read On read if this bit is 0x 1 the OPP change is complete OPPCHANGEDONE_ST PRCM PRM_IRQSTATUS_MPU 16 VP2_ 0x1 Writing 0x1 clears the interrupt status bit OPPCHANGEDONE_ST Enable the voltage processor2 bounds interrupt for automatic SmartReflex2 oper...

Page 456: ...Voltage Control Using VMODE 3 7 2 1 Introduction The PRCM module allows direct simple control of VDD1 and VDD2 through the dedicated signals sys_nvmode1 and sys_nvmode2 A single voltage value can be linked in the external power IC to a given state of sys_nvmode1 or sys_nvmode2 This allows direct voltage management see Table 3 94 Table 3 94 VDD1 and VDD2 Voltage Control Through VMODE sys_nvmode Sig...

Page 457: ... the VMODE signals remain high or low until a transition is initiated Their states then automatically toggle to the opposite state and return when the reverse transition is initiated 4 Set the voltage stabilization delays PRM_VOLTSETUP1 31 16 SETUP_TIME2 VDD2 voltage stabilization time PRM_VOLTSETUP1 15 0 SETUP_TIME1 VDD1 voltage stabilization time SETUP_TIME1 and SETUP_TIME2 are power IC dependen...

Page 458: ...d VDD2 voltage values are set with regards to sys_nvmode1 and sys_nvmode2 low and high states Has a sleep wake up transition been initiated Sys_nvmode1 and sys_nvmode2 automatically toggle Set the voltage stabilization delays Set PRM_VOLTSETUP1 register Wait for stabilization time VDD1 and VDD2 are set to the desired values prcm UC 014 Public Version PRCM Use Cases and Tips www ti com 3 7 2 2 3 Su...

Page 459: ...RE_CM 0x4800 4A00 8192 bytes SGX_CM 0x4800 4B00 8192 bytes WKUP_CM 0x4800 4C00 8192 bytes Clock_Control_Reg_CM 0x4800 4D00 8192 bytes DSS_CM 0x4800 4E00 8192 bytes CAM_CM 0x4800 4F00 8192 bytes PER_CM 0x4800 5000 8192 bytes EMU_CM 0x4800 5100 8192 bytes Global_Reg_CM 0x4800 5200 8192 bytes NEON_CM 0x4800 5300 8192 bytes USBHOST_CM 0x4800 5400 8192 bytes 3 8 1 2 IVA2_CM Registers 3 8 1 2 1 IVA2_CM ...

Page 460: ...RW 0x0 0x0 IVA2_CLK is disabled 0x1 IVA2_CLK is enabled Table 3 98 Register Call Summary for Register CM_FCLKEN_IVA2 PRCM Basic Programming Model CM_FCLKEN_ domain_name Functional Clock Enable Register 0 PRCM Register Manual IVA2_CM Register Summary 1 Table 3 99 CM_CLKEN_PLL_IVA2 Address Offset 0x0000 0004 Physical Address 0x4800 4004 Instance IVA2_CM Description This register controls the IVA2 DP...

Page 461: ... IVA2 DPLL automatic recalibration mode 2 0 EN_IVA2_DPLL IVA2 DPLL control Other enums Reserved RW 0x1 0x1 Put the IVA2 DPLL in low power stop mode 0x5 Put the IVA2 DPLL in low power bypass mode 0x7 Enables the IVA2 DPLL in lock mode Table 3 100 Register Call Summary for Register CM_CLKEN_PLL_IVA2 PRCM Functional Description DPLL Modes 0 DPLL Low Power Mode 1 Recalibration 2 DPLL Source Clock Cont...

Page 462: ...iption Type Reset 31 1 RESERVED Read returns 0 R 0x00000000 0 ST_IVA2_CLK IVA2_CLK activity R 0x0 0x0 IVA2 DPLL is bypassed 0x1 IVA2 DPLL is locked Table 3 104 Register Call Summary for Register CM_IDLEST_PLL_IVA2 PRCM Basic Programming Model CM_IDLEST_PLL_ processor_name Processor DPLL Idle Status Register 0 PRCM Register Manual IVA2_CM Register Summary 1 Table 3 105 CM_AUTOIDLE_PLL_IVA2 Address ...

Page 463: ...7 6 5 4 3 2 1 0 RESERVED IVA2_DPLL_MULT IVA2_DPLL_DIV RESERVED IVA2_CLK_SRC Bits Field Name Description Type Reset 31 22 RESERVED Write 0s for future compatibility Read returns 0 R 0x000 21 19 IVA2_CLK_SRC Selects the IVA2 DPLL bypass source clock Other RW 0x1 enums Reserved 0x1 DPLL2_FCLK is CORE_CLK divided by 1 0x2 DPLL2_FCLK is CORE CLK divided by 2 0x4 DPLL2_FCLK is CORE CLK divided by 4 18 8...

Page 464: ...ided by 3 0x4 DPLL2 CLKOUTX2 divided by 4 0x5 DPLL2 CLKOUTX2 divided by 5 0x6 DPLL2 CLKOUTX2 divided by 6 0x7 DPLL2 CLKOUTX2 divided by 7 0x8 DPLL2 CLKOUTX2 divided by 8 0x9 DPLL2 CLKOUTX2 divided by 9 0xA DPLL2 CLKOUTX2 divided by 10 0xB DPLL2 CLKOUTX2 divided by 11 0xC DPLL2 CLKOUTX2 divided by 12 0xD DPLL2 CLKOUTX2 divided by 13 0xE DPLL2 CLKOUTX2 divided by 14 0xF DPLL2 CLKOUTX2 divided by 15 ...

Page 465: ...upervised sleep transition on the domain 0x2 Start a software supervised wake up transition on the domain 0x3 Automatic transition is enabled Transition is supervised by the HardWare Table 3 112 Register Call Summary for Register CM_CLKSTCTRL_IVA2 PRCM Functional Description Device Wake Up Events 0 1 2 PRCM Basic Programming Model CM_CLKSTCTRL_ domain_name Clock State Control Register 3 PRCM Regis...

Page 466: ...0 0000 0x4800 4800 C CM_SYSCONFIG RW 32 0x0000 0010 0x4800 4810 W 3 8 1 3 2 OCP_System_Reg_CM Registers Table 3 116 CM_REVISION Address Offset 0x0000 0000 Physical Address 0x4800 4800 Instance OCP_System_Reg_CM Description This register contains the IP revision code for the CM part of the PRCM Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED REV...

Page 467: ...l Summary for Register CM_SYSCONFIG PRCM Basic Programming Model PRCM Configuration Registers 0 PRCM Register Manual OCP_System_Reg_CM Register Summary 1 3 8 1 4 MPU_CM Registers 3 8 1 4 1 MPU_CM Register Summary Table 3 120 MPU_CM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type Bits CM_CLKEN_PLL_MPU RW 32 0x0000 0004 0x4800 4904 W CM_IDLEST_MPU R 32 0...

Page 468: ...quence 0x1 Enables the DPLL LP mode to enter the LP mode at the following lock or re lock sequence 9 8 RESERVED RW 0x0 7 4 RESERVED Reserved RW 0x1 3 EN_MPU_DPLL_DRIFTGUARD This bit allows to enable or disable the automatic RW 0x0 recalibration feature of the MPU DPLL The DPLL1 will automatically start a recalibration process upon assertion of the recal flag if this bit is set 0x0 Disables the DPL...

Page 469: ...anual MPU_CM Register Summary 1 Table 3 125 CM_IDLEST_PLL_MPU Address Offset 0x0000 0024 Physical Address 0x4800 4924 Instance MPU_CM Description This register allows monitoring the master clock activity This register is read only and automatically updated Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ST_MPU_CLK Bits Field Name Description Ty...

Page 470: ...ional Description DPLL Modes 0 DPLL Source Clock Controls 1 PRCM Basic Programming Model CM_AUTOIDLE_PLL_ processor_name Processor DPLL Autoidle Register 2 PRCM Register Manual MPU_CM Register Summary 3 Table 3 129 CM_CLKSEL1_PLL_MPU Address Offset 0x0000 0040 Physical Address 0x4800 4940 Instance MPU_CM Description This register provides controls over the MPU DPLL Type RW 31 30 29 28 27 26 25 24 ...

Page 471: ... Model CM_CLKSELn_PLL_ processor_name Processor DPLL Clock Selection Register 4 CM_CLKEN_PLL_ processor_name Processor DPLL Clock Enable Register 5 PRCM Use Cases and Tips Switch VDD1 OPPs 6 7 8 9 PRCM Register Manual MPU_CM Register Summary 10 MPU_CM Registers Table 3 131 CM_CLKSEL2_PLL_MPU Address Offset 0x0000 0044 Physical Address 0x4800 4944 Instance MPU_CM Description This register provides ...

Page 472: ...DPLL1 CLKOUTX2 divided by 14 0xF DPLL1 CLKOUTX2 divided by 15 0x10 DPLL1 CLKOUTX2 divided by 16 Table 3 132 Register Call Summary for Register CM_CLKSEL2_PLL_MPU PRCM Functional Description Processor Clock Configurations 0 PRCM Basic Programming Model CM_CLKSELn_PLL_ processor_name Processor DPLL Clock Selection Register 1 PRCM Register Manual MPU_CM Register Summary 2 Table 3 133 CM_CLKSTCTRL_MPU...

Page 473: ...provides a status on the clock activity in the domain MPU DPLL output clock Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKACTIVITY_MPU Bits Field Name Description Type Reset 31 1 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 0 CLKACTIVITY_MPU Clock activity status R 0x0 0x0 No domain clock activity 0x1 Domain clock...

Page 474: ...dule functional clock activity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED EN_I2C3 EN_I2C2 EN_I2C1 EN_HDQ EN_MMC3 EN_MMC2 EN_MMC1 EN_GPT11 EN_GPT10 EN_UART2 EN_UART1 RESERVED RESERVED RESERVED EN_MCSPI4 EN_MCSPI3 EN_MCSPI2 EN_MCSPI1 EN_MCBSP5 EN_MCBSP1 Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatib...

Page 475: ...ck is disabled 0x1 UART 2 functional clock is enabled 13 EN_UART1 UART 1 functional clock control RW 0x0 0x0 UART 1 functional clock is disabled 0x1 UART 1 functional clock is enabled 12 EN_GPT11 GPTIMER 11 functional clock control RW 0x0 0x0 GPTIMER 11 functional clock is disabled 0x1 GPTIMER 11 functional clock is enabled 11 EN_GPT10 GPTIMER 10 functional clock control RW 0x0 0x0 GPTIMER 10 func...

Page 476: ...VED Reserved for non GP devices RW 0x0 Table 3 141 Register Call Summary for Register CM_FCLKEN3_CORE PRCM Functional Description CM Source Clock Controls 0 CORE Power Domain Clock Controls 1 2 PRCM Basic Programming Model CM_FCLKEN_ domain_name Functional Clock Enable Register 3 PRCM Register Manual CORE_CM Register Summary 4 Table 3 142 CM_ICLKEN1_CORE Address Offset 0x0000 0010 Physical Address...

Page 477: ...0x0 0x0 McSPI 3 interface clock is disabled 0x1 McSPI 3 interface clock is enabled 19 EN_MCSPI2 McSPI 2 interface clock control RW 0x0 0x0 McSPI 2 interface clock is disabled 0x1 McSPI 2 interface clock is enabled 18 EN_MCSPI1 McSPI 1 interface clock control RW 0x0 0x0 McSPI 1 interface clock is disabled 0x1 McSPI 1 interface clock is enabled 17 EN_I2C3 I2C 3 interface clock control RW 0x0 0x0 I2C...

Page 478: ... OTG USB interface clock control RW 0x0 0x0 HS OTG USB interface clock is disabled 0x1 HS OTG USB interface clock is enabled 3 RESERVED Read returns 0 R 0x01 2 RESERVED Read returns 0 R 0x0 1 EN_SDRC SDRC interface clock control RW 0x1 0x0 SDRC interface clock is disabled 0x1 SDRC interface clock is enabled 0 RESERVED Read returns 0 RW 0x0 Table 3 143 Register Call Summary for Register CM_ICLKEN1_...

Page 479: ... 8 7 6 5 4 3 2 1 0 ST_ICR ST_I2C3 ST_I2C2 ST_I2C1 ST_HDQ ST_SDRC ST_SDMA ST_MMC3 ST_MMC2 ST_MMC1 ST_GPT11 ST_GPT10 ST_UART2 ST_UART1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ST_MCSPI4 ST_MCSPI3 ST_MCSPI2 ST_MCSPI1 ST_MCBSP5 ST_MCBSP1 ST_MAILBOXES ST_OMAPCTRL ST_HSOTGUSB_IDLE ST_HSOTGUSB_STDBY Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility Read ret...

Page 480: ...an error 16 ST_I2C2 I2C 2 idle status R 0x1 0x0 I2C 2 can be accessed 0x1 I2C 2 cannot be accessed Any access may return an error 15 ST_I2C1 I2C 1 idle status R 0x1 0x0 I2C 1 can be accessed 0x1 I2C 1 cannot be accessed Any access may return an error 14 ST_UART2 UART 2 idle status R 0x1 0x0 UART 2 can be accessed 0x1 UART 2 cannot be accessed Any access may return an error 13 ST_UART1 UART 1 idle ...

Page 481: ...standby mode 3 RESERVED Read returns 1 R 0x1 2 ST_SDMA System DMA standby status R 0x1 0x0 System DMA is active 0x1 System DMA is in standby mode 1 ST_SDRC SDRC idle status R 0x1 0x0 SDRC can be accessed 0x1 SDRC cannot be accessed Any access may return an error 0 RESERVED Read returns 1 R 0x1 Table 3 147 Register Call Summary for Register CM_IDLEST1_CORE PRCM Basic Programming Model CM_IDLEST_ do...

Page 482: ...ESERVED RESERVED RESERVED RESERVED RESERVED AUTO_HDQ AUTO_MMC3 AUTO_MMC2 AUTO_MMC1 AUTO_GPT11 AUTO_GPT10 AUTO_UART2 AUTO_UART1 AUTO_MCSPI4 AUTO_MCSPI3 AUTO_MCSPI2 AUTO_MCSPI1 AUTO_MCBSP5 AUTO_MCBSP1 AUTO_HSOTGUSB AUTO_MAILBOXES AUTO_OMAPCTRL Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 30 AUTO_MMC3 MMC SDIO 3 auto clock control RW 0x0 0...

Page 483: ..._MCSPI1 McSPI 1 auto clock control RW 0x0 0x0 McSPI 1 interface clock is unrelated to the domain state transition 0x1 McSPI 1 interface clock is automatically enabled or disabled along with the domain state transition 17 AUTO_I2C3 I2C 3 auto clock control RW 0x0 0x0 I2C 3 interface clock is unrelated to the domain state transition 0x1 I2C 3 interface clock is automatically enabled or disabled alon...

Page 484: ...s auto clock control RW 0x0 0x0 Mailboxes interface clock is unrelated to the domain state transition 0x1 Mailboxes interface clock is automatically enabled or disabled along with the domain state transition 6 AUTO_OMAPCTRL System Control Module auto clock control RW 0x0 0x0 SCM interface clock is unrelated to the domain state transition 0x1 SCM interface clock is automatically enabled or disabled...

Page 485: ...3 153 Register Call Summary for Register CM_AUTOIDLE3_CORE PRCM Basic Programming Model CM_AUTOIDLE_ domain_name Autoidle Register 0 PRCM Register Manual CORE_CM Register Summary 1 Table 3 154 CM_CLKSEL_CORE Address Offset 0x0000 0040 Physical Address 0x4800 4A40 Instance CORE_CM Description CORE modules clock selection Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ...

Page 486: ...onfigurations 4 5 PRCM Basic Programming Model CM_CLKSEL_ domain_name Clock Select Register 6 Enabling and Disabling the Interface Clocks 7 PRCM Register Manual CORE_CM Register Summary 8 Table 3 156 CM_CLKSTCTRL_CORE Address Offset 0x0000 0048 Physical Address 0x4800 4A48 Instance CORE_CM Description This register enables the domain power state transition It controls the HW supervised domain powe...

Page 487: ...R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKACTIVITY_L4 CLKACTIVITY_L3 Bits Field Name Description Type Reset 31 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 1 CLKACTIVITY_L4 L4_ICLK interface clock activity status R 0x0 0x0 No domain interface clock activity 0x1 Domain interface clock is active 0 CLKACTIVITY_L3 L3...

Page 488: ...ic engine functional clock activity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EN_SGX RESERVED Bits Field Name Description Type Reset 31 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 1 EN_SGX SGX functional clock enable RW 0x0 0x0 SGX_FCLK is disabled 0x1 SGX_FCLK is enabled 0 RESERVED Write 0s for future compat...

Page 489: ...M_ICLKEN_ domain_name Interface Clock Enable Register 1 PRCM Register Manual SGX_CM Register Summary 2 Table 3 165 CM_IDLEST_SGX Address Offset 0x0000 0020 Physical Address 0x4800 4B20 Instance SGX_CM Description SGX standby status This register is read only and automatically updated Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ST_SGX Bits F...

Page 490: ... functional clock is CORE_CLK divided by 2 0x6 SGX functional clock is COREX2_CLK divided by 3 0x7 SGX functional clock is COREX2_CLK divided by 5 Table 3 168 Register Call Summary for Register CM_CLKSEL_SGX PRCM Functional Description Interface and Peripheral Functional Clock Configurations 0 1 2 3 PRCM Basic Programming Model CM_CLKSEL_ domain_name Clock Select Register 4 5 6 PRCM Register Manua...

Page 491: ... state transition between ACTIVE and INACTIVE states Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKTRCTRL_SGX Bits Field Name Description Type Reset 31 2 RESERVED Write 0s for future compatibility Reads returns 0 R 0x00000000 1 0 CLKTRCTRL_SGX Controls the clock state transition of the SGX clock RW 0x0 domain 0x0 Automatic transition is d...

Page 492: ... clock is active Table 3 174 Register Call Summary for Register CM_CLKSTST_SGX PRCM Basic Programming Model CM_CLKSTST_ domain_name Clock State Status Register 0 PRCM Register Manual SGX_CM Register Summary 1 3 8 1 7 WKUP_CM Registers 3 8 1 7 1 WKUP_CM Register Summary Table 3 175 WKUP_CM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type Bits CM_FCLKEN_W...

Page 493: ...lock is enabled 5 EN_WDT2 WDTIMER 2 functional clock control RW 0x0 0x0 WDTIMER 2 functional clock is disabled 0x1 WDTIMER 2 functional clock is enabled 4 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 3 EN_GPIO1 GPIO 1 clock control RW 0x0 0x0 GPIO 1 functional clock is disabled 0x1 GPIO 1 functional clock is enabled 2 1 RESERVED Write 0s for future compatibility Read returns 0 R...

Page 494: ... RW 0x0 0x0 GPIO 1 interface clock is disabled 0x1 GPIO 1 interface clock is enabled 2 EN_32KSYNC 32 kHz Sync Timer interface clock control RW 0x0 0x0 32k Sync Timer interface clock is disabled 0x1 32k Sync Timer interface clock is enabled 1 RESERVED Reserved for non GP devices RW 0x0 0 EN_GPT1 GPTIMER 1 interface clock control RW 0x0 0x0 GPTIMER 1 interface clock is disabled 0x1 GPTIMER 1 interfa...

Page 495: ... 0x0 WDTIMER 2 can be accessed 0x1 WDTIMER 2 cannot be accessed Any access may return an error 4 RESERVED Reserved for non GP devices R 0x1 3 ST_GPIO1 GPIO 1 idle status R 0x1 0x0 GPIO 1 can be accessed 0x1 GPIO 1 cannot be accessed Any access may return an error 2 ST_32KSYNC 32 kHz Sync Timer idle status R 0x1 0x0 32k Sync Timer can be accessed 0x1 32k Sync Timer cannot be accessed Any access may...

Page 496: ...vity 4 RESERVED Reserved for non GP devices RW 0x0 3 AUTO_GPIO1 GPIO 1 autoidle control RW 0x0 0x0 GPIO 1 interface clock is unrelated to the domain activity 0x1 GPIO 1 interface clock is automaticaly enabled disabled according to the domain activity 2 AUTO_32KSYNC 32 kHz Sync Timer autoidle control RW 0x0 0x0 32k Sync Timer interface clock is unrelated to the domain activity 0x1 32k Sync Timer in...

Page 497: ...and Peripheral Functional Clock Configurations 0 PRCM Basic Programming Model CM_CLKSEL_ domain_name Clock Select Register 1 PRCM Register Manual WKUP_CM Register Summary 2 3 8 1 8 Clock_Control_Reg_CM Registers 3 8 1 8 1 Clock_Control_Reg_CM Register Summary Table 3 186 Clock_Control_Reg_CM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type Bits CM_CLKEN...

Page 498: ...LL4_M6_CLK HSDIVIDER path 0x1 Power down the DPLL4_M6_CLK HSDIVIDER path Writting this bit to 1 will take effect immediatly 30 PWRDN_CAM This bit allows to power down or not the DPLL4_M5_CLK RW 0x0 HSDIVIDER path 0x0 Power up the DPLL4_M5_CLK HSDIVIDER path 0x1 Power down the DPLL4_M5_CLK HSDIVIDER path Writting this bit to 1 will take effect immediatly 29 PWRDN_DSS1 This bit allows to power down ...

Page 499: ...g this bit to 1 will take effect immediatly 11 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 10 EN_CORE_DPLL_LPMODE This bit allows to enable or disable the LP mode of the RW 0x0 DPLL3 Writting this bit to switch the mode between LP or normal mode will take effect only when the DPLL will have transition into the bypass or stop state followed by a lock or re lock of the DPLL 0x0 D...

Page 500: ... Writting this bit to switch the mode between LP or normal mode will take effect only when the DPLL will have transition into the bypass or stop state followed by a lock or re lock of the DPLL 0x0 Disables the DPLL LP mode to re enter the normal mode at the following lock or re lock sequence 0x1 Enables the DPLL LP mode to enter the LP mode at the following lock or re lock sequence 9 8 RESERVED RW...

Page 501: ... activity at the output stage of the DPLL4 R 0x0 0x0 EMU_PER_ALWON_CLK is not active 0x1 EMU_PER_ALWON_CLK is active 12 ST_CAM_CLK CAMERA functional clock activity at the output stage of R 0x0 the DPLL4 0x0 CAM_MCLK is not active 0x1 CAM_MCLK is active 11 ST_DSS1_CLK DSS functional clock 1 activity at the output stage of the R 0x0 DPLL4 0x0 DSS1_ALWON_FCLK is not active 0x1 DSS1_ALWON_FCLK is acti...

Page 502: ...ddress Offset 0x0000 0024 Physical Address 0x4800 4D24 Instance Clock_Control_Reg_CM Description This register allows monitoring the master clock activity This register is read only and automatically updated Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED ST_120M_CLK ST_PERIPH2_CLK ST_FUNC120M_CLK Bits Field Name Description Type Reset...

Page 503: ...RW 0x0 0x0 Auto control disabled 0x1 DPLL4 is automatically put in low power stop mode when none of the 96 MHz and 54 MHz clocks are required anymore It is also restarted automatically 2 0 AUTO_CORE_DPLL DPLL3 automatic control Other enums Reserved RW 0x0 0x0 Auto control disabled 0x1 DPLL3 is automatically put in low power stop mode when the CORE clock is not required anymore It is also restarted...

Page 504: ...p mode when the 120 MHz clock is not required anymore It is also restarted automatically Table 3 198 Register Call Summary for Register CM_AUTOIDLE2_PLL PRCM Functional Description DPLL Modes 0 DPLL Source Clock Controls 1 PRCM Register Manual Clock_Control_Reg_CM Register Summary 2 Table 3 199 CM_CLKSEL1_PLL Address Offset 0x0000 0040 Physical Address 0x4800 4D40 Instance Clock_Control_Reg_CM Des...

Page 505: ...s divided by 22 0x17 DPLL3 output clock is divided by 23 0x18 DPLL3 output clock is divided by 24 0x19 DPLL3 output clock is divided by 25 0x1A DPLL3 output clock is divided by 26 0x1B DPLL3 output clock is divided by 27 0x1C DPLL3 output clock is divided by 28 0x1D DPLL3 output clock is divided by 29 0x1E DPLL3 output clock is divided by 30 0x1F DPLL3 output clock is divided by 31 26 16 CORE_DPLL...

Page 506: ...s register bits field allows setting the sigma delta RW 0x02 divider factor of the PERIPHERAL DPLL It must be comprise between 2 and 255 The values 0 and 1 are reserved 23 21 DCO_SEL This register bits field allows selecting the DCO used by RW 0x2 the PERIPHERAL DPLL to synthesize its output clock Other enums Reserved 0x2 The lock frequency is comprised between 500 MHz and 1000 MHz 0x4 The lock fr...

Page 507: ... clock is DPLL4 clock divided by 12 0xD 96 MHz clock is DPLL4 clock divided by 13 0xE 96 MHz clock is DPLL4 clock divided by 14 0xF 96 MHz clock is DPLL4 clock divided by 15 0x10 96 MHz clock is DPLL4 clock divided by 16 0x11 96 MHz clock is DPLL4 clock divided by 17 0x12 96 MHz clock is DPLL4 clock divided by 18 0x13 96 MHz clock is DPLL4 clock divided by 19 0x14 96 MHz clock is DPLL4 clock divid...

Page 508: ...ite 0s for future compatibility Read returns 0 R 0x0 6 0 PERIPH2_DPLL_DIV DPLL5 divider factor 0 to 127 RW 0x00 Table 3 206 Register Call Summary for Register CM_CLKSEL4_PLL PRCM Basic Programming Model CM_CLKSELn_PLL DPLL Clock Selection Register 0 PRCM Register Manual Clock_Control_Reg_CM Register Summary 1 Clock_Control_Reg_CM Registers Table 3 207 CM_CLKSEL5_PLL Address Offset 0x0000 0050 Phys...

Page 509: ...d by 14 0xF 120 MHz clock is DPLL5 clock divided by 15 0x10 120 MHz clock is DPLL5 clock divided by 16 Table 3 208 Register Call Summary for Register CM_CLKSEL5_PLL PRCM Basic Programming Model CM_CLKSELn_PLL DPLL Clock Selection Register 0 PRCM Register Manual Clock_Control_Reg_CM Register Summary 1 Table 3 209 CM_CLKOUT_CTRL Address Offset 0x0000 0070 Physical Address 0x4800 4D70 Instance Clock_...

Page 510: ...ster Summary Table 3 211 DSS_CM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type Bits CM_FCLKEN_DSS RW 32 0x0000 0000 0x4800 4E00 W CM_ICLKEN_DSS RW 32 0x0000 0010 0x4800 4E10 W CM_IDLEST_DSS R 32 0x0000 0020 0x4800 4E20 C CM_AUTOIDLE_DSS RW 32 0x0000 0030 0x4800 4E30 W CM_CLKSEL_DSS RW 32 0x0000 0040 0x4800 4E40 W CM_SLEEPDEP_DSS RW 32 0x0000 0044 0x48...

Page 511: ...rol Register 4 PRCM Register Manual DSS_CM Register Summary 5 Table 3 214 CM_ICLKEN_DSS Address Offset 0x0000 0010 Physical Address 0x4800 4E10 Instance DSS_CM Description Controls the modules interface clock activity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EN_DSS Bits Field Name Description Type Reset 31 1 RESERVED Write 0s for future...

Page 512: ...mary for Register CM_IDLEST_DSS PRCM Basic Programming Model CM_IDLEST_ domain_name Idle Status Register 0 PRCM Register Manual DSS_CM Register Summary 1 Table 3 218 CM_AUTOIDLE_DSS Address Offset 0x0000 0030 Physical Address 0x4800 4E30 Instance DSS_CM Description This register controls the automatic control of the modules interface clock activity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 513: ...PRCM Register Manual DSS_CM Register Summary 2 Table 3 220 CM_CLKSEL_DSS Address Offset 0x0000 0040 Physical Address 0x4800 4E40 Instance DSS_CM Description Modules clock selection Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKSEL_TV CLKSEL_DSS1 RESERVED 513 SWPU177N December 2009 Revised November 2010 Power Reset and Clock Management Cop...

Page 514: ...ided by 14 0xF TV functional clock is DPLL4 clock divided by 15 0x10 TV functional clock is DPLL4 clock divided by 16 0x11 TV functional clock is DPLL4 clock divided by 17 0x12 TV functional clock is DPLL4 clock divided by 18 0x13 TV functional clock is DPLL4 clock divided by 19 0x14 TV functional clock is DPLL4 clock divided by 20 0x15 TV functional clock is DPLL4 clock divided by 21 0x16 TV func...

Page 515: ...L4 clock divided by 16 0x11 DSS1_ALWON_FCLK is DPLL4 clock divided by 17 0x12 DSS1_ALWON_FCLK is DPLL4 clock divided by 18 0x13 DSS1_ALWON_FCLK is DPLL4 clock divided by 19 0x14 DSS1_ALWON_FCLK is DPLL4 clock divided by 20 0x15 DSS1_ALWON_FCLK is DPLL4 clock divided by 21 0x16 DSS1_ALWON_FCLK is DPLL4 clock divided by 22 0x17 DSS1_ALWON_FCLK is DPLL4 clock divided by 23 0x18 DSS1_ALWON_FCLK is DPL...

Page 516: ... MPU domain is disabled 0x1 DSS domain sleep dependency with MPU domain is enabled 0 EN_CORE CORE domain dependency RW 0 0x0 DSS domain sleep dependency with CORE domain is disabled 0x1 DSS domain sleep dependency with CORE domain is enabled Table 3 223 Register Call Summary for Register CM_SLEEPDEP_DSS PRCM Basic Programming Model CM_SLEEPDEP_ domain_name Sleep Dependency Control Register 0 PRCM ...

Page 517: ...Table 3 226 CM_CLKSTST_DSS Address Offset 0x0000 004C Physical Address 0x4800 4E4C Instance DSS_CM Description This register provides a status on the OCP interface clock activity in the domain Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKACTIVITY_DSS Bits Field Name Description Type Reset 31 1 RESERVED Write 0s for future compatibility Re...

Page 518: ...Controls the modules functional clock activity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EN_CSI2 EN_CAM Bits Field Name Description Type Reset 31 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 1 EN_CSI2 CSI2 functional clock control 96 MHz RW 0x0 0x0 CSI2_96M_FCLK is disabled 0x1 CSI2_96M_FCLK is enabled 0 EN_CA...

Page 519: ...g Model CM_ICLKEN_ domain_name Interface Clock Enable Register 1 PRCM Register Manual CAM_CM Register Summary 2 Table 3 233 CM_IDLEST_CAM Address Offset 0x0000 0020 Physical Address 0x4800 4F20 Instance CAM_CM Description Modules access availability monitoring This register is read only and automatically updated Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 520: ...the domain state transition 0x1 Camera clock is automatically enabled or disabled along with the domain state transition Table 3 236 Register Call Summary for Register CM_AUTOIDLE_CAM PRCM Functional Description CAM Power Domain Clock Controls 0 PRCM Basic Programming Model CM_AUTOIDLE_ domain_name Autoidle Register 1 PRCM Register Manual CAM_CM Register Summary 2 Table 3 237 CM_CLKSEL_CAM Address...

Page 521: ...vided by 15 0x10 CAM_MCLK is DPLL4 clock divided by 16 0x11 CAM_MCLK is DPLL4 clock divided by 17 0x12 CAM_MCLK is DPLL4 clock divided by 18 0x13 CAM_MCLK is DPLL4 clock divided by 19 0x14 CAM_MCLK is DPLL4 clock divided by 20 0x15 CAM_MCLK is DPLL4 clock divided by 21 0x16 CAM_MCLK is DPLL4 clock divided by 22 0x17 CAM_MCLK is DPLL4 clock divided by 23 0x18 CAM_MCLK is DPLL4 clock divided by 24 0...

Page 522: ...sabled 0x1 CAM domain sleep dependency with MPU domain is enabled 0 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 Table 3 240 Register Call Summary for Register CM_SLEEPDEP_CAM PRCM Basic Programming Model CM_SLEEPDEP_ domain_name Sleep Dependency Control Register 0 PRCM Register Manual CAM_CM Register Summary 1 Table 3 241 CM_CLKSTCTRL_CAM Address Offset 0x0000 0048 Physical Add...

Page 523: ...4 Table 3 243 CM_CLKSTST_CAM Address Offset 0x0000 004C Physical Address 0x4800 4F4C Instance CAM_CM Description This register provides a status on the OCP interface clock activity in the domain Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKACTIVITY_CAM Bits Field Name Description Type Reset 31 1 RESERVED Write 0s for future compatibility ...

Page 524: ...CBSP3 EN_MCBSP2 Bits Field Name Description Type Reset 31 19 RESERVED Write 0s for future compatibility Read returns 0 R 0x0000 18 EN_UART4 UART4 functional clock control RW 0x0 0x0 UART 4 functional clock is disabled 0x1 UART 4 functional clock is enabled 17 EN_GPIO6 GPIO 6 functional clock control RW 0x0 0x0 GPIO 6 functional clock is disabled 0x1 GPIO 6 functional clock is enabled 16 EN_GPIO5 G...

Page 525: ...lock is disabled 0x1 GPTIMER 4 functional clock is enabled 4 EN_GPT3 GPTIMER 3 functional clock control RW 0x0 0x0 GPTIMER 3 functional clock is disabled 0x1 GPTIMER 3 functional clock is enabled 3 EN_GPT2 GPTIMER 2 functional clock control RW 0x0 0x0 GPTIMER 2 functional clock is disabled 0x1 GPTIMER 2 functional clock is enabled 2 EN_MCBSP4 McBSP 4 functional clock control RW 0x0 0x0 McBSP 4 fun...

Page 526: ...PIO4 GPIO 4 interfface clock control RW 0x0 0x0 GPIO 4 interface clock is disabled 0x1 GPIO 4 interface clock is enabled 14 EN_GPIO3 GPIO 3 interface clock control RW 0x0 0x0 GPIO 3 interface clock is disabled 0x1 GPIO 3 interface clock is enabled 13 EN_GPIO2 GPIO 2 interface clock control RW 0x0 0x0 GPIO 2 interface clock is disabled 0x1 GPIO 2 interface clock is enabled 12 EN_WDT3 WDTIMER 3 inte...

Page 527: ...SP 3 interface clock control RW 0x0 0x0 McBSP 3 interface clock is disabled 0x1 McBSP 3 interface clock is enabled 0 EN_MCBSP2 McBSP 2 interface clock control RW 0x0 0x0 McBSP 2 interface clock is disabled 0x1 McBSP 2 interface clock is enabled Table 3 249 Register Call Summary for Register CM_ICLKEN_PER PRCM Functional Description PER Power Domain Clock Controls 0 PRCM Basic Programming Model CM_...

Page 528: ...urn an error 12 ST_WDT3 WDTIMER 3 idle status R 0x1 0x0 WDTIMER 3 can be accessed 0x1 WDTIMER 3 cannot be accessed Any access may return an error 11 ST_UART3 UART3 idle status R 0x1 0x0 UART 3 can be accessed 0x1 UART 3 cannot be accessed Any access may return an error 10 ST_GPT9 GPTIMER 9 idle status R 0x1 0x0 GPTIMER 9 can be accessed 0x1 GPTIMER 9 cannot be accessed Any access may return an err...

Page 529: ...ister CM_IDLEST_PER PRCM Basic Programming Model CM_IDLEST_ domain_name Idle Status Register 0 PRCM Register Manual PER_CM Register Summary 1 Table 3 252 CM_AUTOIDLE_PER Address Offset 0x0000 0030 Physical Address 0x4800 5030 Instance PER_CM Description This register controls the automatic control of the modules interface clock activity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 530: ...0 WDTIMER 3 interface clock is unrelated to the domain state transition 0x1 WDTIMER 3 interface clock is automatically enabled or disabled along with the domain state transition 11 AUTO_UART3 UART3 auto clock control RW 0x0 0x0 UART 3 interface clock is unrelated to the domain state transition 0x1 UART 3 interface clock is automatically enabled or disabled along with the domain state transition 10...

Page 531: ...s automatically enabled or disabled along with the domain state transition 2 AUTO_MCBSP4 McBSP 4 auto clock control RW 0x0 0x0 McBSP 4 interface clock is unrelated to the domain state transition 0x1 McBSP 4 interface clock is automatically enabled or disabled along with the domain state transition 1 AUTO_MCBSP3 McBSP 3 auto clock control RW 0x0 0x0 McBSP 3 interface clock is unrelated to the domai...

Page 532: ...CLK 5 CLKSEL_GPT7 Selects GPTIMER 7 source clock RW 0x0 0x0 source is 32K_FCLK 0x1 source is SYS_CLK 4 CLKSEL_GPT6 Selects GPTIMER 6 source clock RW 0x0 0x0 source is 32K_FCLK 0x1 source is SYS_CLK 3 CLKSEL_GPT5 Selects GPTIMER 5 source clock RW 0x0 0x0 source is 32K_FCLK 0x1 source is SYS_CLK 2 CLKSEL_GPT4 Selects GPTIMER 4 source clock RW 0x0 0x0 source is 32K_FCLK 0x1 source is SYS_CLK 1 CLKSEL...

Page 533: ...cy RW 0x0 0x0 PER domain sleep dependency with MPU domain is disabled 0x1 PER domain sleep dependency with MPU domain is enabled 0 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 Table 3 257 Register Call Summary for Register CM_SLEEPDEP_PER PRCM Basic Programming Model CM_SLEEPDEP_ domain_name Sleep Dependency Control Register 0 PRCM Register Manual PER_CM Register Summary 1 Tabl...

Page 534: ...y 4 Table 3 260 CM_CLKSTST_PER Address Offset 0x0000 004C Physical Address 0x4800 504C Instance PER_CM Description This register provides a status on the OCP interface clock activity in the domain Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKACTIVITY_PER Bits Field Name Description Type Reset 31 1 RESERVED Write 0s for future compatibilit...

Page 535: ...W 0x04 Reserved 0x1 EMU_PER_ALWON_CLK is DPLL4 clock divided by 1 0x2 EMU_PER_ALWON_CLK is DPLL4 clock divided by 2 0x3 EMU_PER_ALWON_CLK is DPLL4 clock divided by 3 0x4 EMU_PER_ALWON_CLK is DPLL4 clock divided by 4 0x5 EMU_PER_ALWON_CLK is DPLL4 clock divided by 5 0x6 EMU_PER_ALWON_CLK is DPLL4 clock divided by 6 0x7 EMU_PER_ALWON_CLK is DPLL4 clock divided by 7 0x8 EMU_PER_ALWON_CLK is DPLL4 clo...

Page 536: ...0x3 EMU_CORE_ALWON_CLK is DPLL3 clock divided by 3 0x4 EMU_CORE_ALWON_CLK is DPLL3 clock divided by 4 0x5 EMU_CORE_ALWON_CLK is DPLL3 clock divided by 5 0x6 EMU_CORE_ALWON_CLK is DPLL3 clock divided by 6 0x7 EMU_CORE_ALWON_CLK is DPLL3 clock divided by 7 0x8 EMU_CORE_ALWON_CLK is DPLL3 clock divided by 8 0x9 EMU_CORE_ALWON_CLK is DPLL3 clock divided by 9 0xA EMU_CORE_ALWON_CLK is DPLL3 clock divid...

Page 537: ...ivided by 4 10 8 CLKSEL_PCLK Selects the PCLK clock Other enums Reserved RW 0x2 0x2 PCLK FCLK is the selected PCLK source clock divided by 2 0x3 PCLK FCLK is the selected PCLK source clock divided by 3 0x4 PCLK FCLK is the selected PCLK source clock divided by 4 0x6 PCLK FCLK is the selected PCLK source clock divided by 6 7 6 CLKSEL_PCLKX2 Selects the PCLKx2 clock Other enums Reserved RW 0x1 0x1 P...

Page 538: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKTRCTRL_EMU Bits Field Name Description Type Reset 31 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 1 0 CLKTRCTRL_EMU Controls the clock state transition of the EMULATION RW 0x2 clock domain 0x0 Reserved 0x1 Start a software supervised sleep transition on the domain 0x2 Start a software supervised wake up transit...

Page 539: ...s Register 0 PRCM Register Manual EMU_CM Register Summary 1 Table 3 269 CM_CLKSEL2_EMU Address Offset 0x0000 0050 Physical Address 0x4800 5150 Instance EMU_CM Description This register provides override controls over the DPLL3 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CORE_DPLL_EMU_MULT CORE_DPLL_EMU_DIV RESERVED OVERRIDE_ENABLE Bits Fie...

Page 540: ... OVERRIDE_ENABLE This bit allows to enable or disable the emulation override RW 0x0 controls 0x0 The emulation override controls are disabled 0x1 The emulation override controls are enabled 18 8 PERIPH_DPLL_EMU_MULT DPLL4 override multiplier factor 0 to 2047 RW 0x000 7 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 6 0 PERIPH_DPLL_EMU_DIV DPLL4 override divider factor 0 to 127 RW ...

Page 541: ...is gated low when inactive 0x1 sys_clkout2 is gated high when inactive Table 3 275 Register Call Summary for Register CM_POLCTRL PRCM Functional Description External Output Clock2 sys_clkout2 Control 0 PRCM Basic Programming Model CM_POLCTRL CM Polarity Control Register 1 PRCM Register Manual Global_Reg_CM Register Summary 2 3 8 1 14 NEON_CM Registers 3 8 1 14 1 NEON_CM Register Summary Table 3 27...

Page 542: ..._NEON Address Offset 0x0000 0048 Physical Address 0x4800 5348 Instance NEON_CM Description This register enables the domain power state transition It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKTRCTRL_NEON Bits Field Name Description Type Reset 3...

Page 543: ... 5444 W CM_CLKSTCTRL_USBHOST RW 32 0x0000 0048 0x4800 5448 W CM_CLKSTST_USBHOST R 32 0x0000 004C 0x4800 544C C 3 8 1 15 2 USBHOST_CM Registers Table 3 282 CM_FCLKEN_USBHOST Address Offset 0x0000 0000 Physical Address 0x4800 5400 Instance USBHOST_CM Description Controls the modules functional clock activity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 544: ...s Field Name Description Type Reset 31 1 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 0 EN_USBHOST USB HOST interface clock control RW 0x0 0x0 USB HOST interface clock is disabled 0x1 USB HOST interface clock is enabled Table 3 285 Register Call Summary for Register CM_ICLKEN_USBHOST PRCM Functional Description USBHOST Power Domain Clock Controls 0 PRCM Basic Programming ...

Page 545: ...al Address 0x4800 5430 Instance USBHOST_CM Description This register controls the automatic control of the modules interface clock activity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AUTO_USBHOST Bits Field Name Description Type Reset 31 1 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 0 AUTO_USBHOST USB HOST auto ...

Page 546: ... IVA2 domain is disabled 0x1 USB HOST domain sleep dependency with IVA2 domain is enabled 1 EN_MPU MPU domain dependency RW 0x0 0x0 USB HOST domain sleep dependency with MPU domain is disabled 0x1 USB HOST domain sleep dependency with MPU domain is enabled 0 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 Table 3 291 Register Call Summary for Register CM_SLEEPDEP_USBHOST PRCM Basic...

Page 547: ...nctional Description Device Wake Up Events 0 1 2 PRCM Basic Programming Model CM_CLKSTCTRL_ domain_name Clock State Control Register 3 PRCM Register Manual USBHOST_CM Register Summary 4 Table 3 294 CM_CLKSTST_USBHOST Address Offset 0x0000 004C Physical Address 0x4800 544C Instance USBHOST_CM Description This register provides a status on the interface clock activity in the domain Type R 31 30 29 2...

Page 548: ...ck_Control_Reg_PRM 0x4830 6D00 8192 bytes DSS_PRM 0x4830 6E00 8192 bytes CAM_PRM 0x4830 6F00 8192 bytes PER_PRM 0x4830 7000 8192 bytes EMU_PRM 0x4830 7100 8192 bytes Global_Reg_PRM 0x4830 7200 65536 bytes NEON_PRM 0x4830 7300 8192 bytes USBHOST_PRM 0x4830 7400 8192 bytes 3 8 2 2 IVA2_PRM Registers 3 8 2 2 1 IVA2_PRM Register Summary Table 3 297 IVA2_PRM Register Summary Register Name Type Register...

Page 549: ...d Video Sequencer RW 0x1 hardware accelerator reset control 0x0 IVA2 MMU reset and Video Sequencer hardware accelerator reset are cleared 0x1 Resets IVA2 MMU and Video Sequencer hardware accelerator 0 RST1_IVA2 IVA2 DSP reset control RW 0x1 0x0 IVA2 DSP reset is cleared 0x1 Resets IVA2 DSP Table 3 299 Register Call Summary for Register RM_RSTCTRL_IVA2 PRCM Functional Description Local Reset Source...

Page 550: ...x1 Status bit is cleared to 0 12 EMULATION_VIDEO_HWA_RST Emulation reset RW 0x0 Read 0x0 No emulation reset Write 0x0 Status bit unchanged Read 0x1 Video Sequencer hardware accelerator has been reset upon an emulation reset Write 0x1 Status bit is cleared to 0 11 EMULATION_IVA2_RST Emulation reset RW 0x0 Read 0x0 No emulation reset Write 0x0 Status bit unchanged Read 0x1 IVA2 DSP has been reset up...

Page 551: ...ollowing an IVA2 domain wake up Write 0x1 Status bit is cleared to 0 1 GLOBALWARM_RST Global warm reset RW 0x0 Read 0x0 No Global warm reset Write 0x0 Status bit unchanged Read 0x1 IVA2 domain has been reset upon global warm reset Write 0x1 Status bit is cleared to 0 0 GLOBALCOLD_RST Global cold reset RW 0x1 Read 0x0 No global cold reset Write 0x0 Status bit unchanged Read 0x1 IVA2 domain has been...

Page 552: ...up event 0x1 IVA2 domain is woken up upon DSS domain wake up event 4 EN_WKUP WAKEUP domain dependency RW 0x1 0x0 IVA2 domain is independent of WKUP domain wake up event 0x1 IVA2 domain is woken up upon WKUP domain wake up event 3 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 1 EN_MPU MPU domain dependency RW 0x1 0x...

Page 553: ... enums R 0x3 Reserved 0x0 Reserved 0x1 Reserved 0x2 Reserved 0x3 L2 Flat memory is always ON when domain is ON 21 20 SHAREDL2CACHEFLATONSTA Shared L2 Cache and Flat memory state when domain is RW 0x3 TE ON 0x0 Shared L2 Cache and Flat memory is OFF when domain is ON 0x1 Reserved 0x2 Reserved 0x3 Shared L2 Cache and Flat memory is ON when domain is ON 19 18 L1FLATMEMONSTATE L1 Flat memory state whe...

Page 554: ...RETENTION 0x0 Shared L1 Cache and Flat memory is OFF when domain is in RETENTION state 0x1 Shared L1 Cache and Flat memory is retained when domain is in RETENTION state 7 4 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 3 MEMORYCHANGE Memory change control in ON state RW 0x0 0x0 Disable memory change 0x1 Enable memory change state in ON state This bit is automaticaly cleared when ...

Page 555: ...Flat memory state status R 0x3 0x0 L2 Flat memory is OFF 0x1 L2 Flat memory is in RETENTION 0x2 Reserved 0x3 L2 Flat memory is ON 9 8 SHAREDL2CACHEFLATSTATE Shared L2 Cache and Flat memory state status R 0x3 ST 0x0 Shared L2 Cache and Flat memory is OFF 0x1 Shared L2 Cache and Flat memory is in RETENTION 0x2 Reserved 0x3 Shared L2 Cache and Flat memory is ON 7 6 L1FLATMEMSTATEST L1 Flat memory sta...

Page 556: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED LASTLOGICSTATEENTERED LASTPOWERSTATEENTERED LASTL2FLATMEMSTATEENTERED LASTL1FLATMEMSTATEENTERED LASTSHAREDL2CACHEFLATSTATEENTERED LASTSHAREDL1CACHEFLATSTATEENTERED Bits Field Name Description Type Reset 31 12 RESERVED Read returns 0 R 0x00000 11 10 LASTL2FLATMEMSTATEENTE Last L2 Flat memory state entered RW 0x0 RED 0x0 L2 Flat mem...

Page 557: ...d RW 0x0 0x0 IVA2 domain was previously OFF 0x1 IVA2 domain was previously in RETENTION 0x2 IVA2 domain was previously INACTIVE 0x3 IVA2 domain was previously ON Table 3 309 Register Call Summary for Register PM_PREPWSTST_IVA2 PRCM Basic Programming Model PM_PREPWSTST_ domain_name Previous Power State Status Register 0 PRCM Register Manual IVA2_PRM Register Summary 1 Table 3 310 PRM_IRQSTATUS_IVA2...

Page 558: ...RQSTATUS_IVA2 PRCM Functional Description Recalibration 0 PRCM Interrupts 1 2 3 4 PRCM Basic Programming Model Interrupt Configuration Registers 5 PRCM Register Manual IVA2_PRM Register Summary 6 Table 3 312 PRM_IRQENABLE_IVA2 Address Offset 0x0000 00FC Physical Address 0x4830 60FC Instance IVA2_PRM Description The interrupt enable register allows masking unmasking the module internal sources of i...

Page 559: ...OCP_System_Reg PRM Register Summary Table 3 314 OCP_System_Reg_PRM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type Bits PRM_REVISION R 32 0x0000 0004 0x4830 6804 C PRM_SYSCONFIG RW 32 0x0000 0014 0x4830 6814 W PRM_IRQSTATUS_MPU RW 32 0x0000 0018 0x4830 6818 W PRM_IRQENABLE_MPU RW 32 0x0000 001C 0x4830 681C W 3 8 2 3 2 OCP_System_Reg_PRM Registers Table...

Page 560: ...Model PRCM Configuration Registers 0 PRCM Register Manual OCP_System_Reg PRM Register Summary 1 Table 3 319 PRM_IRQSTATUS_MPU Address Offset 0x0000 0018 Physical Address 0x4830 6818 Instance OCP_System_Reg_PRM Description This interrupt status register regroups all the status of the module internal events that can generate an interrupt Write 1 to a given bit resets this bit This registers applies ...

Page 561: ...s bit unchanged Read 0x1 ABB LDO transaction done event is true pending Write 0x1 Status bit is cleared to 0 25 SND_PERIPH_DPLL_ST DPLL5 recalibration event status RW 0x0 Read 0x0 DPLL5 recalibration event is false Write 0x0 Status bit unchanged Read 0x1 DPLL5 recalibration event is true pending Write 0x1 Status bit is cleared to 0 24 VC_TIMEOUTERR_ST Voltage Controller timeout error event status ...

Page 562: ...ssor 2 timeout event is false Write 0x0 Status bit unchanged Read 0x1 Voltage Processor 2 timeout event is true pending Write 0x1 Status bit is cleared to 0 18 VP2_MAXVDD_ST Voltage Processor 2 voltage higher limit event status RW 0x0 This status is set when the voltage higher limit is reached It is cleared by SW Read 0x0 Voltage Processor 2 voltage higher limit event is false Write 0x0 Status bit...

Page 563: ... timeout event is false Write 0x0 Status bit unchanged Read 0x1 Voltage Processor 1 timeout event is true pending Write 0x1 Status bit is cleared to 0 12 VP1_MAXVDD_ST Voltage Processor 1 voltage higher limit event status RW 0x0 This status is set when the voltage higher limit is reached It is cleared by SW Read 0x0 Voltage Processor 1 voltage higher limit event is false Write 0x0 Status bit uncha...

Page 564: ...alse Write 0x0 Status bit unchanged Read 0x1 DPLL3 recalibration event is true pending Write 0x1 Status bit is cleared to 0 4 TRANSITION_ST Software supervised transition completed event status RW 0x0 Read 0x0 Software supervised transition completed event is false Write 0x0 Status bit unchanged Read 0x1 Software supervised transition completed event is true pending Write 0x1 Status bit is cleared...

Page 565: ..._MAXVDD_EN VP1_MAXVDD_EN VP2_EQVALUE_EN VP1_EQVALUE_EN VC_BYPASS_ACK_EN VC_TIMEOUTERR_EN VP2_TRANXDONE_EN VP1_TRANXDONE_EN VP2_NOSMPSACK_EN VP1_NOSMPSACK_EN IVA2_DPLL_RECAL_EN MPU_DPLL_RECAL_EN CORE_DPLL_RECAL_EN PERIPH_DPLL_RECAL_EN ABB_LDO_TRANXDONE_EN VP2_OPPCHANGEDONE_EN VP1_OPPCHANGEDONE_EN SND_PERIPH_DPLL_RECAL_EN Bits Field Name Description Type Reset 31 29 RESERVED Write 0s for future comp...

Page 566: ...VP2_EQVALUE_EN Voltage Processor 2 voltage value change mask RW 0x0 0x0 Voltage Processor 2 voltage value change event is masked 0x1 Voltage Processor 2 voltage value change event generates an interrupt 19 VP2_NOSMPSACK_EN Voltage Processor 2 timeout mask RW 0x0 0x0 Voltage Processor 2 timeout event is masked 0x1 Voltage Processor 2 timeout event generates an interrupt 18 VP2_MAXVDD_EN Voltage Pro...

Page 567: ...d 0x1 IO pad event generates an interrupt 8 IVA2_DPLL_RECAL_EN IVA2 DPLL recalibration mask RW 0x0 0x0 IVA2 DPLL recalibration event is masked 0x1 IVA2 DPLL recalibration event generates an interrupt 7 MPU_DPLL_RECAL_EN DPLL1 recalibration mask RW 0x0 0x0 DPLL1 recalibration event is masked 0x1 DPLL1 recalibration event generates an interrupt 6 PERIPH_DPLL_RECAL_EN DPLL4 recalibration mask RW 0x0 ...

Page 568: ... Event Generator Programming Examples 34 PRCM Use Cases and Tips Switch VDD1 OPPs 35 36 Switch VDD2 OPPs 37 38 PRCM Register Manual OCP_System_Reg PRM Register Summary 39 3 8 2 4 MPU_PRM Registers Registers 3 8 2 4 1 MPU_PRM Registers Register Summary Table 3 323 MPU_PRM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type Bits RM_RSTST_MPU RW 32 0x0000 005...

Page 569: ...compatibility Read returns 0 R 0x00 3 COREDOMAINWKUP_RST CORE domain wake up reset RW 0x0 Read 0x0 No power domain wake up reset Write 0x0 Status bit unchanged Read 0x1 MPU domain has been reset following a CORE power domain wake up from OFF to ON Write 0x1 Status bit is cleared to 0 2 DOMAINWKUP_RST Power domain wake up reset RW 0x0 Read 0x0 No power domain wake up reset Write 0x0 Status bit unch...

Page 570: ...vent 6 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 5 EN_DSS DSS domain dependency RW 0x1 0x0 MPU domain is independent of DSS domain wake up event 0x1 MPU domain is woken up upon DSS domain wake up event 4 3 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 2 EN_IVA2 IVA2 domain dependency RW 0x1 0x0 MPU domain is independent of IVA2 domain wake up event 0x1 MPU d...

Page 571: ...OFF load mode setting RW 0x2 0x0 Load on update of PM_EVGENOFFTIM_MPU 0x1 Reserved 0x2 Load on MPU standby signal assertion 0x3 Auto load 2 1 ONLOADMODE ON load mode setting RW 0x1 0x0 Load on update of PM_EVGENONTIM_MPU 0x1 Load on MPU standby signal de assertion 0x2 Reserved 0x3 Auto load 0 ENABLE Event generator control RW 0x0 0x0 Disable event generator 0x1 Enable event generator Table 3 329 R...

Page 572: ...U_PRM Registers Register Summary 5 MPU_PRM Registers 6 Table 3 332 PM_EVGENOFFTIM_MPU Address Offset 0x0000 00DC Physical Address 0x4830 69DC Instance MPU_PRM Description This register sets the OFF count duration of the event generator number of system clock cycles Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFTIMEVAL Bits Field Name Description T...

Page 573: ...r future compatibility Read returns 0 R 0x00 8 L2CACHERETSTATE L2 Cache memory state when domain is RETENTION RW 0x1 0x0 L2 Cache memory is OFF when domain is in RETENTION state 0x1 L2 Cache memory is retained when domain is in RETENTION state 7 4 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 3 MEMORYCHANGE Memory change control in ON state RW 0x0 0x0 Disable memory change 0x1 En...

Page 574: ...0x0 0x0 No transition 0x1 MPU power domain transition is in progress 19 8 RESERVED Read returns 0 R 0x000 7 6 L2CACHESTATEST L2 Cache memory state status R 0x3 0x0 L2 Cache memory is OFF 0x1 L2 Cache memory is in RETENTION 0x2 Reserved 0x3 L2 Cache memory is ON 5 3 RESERVED Read returns 0 R 0x0 2 LOGICL1CACHESTATEST Logic and L1 Cache state status R 0x1 0x0 MPU domain logic and L1 Cache is OFF 0x1...

Page 575: ...usly in RETENTION 0x2 Reserved 0x3 L2 Cache memory was previously ON 5 3 RESERVED Read returns 0 R 0x0 2 LASTLOGICL1CACHESTATE Last logic and L1 Cache state entered RW 0x0 ENTERED 0x0 MPU domain logic and L1 Cache was previously OFF 0x1 MPU domain logic and L1 Cache was previously ON 1 0 LASTPOWERSTATEENTERED Last power state entered RW 0x0 0x0 MPU domain was previously OFF 0x1 MPU domain was prev...

Page 576: ...sical Address 0x4830 6A58 Instance CORE_PRM Description This register logs the different reset sources of the CORE domain Each bit is set upon release of the domain reset signal Must be cleared by software Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED GLOBALCOLD_RST DOMAINWKUP_RST GLOBALWARM_RST Bits Field Name Description Type Reset 31 3 RE...

Page 577: ...CSPI2 EN_MCSPI1 EN_MCBSP5 EN_MCBSP1 EN_HSOTGUSB Bits Field Name Description Type Reset 31 RESERVED Write 1 s for future compatibility Read returns 1 RW 0x1 30 EN_MMC3 MMC SDIO 3 wake up control RW 0x1 0x0 MMC 3 wake up is disabled 0x1 MMC 3 wake up event is enabled 29 26 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 25 EN_MMC2 MMC SDIO 2 wake up control RW 0x1 0x0 MMC 2 wake up i...

Page 578: ...1 GPTIMER 11 wake up event is enabled 11 EN_GPT10 GPTIMER 10 wake up control RW 0x1 0x0 GPTIMER 10 wake up is disabled 0x1 GPTIMER 10 wake up event is enabled 10 EN_MCBSP5 McBSP 5 wake up control RW 0x1 0x0 McBSP 5 wake up is disabled 0x1 McBSP 5 wake up event is enabled 9 EN_MCBSP1 McBSP 1 wake up control RW 0x1 0x0 McBSP 1 wake up is disabled 0x1 McBSP 1 wake up event is enabled 8 5 RESERVED Wri...

Page 579: ...ot attached to the MPU wake up events group 0x1 MMC 2 is attached to the MPU wake up events group 24 GRPSEL_MMC1 Select the MMC 1 in the MPU wake up events group RW 0x1 0x0 MMC 1 is not attached to the MPU wake up events group 0x1 MMC 1 is attached to the MPU wake up events group 23 22 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 21 GRPSEL_MCSPI4 Select the McSPI 4 in the MPU wa...

Page 580: ...ct the GPTIMER 11 in the MPU wake up events RW 0x1 group 0x0 GPTIMER 11 is not attached to the MPU wake up events group 0x1 GPTIMER 11 is attached to the MPU wake up events group 11 GRPSEL_GPT10 Select the GPTIMER 10 in the MPU wake up events RW 0x1 group 0x0 GPTIMER 10 is not attached to the MPU wake up events group 0x1 GPTIMER 10 is attached to the MPU wake up events group 10 GRPSEL_MCBSP5 Selec...

Page 581: ...lect the MMC 3 in the IVA2 wake up events group RW 0x1 0x0 MMC 3 is not attached to the IVA2 wake up events group 0x1 MMC 3 is attached to the IVA2 wake up events group 29 26 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 25 GRPSEL_MMC2 Select the MMC 2 in the IVA2 wake up events group RW 0x1 0x0 MMC 2 is not attached to the IVA2 wake up events group 0x1 MMC 2 is attached to the I...

Page 582: ... 0x1 0x0 UART 2 is not attached to the IVA2 wake up events group 0x1 UART 2 is attached to the IVA2 wake up events group 13 GRPSEL_UART1 Select the UART 1 in the IVA2 wake up events group RW 0x1 0x0 UART 1 is not attached to the IVA2 wake up events group 0x1 UART 1 is attached to the IVA2 wake up events group 12 GRPSEL_GPT11 Select the GPTIMER 11 in the IVA2 wake up events RW 0x1 group 0x0 GPTIMER...

Page 583: ...4 3 2 1 0 RESERVED RESERVED RESERVED ST_I2C3 ST_I2C2 ST_I2C1 ST_MMC3 ST_MMC2 ST_MMC1 ST_GPT11 ST_GPT10 ST_UART2 ST_UART1 RESERVED RESERVED ST_MCSPI4 ST_MCSPI3 ST_MCSPI2 ST_MCSPI1 ST_MCBSP5 ST_MCBSP1 ST_HSOTGUSB Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 30 ST_MMC3 MMC 3 Wake up status RW 0x0 Read 0x0 MMC 3 wake up did not occur or was...

Page 584: ..._I2C3 I2C 3 Wake up status RW 0x0 Read 0x0 I2C 3 wake up did not occur or was masked Write 0x0 Status bit unchanged Read 0x1 I2C 3 wake up occurred Write 0x1 Status bit is cleared to 0 16 ST_I2C2 I2C 2 Wake up status RW 0x0 Read 0x0 I2C 2 wake up did not occur or was masked Write 0x0 Status bit unchanged Read 0x1 I2C 2 wake up occurred Write 0x1 Status bit is cleared to 0 15 ST_I2C1 I2C 1 Wake up ...

Page 585: ...ite 0x1 Status bit is cleared to 0 8 5 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 4 ST_HSOTGUSB HS OTG USB Wake up status RW 0x0 Read 0x0 HS OTG USB wake up did not occur or was masked Write 0x0 Status bit unchanged Read 0x1 HS OTG USB wake up occurred Write 0x1 Status bit is cleared to 0 3 0 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 Table 3 350 Register ...

Page 586: ... 2 1 0 RESERVED RESERVED RESERVED POWERSTATE MEM2ONSTATE MEM1ONSTATE MEM2RETSTATE MEM1RETSTATE LOGICRETSTATE MEMORYCHANGE SAVEANDRESTORE Bits Field Name Description Type Reset 31 20 RESERVED Write 0s for future compatibility Read returns 0 R 0x000 19 18 MEM2ONSTATE Memory block 2 state when domain is ON RW 0x3 0x0 Memory block 2 is OFF when domain is ON 0x1 Memory block 2 is in RETENTION when doma...

Page 587: ...ogic is OFF when domain is in RETENTION state 0x1 Logic is retained when domain is in RETENTION state 1 0 POWERSTATE Power state control RW 0x3 0x0 OFF state 0x1 RETENTION state 0x2 Reserved 0x3 ON state Table 3 354 Register Call Summary for Register PM_PWSTCTRL_CORE PRCM Functional Description Device Power Domains 0 1 2 CORE Power Domain Clock Controls 3 USBHOST USBTLL Save and Restore Management...

Page 588: ...EM2STATEST Memory block 2 state status R 0x3 0x0 Memory is OFF 0x1 Memory is in RETENTION 0x2 Reserved 0x3 Memory is ON 5 4 MEM1STATEST Memory block 1 state status R 0x3 0x0 Memory is OFF 0x1 Memory is in RETENTION 0x2 Reserved 0x3 Memory is ON 3 RESERVED Read returns 0 R 0x0 2 LOGICSTATEST Logic state status R 0x1 0x0 CORE domain logic is OFF 0x1 CORE domain logic is ON 1 0 POWERSTATEST Current p...

Page 589: ...0x3 Memory was previously ON 5 4 LASTMEM1STATEENTERED Last Memory block 1 state entered RW 0x0 0x0 Memory was previously OFF 0x1 Memory was previously in RETENTION 0x2 Reserved 0x3 Memory was previously ON 3 RESERVED Read returns 0 R 0x0 2 LASTLOGICSTATEENTERED Last logic state entered RW 0x0 0x0 CORE domain logic was previously OFF 0x1 CORE domain logic was previously ON 1 0 LASTPOWERSTATEENTERED...

Page 590: ...del PM_WKEN_ domain_name Wake Up Enable Register 0 PRCM Register Manual CORE_PRM Register Summary 1 Table 3 361 PM_IVA2GRPSEL3_CORE Address Offset 0x0000 00F4 Physical Address 0x4830 6AF4 Instance CORE_PRM Description This register allows selecting the group of modules that wake up the IVA2 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESER...

Page 591: ...group RW 0x1 0x0 USB TLL is not attached to the MPU wake up events group 0x1 USB TLL is attached to the MPU wake up events group 1 0 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 Table 3 364 Register Call Summary for Register PM_MPUGRPSEL3_CORE PRCM Functional Description Device Wake Up Events 0 PRCM Basic Programming Model PM_ processor_name GRPSEL_ domain_name Processor Group S...

Page 592: ...omain wake up from OFF to ON Write 0x1 Status bit is cleared to 0 2 DOMAINWKUP_RST Power domain wake up reset RW 0x0 Read 0x0 SGX domain is not reset Write 0x0 Status bit unchanged Read 0x1 SGX domain has been reset following a SGX domain wake up Write 0x1 Status bit is cleared to 0 1 GLOBALWARM_RST Global warm reset RW 0x0 Read 0x0 No global warm reset Write 0x0 Status bit unchanged Read 0x1 SGX ...

Page 593: ... 0 R 0x0 2 EN_IVA2 IVA2 domain dependency RW 0x1 0x0 SGX domain is independent of IVA2 domain wake up event 0x1 SGX domain is woken up upon IVA2 domain wake up event 1 EN_MPU MPU domain dependency RW 0x1 0x0 SGX domain is independent of MPU domain wake up 0x1 SGX domain is woken up upon MPU domain wake up 0 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 Table 3 369 Register Call S...

Page 594: ...NTION state 1 0 POWERSTATE Power state control RW 0x3 0x0 OFF state 0x1 RETENTION state 0x2 Reserved 0x3 ON state Table 3 371 Register Call Summary for Register PM_PWSTCTRL_SGX PRCM Basic Programming Model PM_PWSTCTRL_ domain_name Power State Control Register 0 PRCM Register Manual SGX_PRM Register Summary 1 Table 3 372 PM_PWSTST_SGX Address Offset 0x0000 00E4 Physical Address 0x4830 6BE4 Instance...

Page 595: ...tered during the last sleep transition Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LASTPOWERSTATEENTERED Bits Field Name Description Type Reset 31 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 1 0 LASTPOWERSTATEENTERED Last power state entered RW 0x0 0x0 SGX domain was previously OFF 0x1 SGX domain was previously...

Page 596: ...is disabled RW 1 0x0 I O wake up daisy chain is disabled 0x1 I O wake up daisy chain event is enabled 15 10 RESERVED Write 0s for future compatibility Read returns 0 R 0x000000 9 RESERVED Reserved for non GP devices RW 0x1 8 EN_IO IO pad wake up control RW 0x1 0x0 IO pad wakeup is disabled 0x1 IO pad wake up event is enabled 7 EN_SR2 SmartRefex 2 wake up control RW 0x1 0x0 SmartReflex 2 wakeup is ...

Page 597: ...D RESERVED GRPSEL_IO GRPSEL_SR2 GRPSEL_SR1 GRPSEL_GPT1 GRPSEL_GPIO1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GRPSEL_IO GRPSEL_GPT1 GRPSEL_GPIO1 Bits Field Name Description Type Reset 31 10 RESERVED Write 0s for future compatibility Read returns 0 R 0x000000 9 RESERVED Reserved for non GP devices RW 0...

Page 598: ...ter Summary 2 Table 3 381 PM_IVA2GRPSEL_WKUP Address Offset 0x0000 00A8 Physical Address 0x4830 6CA8 Instance WKUP_PRM Description This register allows selecting the group of modules that wake up the IVA2 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED GRPSEL_IO GRPSEL_SR2 GRPSEL_SR1 GRPSEL_GPT1 GRPSEL_GPIO1...

Page 599: ...t Sources 0 PM_ processor_name GRPSEL_ domain_name Processor Group Selection Register 1 PRCM Register Manual WKUP_PRM Register Summary 2 Table 3 383 PM_WKST_WKUP Address Offset 0x0000 00B0 Physical Address 0x4830 6CB0 Instance WKUP_PRM Description This register logs module wake up events Must be cleared by software If it is not cleared it prevents further domain transition Type RW 31 30 29 28 27 2...

Page 600: ...bit unchanged Read 0x1 GPIO 1 wakeup occurred Write 0x1 Status bit is cleared to 0 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 1 RESERVED Reserved for non GP devices RW 0x0 0 ST_GPT1 GPTIMER 1 wake up status RW 0x0 Read 0x0 GPTIMER 1 wakeup did not occur or was masked Write 0x0 Status bit unchanged Read 0x1 GPTIMER 1 wakeup occurred Write 0x1 Status bit is cleared to 0 Table ...

Page 601: ... enums Reserved RW 0x4 0x0 OSC_SYS_CLK is 12 MHz 0x1 OSC_SYS_CLK is 13 MHz 0x2 OSC_SYS_CLK is 19 2 MHz 0x3 OSC_SYS_CLK is 26 MHz 0x4 OSC_SYS_CLK is 38 4 MHz 0x5 OSC_SYS_CLK is 16 8 MHz Table 3 387 Register Call Summary for Register PRM_CLKSEL PRCM Functional Description External Clock Inputs 0 PRCM Register Manual Clock_Control_Reg_PRM Register Summary 1 Table 3 388 PRM_CLKOUT_CTRL Address Offset ...

Page 602: ...ter Width Address Offset Physical Address Reset Type Bits RM_RSTST_DSS RW 32 0x0000 0058 0x4830 6E58 C PM_WKEN_DSS RW 32 0x0000 00A0 0x4830 6EA0 W PM_WKDEP_DSS RW 32 0x0000 00C8 0x4830 6EC8 W PM_PWSTCTRL_DSS RW 32 0x0000 00E0 0x4830 6EE0 W PM_PWSTST_DSS R 32 0x0000 00E4 0x4830 6EE4 C PM_PREPWSTST_DSS RW 32 0x0000 00E8 0x4830 6EE8 C 3 8 2 9 2 DSS_PRM Registers Table 3 391 RM_RSTST_DSS Address Offse...

Page 603: ... is cleared to 0 0 GLOBALCOLD_RST Global cold reset RW 0x1 Read 0x0 No global cold reset Write 0x0 Status bit unchanged Read 0x1 DISPLAY domain has been reset upon a global cold reset Write 0x1 Status bit is cleared to 0 Table 3 392 Register Call Summary for Register RM_RSTST_DSS PRCM Basic Programming Model RM_RSTST_ domain_name Reset Status Register 0 PRCM Register Manual DSS_PRM Register Summar...

Page 604: ...ncy RW 0x1 0x0 DSS domain is independent of WKUP domain wake up event 0x1 DSS domain is woken up upon WKUP domain wake up event 3 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 2 EN_IVA2 IVA2 domain dependency RW 0x1 0x0 DSS domain is independent of IVA2 domain wake up event 0x1 DSS domain is woken up upon IVA2 domain wake up event 1 EN_MPU MPU domain dependency RW 0x1 0x0 DSS dom...

Page 605: ...n RETENTION state 7 3 RESERVED Write 0s for future compatibility Read returns 0 R 0x00 2 LOGICRETSTATE Logic state when RETENTION R 0x1 0x1 Logic is always retained when domain is in RETENTION state 1 0 POWERSTATE Power state control RW 0x3 0x0 OFF state 0x1 RETENTION state 0x2 Reserved 0x3 ON state Table 3 398 Register Call Summary for Register PM_PWSTCTRL_DSS PRCM Basic Programming Model PM_PWST...

Page 606: ...ress 0x4830 6EE8 Instance DSS_PRM Description This register provides a status on the DSS domain previous power state It indicates the state entered during the last sleep transition Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LASTPOWERSTATEENTERED Bits Field Name Description Type Reset 31 2 RESERVED Write 0s for future compatibility Read re...

Page 607: ...st be cleared by software Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED GLOBALCOLD_RST DOMAINWKUP_RST GLOBALWARM_RST COREDOMAINWKUP_RST Bits Field Name Description Type Reset 31 4 RESERVED Write 0s for future compatibility Read returns 0 R 0x0000000 3 COREDOMAINWKUP_RST CORE domain wake up reset RW 0x0 Read 0x0 No power domain wake up reset ...

Page 608: ...p of the CAM domain upon another domain wakeup Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EN_IVA2 EN_MPU EN_WKUP RESERVED RESERVED Bits Field Name Description Type Reset 31 5 RESERVED Write 0s for future compatibility Read returns 0 R 0x0000000 4 EN_WKUP WAKEUP domain dependency RW 0x1 0x0 CAM domain is independent of WKUP domain wake up ...

Page 609: ...patibility Read returns 0 R 0x0000 17 16 MEMONSTATE Memory state when ON R 0x3 0x3 Memory is always ON when domain is ON 15 9 RESERVED Write 0s for future compatibility Read returns 0 R 0x00 8 MEMRETSTATE Memory state when RETENTION R 0x1 0x1 Memory is always retained when domain is in RETENTION state 7 3 RESERVED Write 0s for future compatibility Read returns 0 R 0x00 2 LOGICRETSTATE Logic state ...

Page 610: ...ns 0 R 0x00000 1 0 POWERSTATEST Current power state status R 0x3 0x0 Power domain is OFF 0x1 Power domain is in RETENTION 0x2 Power domain is INACTIVE 0x3 Power domain is ON Table 3 411 Register Call Summary for Register PM_PWSTST_CAM PRCM Basic Programming Model PM_PWSTST_ domain_name Power State Status Register 0 PRCM Register Manual CAM_PRM Registers 1 Table 3 412 PM_PREPWSTST_CAM Address Offse...

Page 611: ...0x4830 7058 C PM_WKEN_PER RW 32 0x0000 00A0 0x4830 70A0 W PM_MPUGRPSEL_PER RW 32 0x0000 00A4 0x4830 70A4 W PM_IVA2GRPSEL_PER RW 32 0x0000 00A8 0x4830 70A8 W PM_WKST_PER RW 32 0x0000 00B0 0x4830 70B0 C PM_WKDEP_PER RW 32 0x0000 00C8 0x4830 70C8 W PM_PWSTCTRL_PER RW 32 0x0000 00E0 0x4830 70E0 W PM_PWSTST_PER R 32 0x0000 00E4 0x4830 70E4 C PM_PREPWSTST_PER RW 32 0x0000 00E8 0x4830 70E8 C 3 8 2 11 2 P...

Page 612: ...d reset Write 0x0 Status bit unchanged Read 0x1 PER domain has been reset upon a global cold reset Write 0x1 Status bit is cleared to 0 Table 3 416 Register Call Summary for Register RM_RSTST_PER PRCM Basic Programming Model RM_RSTST_ domain_name Reset Status Register 0 PRCM Register Manual PER_PRM Register Summary 1 Table 3 417 PM_WKEN_PER Address Offset 0x0000 00A0 Physical Address 0x4830 70A0 I...

Page 613: ...ake up control RW 0x1 0x0 GPTIMER 8 wake up is disabled 0x1 GPTIMER 8 wake up event is enabled 8 EN_GPT7 GPTIMER 7 wake up control RW 0x1 0x0 GPTIMER 7 wake up is disabled 0x1 GPTIMER 7 wake up event is enabled 7 EN_GPT6 GPTIMER 6 wake up control RW 0x1 0x0 GPTIMER 6 wake up is disabled 0x1 GPTIMER 6 wake up event is enabled 6 EN_GPT5 GPTIMER 5 wake up control RW 0x1 0x0 GPTIMER 5 wake up is disab...

Page 614: ...IO3 GRPSEL_GPIO2 GRPSEL_UART4 GRPSEL_UART3 GRPSEL_MCBSP4 GRPSEL_MCBSP3 GRPSEL_MCBSP2 Bits Field Name Description Type Reset 31 19 RESERVED Write 0s for future compatibility Read returns 0 R 0x0000 18 GRPSEL_UART4 Select the UART 4 in the MPU wake up events group RW 0x1 0x0 UART 4 is not attached to the MPU wake up events group 0x1 UART 4 is attached to the MPU wake up events group 17 GRPSEL_GPIO6 ...

Page 615: ...oup 8 GRPSEL_GPT7 Select the GPTIMER 7 in the MPU wake up events group RW 0x1 0x0 GPTIMER 7 is not attached to the MPU wake up events group 0x1 GPTIMER 7 is attached to the MPU wake up events group 7 GRPSEL_GPT6 Select the GPTIMER 6 in the MPU wake up events group RW 0x1 0x0 GPTIMER 6 is not attached to the MPU wake up events group 0x1 GPTIMER 6 is attached to the MPU wake up events group 6 GRPSEL...

Page 616: ...ble 3 421 PM_IVA2GRPSEL_PER Address Offset 0x0000 00A8 Physical Address 0x4830 70A8 Instance PER_PRM Description This register allows selecting the group of modules that wake up the IVA2 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED GRPSEL_GPT9 GRPSEL_GPT8 GRPSEL_GPT7 GRPSEL_GPT6 GRPSEL_GPT5 GRPSEL_GPT4 GRPSEL_GPT3 GRPSEL_GPT2 GRPSE...

Page 617: ...PSEL_GPT9 Select the GPTIMER 9 in the IVA2 wake up events group RW 0x1 0x0 GPTIMER 9 is not attached to the IVA2 wake up events group 0x1 GPTIMER 9 is attached to the IVA2 wake up events group 9 GRPSEL_GPT8 Select the GPTIMER 8 in the IVA2 wake up events group RW 0x1 0x0 GPTIMER 8 is not attached to the IVA2 wake up events group 0x1 GPTIMER 8 is attached to the IVA2 wake up events group 8 GRPSEL_G...

Page 618: ...elect the McBSP 2 in the IVA2 wake up events group RW 0x1 0x0 McBSP 2 is not attached to the IVA2 wake up events group 0x1 McBSP 2 is attached to the IVA2 wake up events group Table 3 422 Register Call Summary for Register PM_IVA2GRPSEL_PER PRCM Functional Description Device Wake Up Events 0 PRCM Basic Programming Model PM_ processor_name GRPSEL_ domain_name Processor Group Selection Register 1 PR...

Page 619: ...hanged Read 0x1 GPIO 4 wake up occurred Write 0x1 Status bit is cleared to 0 14 ST_GPIO3 GPIO 3 Wake up status RW 0x0 Read 0x0 GPIO 3 wake up did not occur or was masked Write 0x0 Status bit unchanged Read 0x1 GPIO 3 wake up occurred Write 0x1 Status bit is cleared to 0 13 ST_GPIO2 GPIO 2 Wake up status RW 0x0 Read 0x0 GPIO 2 wake up did not occur or was masked Write 0x0 Status bit unchanged Read ...

Page 620: ...hanged Read 0x1 GPTIMER 5 wake up occurred Write 0x1 Status bit is cleared to 0 5 ST_GPT4 GPTIMER 4 Wake up status RW 0x0 Read 0x0 GPTIMER 4 wake up did not occur or was masked Write 0x0 Status bit unchanged Read 0x1 GPTIMER 4 wake up occurred Write 0x1 Status bit is cleared to 0 4 ST_GPT3 GPTIMER 3 Wake up status RW 0x0 Read 0x0 GPTIMER 3 wake up did not occur or was masked Write 0x0 Status bit u...

Page 621: ...or disabling the wake up of the PER domain upon another domain wakeup events Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EN_IVA2 EN_MPU EN_CORE EN_WKUP RESERVED Bits Field Name Description Type Reset 31 5 RESERVED Write 0s for future compatibility Read returns 0 R 0x0000000 4 EN_WKUP WAKEUP domain dependency RW 0x1 0x0 PER domain is indepe...

Page 622: ... 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED POWERSTATE MEMONSTATE MEMRETSTATE LOGICRETSTATE Bits Field Name Description Type Reset 31 18 RESERVED Write 0s for future compatibility Read returns 0 R 0x0000 17 16 MEMONSTATE Memory state when ON R 0x3 0x3 Memory is always ON when domain is ON 15 9 RESERVED Write 0s for future compatibility Read returns 0 R 0x00 8 MEMRETSTATE Memory state when RETE...

Page 623: ... RESERVED Write 0s for future compatibility Read returns 0 R 0x000 20 INTRANSITION Domain transition status R 0x0 0x0 No transition 0x1 PERIPHERAL power domain transition is in progress 19 3 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000 2 LOGICSTATEST Logic state status R 0x1 0x0 PER domain logic is OFF 0x1 PER domain logic is ON 1 0 POWERSTATEST Current power state status R ...

Page 624: ...logic was previously ON 1 0 LASTPOWERSTATEENTERED Last power state entered RW 0x0 0x0 PER domain was previously OFF 0x1 PER domain was previously in RETENTION 0x2 PER domain was previously INACTIVE 0x3 PER domain was previously ON Table 3 432 Register Call Summary for Register PM_PREPWSTST_PER PRCM Basic Programming Model PM_PREPWSTST_ domain_name Previous Power State Status Register 0 PRCM Regist...

Page 625: ...e 0x0 Status bit unchanged Read 0x1 EMULATION domain has been reset following an EMULATION power domain wake up Write 0x1 Status bit is cleared to 0 1 GLOBALWARM_RST Global warm reset RW 0x0 Read 0x0 No global warm reset Write 0x0 Status bit unchanged Read 0x1 MPU domain has been reset upon a global warm reset Write 0x1 Status bit is cleared to 0 0 GLOBALCOLD_RST Global cold reset RW 0x1 Read 0x0 ...

Page 626: ...is ON Table 3 437 Register Call Summary for Register PM_PWSTST_EMU PRCM Basic Programming Model PM_PWSTST_ domain_name Power State Status Register 0 PRCM Register Manual EMU_PRM Register Summary 1 3 8 2 13 Global_Reg_PRM Registers 3 8 2 13 1 Global_Reg_PRM Register Summary Table 3 438 Global_Reg_PRM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type Bits ...

Page 627: ...2_VSTEPMIN RW 32 0x0000 00D4 0x4830 72D4 W PRM_VP2_VSTEPMAX RW 32 0x0000 00D8 0x4830 72D8 W PRM_VP2_VLIMITTO RW 32 0x0000 00DC 0x4830 72DC W PRM_VP2_VOLTAGE R 32 0x0000 00E0 0x4830 72E0 W PRM_VP2_STATUS R 32 0x0000 00E4 0x4830 72E4 W PRM_LDO_ABB_SETUP RW 32 0x0000 00F0 0x4830 72F0 W PRM_LDO_ABB_CTRL RW 32 0x0000 00F4 0x4830 72F4 W 3 8 2 13 2 Global_Reg_PRM Registers Table 3 439 PRM_VC_SMPS_SA Addr...

Page 628: ...value for RW 0x00 the second VDD channel VDD2 15 8 RESERVED Write 0s for future compatibility Read is undefined R 0x00 7 0 VOLRA0 Set the voltage configuration register address value for RW 0x00 the first VDD channel VDD1 Table 3 442 Register Call Summary for Register PRM_VC_SMPS_VOL_RA PRCM Basic Programming Model Voltage Controller Registers 0 PRM_VC_BYPASS_VAL Voltage Controller Bypass Command ...

Page 629: ...fset 0x0000 002C Physical Address 0x4830 722C Instance Global_Reg_PRM Description This register allows the setting of the ON Retention OFF voltage level values for the first VDD channel Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ON ONLP RET OFF Bits Field Name Description Type Reset 31 24 ON Set the ON voltage level value for the first VDD channel...

Page 630: ...ntroller Registers 2 PRCM Register Manual Global_Reg_PRM Register Summary 3 Table 3 449 PRM_VC_CH_CONF Address Offset 0x0000 0034 Physical Address 0x4830 7234 Instance Global_Reg_PRM Description This register allows the configuration pointers for both VDD channels Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED SA1 SA0 RAV1 RAV0 RAC1 ...

Page 631: ... allows the configuration pointers for both VDD channels Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MCODE SREN HSEN HSMASTER Bits Field Name Description Type Reset 31 6 RESERVED Write 0s for future compatibility Read is undefined R 0x0000000 5 HSMASTER Put the I2C pads in a low power mode in case of light RW 0x0 load 0x0 Disables the I2C ...

Page 632: ...een acknowledged 0x1 The Voltage Controller send the command to the I2C interface 0x1 Pending command is being process 23 16 DATA Data to send to the Power IC device RW 0x00 15 8 REGADDR Set the address of Power IC device register to configure RW 0x00 7 RESERVED Write 0s for future compatibility Read is undefined RW 0x0 6 0 SLAVEADDR Set the I2C slave address value RW 0x00 Table 3 454 Register Cal...

Page 633: ...ming Model RM_RSTCTRL_ domain_name Reset Control Register 2 3 PRCM Register Manual Global_Reg_PRM Register Summary 4 Table 3 457 PRM_RSTTIME Address Offset 0x0000 0054 Physical Address 0x4830 7254 Instance Global_Reg_PRM Description Reset duration control Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RSTTIME2 RSTTIME1 Bits Field Name Descrip...

Page 634: ...ite 0x1 Status bit is cleared to 0 9 ICEPICK_RST IcePick reset event This is a source of warm reset RW 0x0 initiated by the emulation Read 0x0 No IcePick reset Write 0x0 Status bit unchanged Read 0x1 IcePick reset occurred Write 0x1 Status bit is cleared to 0 8 VDD2_VOLTAGE_MANAGER_R VDD2 voltage manager reset event RW 0x0 ST Read 0x0 No VDD2 voltage manager reset Write 0x0 Status bit unchanged Re...

Page 635: ...tatus bit unchanged Read 0x1 Power on reset occurred Write 0x1 Status bit is cleared to 0 Table 3 460 Register Call Summary for Register PRM_RSTST PRCM Functional Description Reset Logging 0 PRCM Reset Logging Mechanism 1 PRCM Basic Programming Model RM_RSTST_ domain_name Reset Status Register 2 3 4 Reset Management 5 PRCM Register Manual Global_Reg_PRM Register Summary 6 Table 3 461 PRM_VOLTCTRL ...

Page 636: ...d an OFF command to the Power RW 0x0 IC 0x0 The OFF command is not send 0x1 The OFF command is automatically send when the voltage domain is in the appropriate standby mode 1 AUTO_RET This bit allows to send a RETENTION command to the RW 0x0 Power IC through the voltage controller I2C interface 0x0 The RETENTION command is not send 0x1 The RETENTION command is automatically send when the voltage d...

Page 637: ...ance Global_Reg_PRM Description This register provides control over the device source clock Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED SYSCLKDIV SYSCLKSEL DPLL4_CLKINP_DIV AUTOEXTCLKMODE Bits Field Name Description Type Reset 31 9 RESERVED Write 0s for future compatibility Read returns 0 R 0x000000 8 DPLL4_CLKINP_DIV Thi...

Page 638: ...mode the system clock is issued from an external square clock source 0x1 Oscillator mode the system clock is issued from an external quartz 0x2 Reserved 0x3 Unknow state not know before release of the power on reset Table 3 466 Register Call Summary for Register PRM_CLKSRC_CTRL PRCM Functional Description External Clock Inputs 0 DPLLs 1 2 3 System Clock Oscillator Control 4 5 PRM Source Clock Cont...

Page 639: ...of cycles of SYS_CLK set in the register bit field Table 3 470 Register Call Summary for Register PRM_VOLTSETUP1 PRCM Functional Description Direct Control With VMODE Signals 0 Device Off Mode Sequences 1 2 Sleep Sequences 3 4 Wake Up Sequences 5 6 PRCM Basic Programming Model PRM_VOLTSETUP Voltage Setup Time Register 7 8 9 10 11 PRCM Use Cases and Tips Initialization Procedure 12 13 PRCM Register...

Page 640: ...lity Read returns 0 R 0x0000 15 0 SETUP_TIME Number of 32kHz clock cycles for the SETUP duration RW 0x0000 Table 3 474 Register Call Summary for Register PRM_CLKSETUP PRCM Functional Description System Clock Oscillator Control 0 PRM Source Clock Controls 1 Device Off Mode Sequences 2 PRCM Basic Programming Model PRM_CLKSETUP Source Clock Setup Register 3 PRM_VOLTOFFSET Voltage Offset Register 4 5 ...

Page 641: ...With VMODE Signals 9 10 PRCM Use Cases and Tips Initialization Procedure 11 PRCM Register Manual Global_Reg_PRM Register Summary 12 Table 3 477 PRM_VOLTSETUP2 Address Offset 0x0000 00A0 Physical Address 0x4830 72A0 Instance Global_Reg_PRM Description This register allows setting the overall setup time of VDD1 and VDD2 regulators This register is used when exiting OFF mode and when the Power IC man...

Page 642: ...ty of the Voltage RW 0x0 Controller State Machine 0x0 Timeout is disabled Loop will wait indefinitely 0x1 Timeout will occur when TIMEOUT cycles have elapsed 2 INITVDD Initializes the voltage in the Voltage Processor RW 0x0 0x0 Reset the initialization bit 0x1 The positive edge of InitVdd triggers a write of the value in the InitVoltage into the Voltage Processor 1 FORCEUPDATE Forces an update of ...

Page 643: ...1 PRCM Register Manual Global_Reg_PRM Register Summary 2 Table 3 483 PRM_VP1_VSTEPMAX Address Offset 0x0000 00B8 Physical Address 0x4830 72B8 Instance Global_Reg_PRM Description This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor 1 VDD1 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SMPSW...

Page 644: ...rs 0 PRM_VP_VLIMITTO Voltage Processor Voltage Limit and Time Out 1 PRCM Register Manual Global_Reg_PRM Register Summary 2 Table 3 487 PRM_VP1_VOLTAGE Address Offset 0x0000 00C0 Physical Address 0x4830 72C0 Instance Global_Reg_PRM Description This register indicates the current value of the SMPS voltage for the Voltage Processor 1 VDD1 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1...

Page 645: ...Status Register 1 PRCM Register Manual Global_Reg_PRM Register Summary 2 Table 3 491 PRM_VP2_CONFIG Address Offset 0x0000 00D0 Physical Address 0x4830 72D0 Instance Global_Reg_PRM Description This register allows the configuration of the Voltage Processor 2 VDD2 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERROROFFSET ERRORGAIN INITVOLTAGE RESERVED ...

Page 646: ...nfiguration Register 1 PRCM Use Cases and Tips Device SmartReflex Initialization 2 Switch VDD2 OPPs 3 4 5 6 PRCM Register Manual Global_Reg_PRM Register Summary 7 Table 3 493 PRM_VP2_VSTEPMIN Address Offset 0x0000 00D4 Physical Address 0x4830 72D4 Instance Global_Reg_PRM Description This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor 2 VDD2 Ty...

Page 647: ...al Global_Reg_PRM Register Summary 1 Table 3 497 PRM_VP2_VLIMITTO Address Offset 0x0000 00DC Physical Address 0x4830 72DC Instance Global_Reg_PRM Description This register allows the configuration of the voltage limits and timeout values of the Voltage Processor 2 VDD2 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VDDMAX VDDMIN TIMEOUT Bits Field Nam...

Page 648: ...3 501 PRM_VP2_STATUS Address Offset 0x0000 00E4 Physical Address 0x4830 72E4 Instance Global_Reg_PRM Description This register reflects the idle state of the Voltage Processor 2 VDD2 This register is read only and automatically updated Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VPINIDLE Bits Field Name Description Type Reset 31 1 RESERVED ...

Page 649: ...ity Read is undefined R 0x0 4 3 SR2_STATUS Indicates the current mode of operation of the ABB LDO R 0x0 0x0 The ABB LDO is in bypass mode 0x1 Reserved 0x2 The ABB LDO is in FBB mode 0x3 Reserved 2 OPP_CHANGE The ABB LDO controller samples OPP_SEL bits field and RW 0x0 ACTIVE_RRB_SEL and ACTIVE_FBB_SEL bit fields upon rising edge of this bit It is automatically cleared by the PRCM HW upon completio...

Page 650: ...G 0x0 ABB LDO will operate in bypass mode 0x1 ABB LDO will operate in FBB mode 1 RESERVED Write 0s for future compatibility Read is undefined R 0X0 0 SR2EN Enables the ABB LDO RW 0x0 0x0 ABB LDO is in bypass mode 0x1 ABB LDO will operate in FBB mode or bypass mode accordingly to the other SW settings and HW events Table 3 506 Register Call Summary for Register PRM_LDO_ABB_CTRL PRCM Functional Desc...

Page 651: ...wake up from OFF to ON Write 0x1 Status bit is cleared to 0 2 DOMAINWKUP_RST Power domain wake up reset RW 0x0 Read 0x0 No power domain wake up reset Write 0x0 Status bit unchanged Read 0x1 NEON domain has been reset following a NEON power domain wake up Write 0x1 Status bit is cleared to 0 1 GLOBALWARM_RST Global warm reset RW 0x0 Read 0x0 No global warm reset Write 0x0 Status bit unchanged Read ...

Page 652: ...able 3 511 Register Call Summary for Register PM_WKDEP_NEON PRCM Functional Description Device Wake Up Events 0 PRCM Basic Programming Model PM_WKDEP_ domain_name Wake Up Dependency Register 1 PRCM Register Manual NEON_PRM Register Summary 2 Table 3 512 PM_PWSTCTRL_NEON Address Offset 0x0000 00E0 Physical Address 0x4830 73E0 Instance NEON_PRM Description This register controls the NEON domain powe...

Page 653: ...1 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED INTRANSITION POWERSTATEST Bits Field Name Description Type Reset 31 21 RESERVED Write 0s for future compatibility Read returns 0 R 0x000 20 INTRANSITION Domain transition status R 0x0 0x0 No transition 0x1 NEON power domain transition is in progress 19 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000 1 0 POWERSTATEST Current power sta...

Page 654: ...r Call Summary for Register PM_PREPWSTST_NEON PRCM Basic Programming Model PM_PREPWSTST_ domain_name Previous Power State Status Register 0 PRCM Register Manual NEON_PRM Register Summary 1 3 8 2 15 USBHOST_PRM Registers 3 8 2 15 1 USBHOST_PRM Register Summary Table 3 518 USBHOST_PRM Register Summary Register Name Type Register Width Address Offset Physical Address Reset Type Bits RM_RSTST_USBHOST ...

Page 655: ...e up from OFF to ON Write 0x1 Status bit is cleared to 0 2 DOMAINWKUP_RST Power domain wake up reset RW 0x0 Read 0x0 No power domain wake up reset Write 0x0 Status bit unchanged Read 0x1 USB HOST domain has been reset following an USB HOST power domain wake up Write 0x1 Status bit is cleared to 0 1 GLOBALWARM_RST Global warm reset RW 0x0 Read 0x0 No global warm reset Write 0x0 Status bit unchanged...

Page 656: ...s 0 PRCM Basic Programming Model PM_WKEN_ domain_name Wake Up Enable Register 1 PRCM Register Manual USBHOST_PRM Register Summary 2 Table 3 523 PM_MPUGRPSEL_USBHOST Address Offset 0x0000 00A4 Physical Address 0x4830 74A4 Instance USBHOST_PRM Description This register allows selecting the group of modules that wake up the MPU Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 657: ...PSEL_USBHOST Select the USBHOST in the IVA2 wake up events group RW 0x1 0x0 USBHOST is not attached to the IVA2 wake up events group 0x1 USBHOST is attached to the IVA2 wake up events group Table 3 526 Register Call Summary for Register PM_IVA2GRPSEL_USBHOST PRCM Basic Programming Model PM_ processor_name GRPSEL_ domain_name Processor Group Selection Register 0 PRCM Register Manual USBHOST_PRM Reg...

Page 658: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EN_IVA2 EN_MPU EN_CORE EN_WKUP RESERVED Bits Field Name Description Type Reset 31 5 RESERVED Write 0s for future compatibility Read returns 0 R 0x0000000 4 EN_WKUP WAKEUP domain dependency RW 0x1 0x0 USB HOST domain is independent of WKUP domain wake up event 0x1 USB HOST domain is woken up upon WKUP domain wake up event 3 RESERVED Write 0s for future co...

Page 659: ... returns 0 R 0x0000 17 16 MEMONSTATE Memory state when ON R 0x3 0x3 Memory is always ON when domain is ON 15 9 RESERVED Write 0s for future compatibility Read returns 0 R 0x00 8 MEMRETSTATE Memory state when RETENTION R 0x1 0x1 Memory is always retained when domain is in RETENTION state 7 5 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 4 SAVEANDRESTORE Save And Restore mechanism ...

Page 660: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED INTRANSITION POWERSTATEST Bits Field Name Description Type Reset 31 21 RESERVED Write 0s for future compatibility Read returns 0 R 0x000 20 INTRANSITION Domain transition status R 0x0 0x0 No transition 0x1 USB HOST power domain transition is in progress 19 2 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000 1 0 POWERST...

Page 661: ...domain was previously in RETENTION 0x2 USB HOST domain was previously INACTIVE 0x3 USB HOST domain was previously ON Table 3 536 Register Call Summary for Register PM_PREPWSTST_USBHOST PRCM Register Manual USBHOST_PRM Register Summary 0 3 8 3 SR Registers 3 8 3 1 SR Instance Summary Table 3 537 SR Instance Summary Module Name Base address hex Size SR1 0x480C 9000 4K bytes SR2 0x480C B000 4K bytes ...

Page 662: ...ters Table 3 539 SRCONFIG Address Offset 0x0000 0000 Physical Address 0x480C 9000 Instance SR1 0x480C B000 SR2 Description This register contains configuration bits for the sensor core and digital processing Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACCUMDATA SRCLKLENGTH RESERVED SRENABLE SENENABLE SENPENABLE SENNENABLE MINMAXAVGENABLE ERRORGENER...

Page 663: ...ing Model SmartReflex Module Initialization Basic Programming Model 11 12 13 14 15 16 17 18 Changing OPP Using the SmartReflex Module 19 20 21 Changing OPP Using Only the Voltage Processor Module 22 PRCM Use Cases and Tips Device SmartReflex Initialization 23 24 25 26 27 28 29 30 Switch VDD1 OPPs 31 32 33 34 35 36 Switch VDD2 OPPs 37 38 39 40 41 42 PRCM Register Manual SR Register Summary 43 Table...

Page 664: ...M Functional Description SmartReflex Voltage Control 0 1 2 3 4 5 6 PRCM Register Manual SR Register Summary 7 Table 3 543 SENVAL Address Offset 0x0000 0008 Physical Address 0x480C 9008 Instance SR1 0x480C B008 SR2 Description This register gives the sensor value for the sensor core Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SENPVAL SENNVAL Bits Fie...

Page 665: ...Control 0 1 2 3 PRCM Register Manual SR Register Summary 4 Table 3 547 SENMAX Address Offset 0x0000 0010 Physical Address 0x480C 9010 Instance SR1 0x480C B010 SR2 Description This register give the maximum sensor value Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SENPMAX SENNMAX Bits Field Name Description Type Reset 31 16 SENPMAX Maximum Value of Se...

Page 666: ...nstance SR1 0x480C B018 SR2 Description This register gives the weighing factor in the average computation Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SENPAVGWEIGHT SENNAVGWEIGHT Bits Field Name Description Type Reset 31 4 RESERVED Reserved bits R 0x0000000 3 2 SENPAVGWEIGHT The weighting factor for the SenP Averager RW 0x0 1 0 SENNAVGWEIG...

Page 667: ...all Summary for Register NVALUERECIPROCAL PRCM Functional Description SmartReflex Voltage Control 0 1 2 3 4 5 6 7 PRCM Basic Programming Model SmartReflex Module Initialization Basic Programming Model 8 9 10 11 Changing OPP Using the SmartReflex Module 12 13 14 15 PRCM Use Cases and Tips Device SmartReflex Initialization 16 17 18 19 Switch VDD1 OPPs 20 21 22 23 24 25 26 27 Switch VDD2 OPPs 28 29 3...

Page 668: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MCUVALIDINTSTATENA MCUACCUMINTSTATENA MCUBOUNDSINTSTATENA MCUDISABLEACKINTSTATENA Bits Field Name Description Type Reset 31 4 RESERVED Reserved R 0x0000000 3 MCUACCUMINTSTATENA Read 0 Accum interrupt status is unchanged RW 0 Read 1 Accum interrupt status is set Write 0 Accum interrupt status is unchanged Write 1 Accum interru...

Page 669: ...NASET MCUBOUNDSINTENASET MCUDISABLEACKINTSTATENA Bits Field Name Description Type Reset 31 4 RESERVED Reserved R 0x0000000 3 MCUACCUMINTENASET Read mode RW 0 0 Accum interrupt generation is disabled masked 1 Accum interrupt generation is enabled Write mode 0 No change to Accum interrupt enable 1 Enable Accum interrupt generation 2 MCUVALIDINTENASET Read mode RW 0 0 Valid interrupt generation is di...

Page 670: ...et 0x0000 0030 Physical Address 0x480C 9030 Instance SR1 0x480C B030 SR2 Description MCU interrup enable flag and clear Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MCUVALIDINTENACLR MCUACCUMINTENACLR MCUBOUNDSINTENACLR MCUDISABLEACKINTENACLR Bits Field Name Description Type Reset 31 4 RESERVED Reserved R 0x0000000 3 MCUACCUMINTENACLR Read ...

Page 671: ...r IRQENABLE_CLR PRCM Register Manual SR Register Summary 0 Table 3 563 SENERROR_REG Address Offset 0x0000 0034 Physical Address 0x480C 9034 Instance SR1 0x480C B034 SR2 Description This register gives the sensor error from the error generator Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AVGERROR SENERROR Bits Field Name Description Type Rese...

Page 672: ...rupt status is unchanged RW 0x0 0x1 Bounds interrupt status is cleared 22 VPBOUNDSINTENABLE 0x0 Bounds interrupt disabled RW 0x0 0x1 Bounds interrupt enabled 21 19 RESERVED Reserved RW 0x0 18 16 ERRWEIGHT Average Sensor Error weight RW 0x0 15 8 ERRMAXLIMIT Upper limit of sensor error for interrupt generation RW 0x7F 7 0 ERRMINLIMIT Lower limit of sensor error for interrupt generation RW 0x80 Table...

Page 675: ...icroprocessor unit MPU subsystem Topic Page 4 1 MPU Subsystem Overview 676 4 2 MPU Subsystem Integration 678 4 3 MPU Subsystem Functional Description 685 4 4 MPU Subsystem Basic Programming Model 690 675 SWPU177N December 2009 Revised November 2010 MPU Subsystem Copyright 2009 2010 Texas Instruments Incorporated ...

Page 676: ...ing the ARM subchip with additional logic for protocol conversion emulation interrupt handling and debug enhancements Figure 4 1 shows the high level block diagram of the MPU subsystem Figure 4 1 MPU Subsystem Overview 4 1 2 Features The MPU subsystem integrates the following ARM subchip ARM Cortex A8 core revision r3p2 For more information refer to the ARM Cortex A8 TRM ARM Version 7 ISA Standard...

Page 677: ...ebug features Interrupt controller INTC allows up to 96 level sensitive interrupt inputs For details see Chapter 12 Interrupt Controller Local interconnect between ARM Cortex A8 CPU Interrupt controller and L3 interconnect Clock generation and control module generates clocks power modes and idle and active acknowledge signals Emulation features ICECrusher Embedded Trace Macrocell ETM The Cortex A8...

Page 678: ...rrupts For details see Chapter 12 Interrupt Controller Local interconnect between ARM Cortex A8 CPU Interrupt controller and L3 interconnect MPU clock generator Provides clocks to internal modules of the MPU subsystem fed by the MPU digital phase locked loop DPLL of the power reset and clock management PRCM module of the device The MPU DPLL generates clock for the ARM Cortex A8 CPU and the Cortex ...

Page 679: ...t the frequency of the MPU_CLK when DPLL1 is locked and runs as the frequency of the bypass clock when DPLL1 is bypassed Local interconnect clock AXI_FCLK This clock is half the frequency of the MPU clock MPU_CLK The L3 interconnect interface thus performs at one half the frequency of the MPU Interrupt Controller Functional Clock MPU_INTC_FCLK This clock which is part of the INTC module is half th...

Page 680: ...erconnect functional clock ICECRUSHER_FCLK O ICECrusher ICECrusher functional clock 4 2 1 2 Reset Distribution Resets to the MPU subsystem are provided by the PRCM and controlled by the clock generator module There are as many reset signals as power domains For details about power domains see Section 4 3 2 1 Figure 4 4 shows the reset scheme of the MPU subsystem 680 MPU Subsystem SWPU177N December...

Page 681: ...Subsystem Reset Signals Signal Name I O Interface Comments MPU_RST I PRCM MPU power domain reset NEON_RST I PRCM NEON power domain reset CORE_RST I PRCM CORE power domain reset MPU_PWRON_RST I PRCM ICECrusher reset It is active upon a Cold reset only EMU_RST I PRCM Emulation interconnect reset EMU_RSTPWRON I PRCM Emulation modules reset 681 SWPU177N December 2009 Revised November 2010 MPU Subsyste...

Page 682: ...e MPU subsystem of the device The MPU subsystem implements the ARM Version 7 Instruction Set Architecture ISA Table 4 3 ARM Core Key Features Feature Comment ARM version 7 ISA Standard ARM instruction set Thumb 2 JazelleX Java accelerator and Media extensions Backward compatible with previous ARM ISA versions L1 Icache and Dcache 32KB 4 way 64 byte cache line 128 bit interface for Icache and 64 bi...

Page 683: ...et NEON_RST I PRCM Reset NEON only EMU_RST I PRCM Emulation interconnect reset EMU_RSTPWRON I PRCM Emulation modules reset 4 2 2 3 3 Power Management For details see Section 4 3 2 4 2 3 Local Interconnect 4 2 3 1 Description The local interconnect inside the MPU connects the ARM Cortex A8 CPU Interrupt controller and L3 interconnect 4 2 3 2 Clocks Reset and Power Management 4 2 3 2 1 Clocks Table ...

Page 684: ...l clock 4 2 4 2 Reset Table 4 9 lists the reset of the INTC It is a power domain reset that also resets the whole core domain For details see Chapter 12 Interrupt Controller and Chapter 3 Power Reset and Clock Management Table 4 9 MPU Subsystem Reset Signal Signal Name I O Interface Comments CORE_RST I PRCM CORE power domain reset 4 2 4 3 Power Management See Chapter 12 Interrupt Controller and Ch...

Page 685: ...r an FIQ to the MPU depending on the INTC programming The INTC handles only the interrupts directed to the MPU subsystem A maximum of 96 requests can be steered prioritized as MPU FIQ or IRQ interrupt requests For details see Chapter 12 Interrupt Controller 4 3 2 Power Management 4 3 2 1 Power Domains The MPU subsystem is divided into 5 power domains controlled by the PRCM as shown in Figure 4 5 N...

Page 686: ...f Off All Retention On or Off On or Off Off all clocks All or part Off Off Off Off all clocks None The PRCM manages all transitions for each power domain by controlling domain clocks domain resets domain logic power switches memory power switches and memory retention The MPU subsystem DPLL then internally synchronizes the internal clocks resets and switches 4 3 2 3 Power Modes MPU DPLL power modes...

Page 687: ... switch retention OSwR Closed switch retention CSwR These modes are described in Table 4 13 Table 4 13 MPU Retention Modes Name Mode ARM Logic L1 L2 Dormant OSwR OFF OFF RET RET CSwR ON ON RET Table 4 14 outlines the supported operational power modes All other combinations are illegal The ARM L2 NEON and ETM Debug can be powered up down independently The APB ATB ETM Debug column refers to all thre...

Page 688: ...ion mode enabled StandbyWFI controlled to put into standby and wakeup via interrupt when L2 is in retention and NEON is off 12 Standby OFF Standby Active Disabled or Standby mode StandbyWFI enabled controlled to put into standby and wakeup via interrupt when L2 is off 13 Standby OFF OFF Active Disabled or Standby mode StandbyWFI enabled controlled to put into standby and wakeup via interrupt when ...

Page 689: ... wait for interruption WFI instruction Table 4 15 Power Mode Allowable Transitions To Power Mode From 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 Y Y Y Y Y Y Y 2 Y Y Y Y Y Y Y Y 3 Y Y Y Y Y Y 4 Y Y Y Y Y Y 5 Y Y Y Y Y Y Y Y Y 6 Y Y Y Y Y Y Y Y Y 7 Y Y Y Y Y 8 Y Y Y Y 9 Y Y Y Y Y Y 10 Y Y Y Y 11 Y Y Y Y Y Y 12 Y Y Y Y 13 Y Y Y Y Y Y Y Y Y 14 Y Y Y Y Y Y Y Y For more information about clocks reset power mana...

Page 690: ...peration and applies to initial power up and wakeup from device off mode 1 Reset DPLL supply reference clock program the MPU DPLL in applicable DPLL mode to generate clocks for MPU subsystem modules This is controlled solely by the PRCM module 2 Reset the INTC CORE_RST and the MPU subsystem modules MPU_RST The clocks must be active during the MPU reset and CORE reset 4 4 3 2 MPU Into Standby Mode ...

Page 691: ... 4 MPU Power On From a Powered Off State 1 DPLL Power On MPU Power On NEON Power On Core Power On INTC should follow the ordered sequence per power switch daisy chain to minimize the peaking of current during power up NOTE The core domain must be on and reset with the clocks of the DPLL on before the MPU can be reset 2 Next follow the reset sequence as described in Section 4 4 3 1 Basic Power On R...

Page 693: ...A2 2 subsystem Topic Page 5 1 IVA2 2 Subsystem Overview 694 5 2 IVA2 2 Subsystem Integration 696 5 3 IVA2 2 Subsystem Functional Description 706 5 4 IVA2 2 Subsystem Basic Programming Model 744 5 5 IVA2 2 Subsystem Register Manual 804 693 SWPU177N December 2009 Revised November 2010 IVA2 2 Subsystem Copyright 2009 2010 Texas Instruments Incorporated ...

Page 694: ...rs L1 RAM and L2 RAM and ROM Video hardware accelerator module including local sequencer Dedicated enhanced data memory access EDMA engine to download upload data from to memories and peripherals external to the subchip Dedicated memory management unit MMU for accessing level 3 L3 interconnect address space Local interconnect network Dedicated modules SYSC and WUGEN in charge of power management c...

Page 695: ...ware accelerator Improved motion estimation dedicated hardware Improved loop filtering dedicated hardware Improved variable length coder decoder with quantizing capabilities dedicated hardware Dedicated sequencer Local interconnect Shared level 2 L2 memory interface arbiter Private direct memory access DMA controller 128 logical channels 1D 2D addressing Chaining capability Fully pipelined two 64 ...

Page 696: ...s D_DMA_ 19 0 IVA2_IRQ 47 0 EDMA_REQ 0 19 CD2_CLK IVA2_RST1 RET_RST IVA2_RET_RST IVA2_WGN_RST IVA2_RST3 iLF iVLCD iME SEQ CD2_CLK CD2_CLK SEQ_CLK VIDEO SYSC IVA2_CLK Idle handshake protocol iva2 002 Public Version IVA2 2 Subsystem Integration www ti com C friendly environment state of the art C compiler for VLIW architecture Texas Instruments low overhead DSP BIOS operating system 5 2 IVA2 2 Subsy...

Page 697: ... interfaces local interconnect EDMA MMU SYSC iVLCD iME iLF NOTE The internal clocks can be shut down by the PRCM module after the handshake protocol is complete To configure the PRCM so that internal clocks are hardware supervised set the PRCM CM_AUTOIDLE_PLL_IVA2 2 0 AUTO_IVA2_DPLL field to 0x1 For more information see Chapter 3 Power Reset and Clock Management The video sequencer module receives...

Page 698: ...s stage the DSP megamodule is kept under reset unless the MPU also cleared the PRCM RM_RSTCTRL_IVA2 0 RST1_IVA2 bit the MPU can upload some code and data in the C64x memory When the MPU has uploaded the code in the C64x memory the MPU clears the RST1_IVA2 bit releasing the DSP megamodule from reset At this point the sequencer is kept under reset unless the PRCM RM_RSTCTRL_IVA2 2 RST3_IVA2 bit was ...

Page 699: ...nd CORE_RST are released Power on reset is not applied in this case 5 2 1 2 2 Software Resets IVA2 2 subsystem reset signals are sourced from the PRCM module Some modules of the DSP subsystem can also be reset by software control The IVA2_RST1 signal maps to the PRCM RM_RSTCTL_IVA2 RST1_IVA2 bit the IVA2_RST2 signal maps to the PRCM RM_RSTCTL_IVA2 RST2_IVA2 bit and the IVA2_RST3 signal maps to the...

Page 700: ...domain includes several other system level components of the device The WUGEN module is included in the CORE power domain to enable the powered off DSP subsystem to be awakened after receiving an interrupt a DMA request or an L3 slave port access Memory voltage can be reduced locally when memory is not being used to reduce memory leakage If IVA2 2 is not active this is controlled by the PRCM PM_PW...

Page 701: ...5 Figure 5 5 IVA2 2 EDMA Requests For a description of the EDMA controller see Section 5 3 2 1 EDMA Table 5 2 lists EDMA request mappings to the IVA2 2 subsystem EDMA controller Table 5 2 IVA2 2 Subsystem EDMA Request Mappings DMA Source Description D_DMA_0 MCBSP1_DMA_TX MCBSP module 1 transmit request D_DMA_1 MCBSP1_DMA_RX MCBSP module 1 receive request D_DMA_2 MCBSP2_DMA_TX MCBSP module 2 transm...

Page 702: ...tem like SPI display subsystem or camera subsystem Peripherals that generate interrupts at the IVA2 2 level use the IVA2_IRQ 47 0 input lines of the IVA2 2 subsystem MMU interrupt The IVA2 2 MMU can generate an interrupt to an external host outside the IVA2 2 subsystem As shown in Figure 5 2 the interrupt line of the MMU IVA2_MMU_IRQ is connected to M_IRQ_28 of the MPU subsystem interrupt controll...

Page 703: ...Interrupt Mappings EVT Interrupts Events IVA2 2 Pin Name Interrupt Interrupt Description Source 0 EVT0 N A internal DSP INT CTL Output of event combiner 0 for events 4 31 1 EVT1 N A internal DSP INT CTL Output of event combiner 1 for events 32 63 2 EVT2 N A internal DSP INT CTL Output of event combiner 2 for events 64 95 3 EVT3 N A internal DSP INT CTL Output of event combiner 3 for events 96 127 ...

Page 704: ...stem 57 PRCM_IVA_IRQ IVA2_IRQ 12 PRCM PRCM module 58 DSS_IRQ IVA2_IRQ 13 Display Display subsystem module subsystem 59 Reserved IVA2_IRQ 14 N A N A 60 UART3_IRQ IVA2_IRQ 15 UART3 UART module 3 also infrared 61 MCBSP1_IRQ_TX IVA2_IRQ 16 MCBSP1 MCBSP module 1 transmit 62 MCBSP1_IRQ_RX IVA2_IRQ 17 MCBSP1 MCBSP module 1 receive 63 Reserved IVA2_IRQ 18 N A N A 64 MCBSP2_IRQ_TX IVA2_IRQ 19 MCBSP2 MCBSP ...

Page 705: ...UMC Uncorrected bit error detected 118 PDC_INT N A internal DSP PDC PDC sleep interrupt 119 SYS_CMPA N A internal DSP PMC SYS CPU memory protection fault 120 PMC_CMPA N A internal DSP PMC CPU memory protection fault 121 PMC_DMPA N A internal DSP PMC DMA memory protection fault 122 DMC_CMPA N A internal DSP DMC CPU memory protection fault 123 DMC_DMPA N A internal DSP DMC DMA memory protection faul...

Page 706: ...veral submodules that enable its integration in the device architecture The IVA2 2 subsystem provides one slave port and one master port both ports are connected to the L3 interconnect Figure 5 7 is a block diagram of the IVA2 2 subsystem Figure 5 7 IVA2 2 Subsystem Block Diagram NOTE This indicates the number of threads for IVA2 2 master slave port interrupts For details see Chapter 9 Interconnec...

Page 707: ...22 108 32 Public Version www ti com IVA2 2 Subsystem Functional Description Figure 5 8 DSP Megamodule Block Diagram 5 3 1 1 DSP Overview The C64x is an extension of the first C64x DSP section also named Kelvin The C64x features the following 32 bit fixed point media processor VLIW architecture 8 instructions cycle 8 execution units 707 SWPU177N December 2009 Revised November 2010 IVA2 2 Subsystem ...

Page 708: ...ation of SRAM to cache or memory mapped SRAM DMA transfer from to SRAM Fair priority based arbitration between DSP DMA and cache controller for access to the SRAM Block and global program initiated cache coherence support invalidate Freeze mode support In the IVA2 2 subsystem the PMC controls the 32 KB SRAM typically used as cache RAM However the allocation of SRAM can be software configured to ke...

Page 709: ...ite back invalidate Freeze and bypass modes support Per page memory protection attribute check support Emulation support Long distance access support noncacheable data accesses Page based memory automatic power down to clock off state and wake up support The UMC contains the interfaces to L2 memory the L1D the L1P and the EMC The EMC houses the interfaces to the EDMA and internal data memory acces...

Page 710: ...ut illegal memory accesses Prevents unauthorized access to sensitive data Allows the OS to enforce clearly defined boundaries between supervisor and user mode accesses leading to greater system robustness Memory protection is implemented for the PMC DMC UMC and EMC and also for the IDMA and EDMA modules 5 3 1 7 INTC The DSP megamodule INTC detects potentially combines and routes up to 128 system e...

Page 711: ...P Megamodule INTC Block Diagram NOTE Not all of the 128 event inputs of the INTC are connected to an internal or external event line Table 5 3 lists the global interrupt mapping of the DSP INTC Some interrupts at the IVA2 2 boundary are reserved for future use or are not used by the IVA2 2 subsystem For information about the DSP core INTC see the C64x DSP documents listed in Section 5 3 1 8 Other ...

Page 712: ...nt from the logical OR of 32 system event flags qualified by a mask provided through programmable registers IC EVTMASKi where i 0 to 3 The combination of the event flags creates an event that is asserted when any of the event flags included in its generation is active Software must clear the event flags IC EVTCLRi where i 0 to 3 to deassert a combined event NOTE The use of event flags makes it imp...

Page 713: ...ster but do not affect when the DSP CPU interrupt is generated The event flags in the IC EVTFLAGi registers retain the value of 1 for any event received These registers are read only and must be cleared through the write only IC EVTCLRi registers The IC EVTSETi registers can be used to manually set bits in the IC EVTFLAGi registers including those that are masked NOTE Because external events are m...

Page 714: ...me strategy of register settings events event set event clear event mask is used in the WUGEN which is not really an INTC which enables defining wake up events so that they can wake up the IVA2 2 subsystem For more information see Section 5 3 6 Wake Up Generator For more information see Section 5 4 8 Interrupt Management See Section 5 4 IVA2 2 Subsystem Basic Programming Model for information on a...

Page 715: ...Programmers Guide TI literature number SPRU198 describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples TMS320C64x to TMS320C64x CPU Migration Guide application note TI literature number SPRAA84A 715 SWPU177N December 2009 Revised November 2010 IVA2 2 Subsystem Copyright 2009 2010 Texas Instruments Incorporated ...

Page 716: ...nts Third party DMA channel controller TPCC Third party DMA transfer controller TPTC There are two instances of the TPTC in the IVA2 2 subsystem Figure 5 11 shows how the EDMA is integrated in the IVA2 2 subsystem Code running on the DSP can configure the EDMA through the DSP megamodule configuration port and the local interconnect the code can program DMA transfers and software trigger them by wr...

Page 717: ...m IVA2 2 Subsystem Functional Description Figure 5 11 IVA2 2 EDMA Overview 5 3 2 1 1 Third Party Channel Controller The TPCC is the DMA transfer scheduler responsible for scheduling arbitrating and issuing user programmed transfers to the two TPTCs 5 3 2 1 1 1 TPCC Features The TPCC features are as follows Parameter RAM PaRAM entires holding up to 128 transfer contexts with the following capabilit...

Page 718: ...AM entry can be used as a DMA entry up to 64 QDMA entry up to 8 or link entry remaining Up to 64 DMA logical channels 64 channels can be triggered explicitly by the DSP CPU DMA entry 64 channels can be triggered by 20 external events see Table 5 2 All channels can be triggered by completion of a previous transfer in a user programmed chain of transfers linked entry 8 channels can be triggered auto...

Page 719: ...s QDMA The only difference between a QDMA and a DMA transfer is the specific means of generating recognizing TR synchronization From the user point of view DMA and QDMA transfer types can be combined to perform various types of transfers DMA channel TR synchronization can be generated from one of three sources Event triggered The event register TPCC_ER channel n bit is set as the result of an exte...

Page 720: ... is designated with a 9 bit PAENTRY TPCC_DCHMAPi 13 5 PAENTRY and TPCC_QCHMAPj 13 5 PAENTRY bit fields PaRAM entry number that defines the entry number in a 128 entry maximum PaRAM see Figure 5 13 TPCC_QCHMAPj 4 2 TRWORD points to the trigger word of the PaRAM entry defined by PAENTRY A write to the trigger word results in a QDMA event being recognized Figure 5 13 DMA QDMA Channel Mapping and PaRA...

Page 721: ...first array in the previous frame For information about parameter updates see Section 5 3 10 Error Reporting In a 2D synchronized transfer each TR synchronization triggers the transfer of two dimensions or one frame In other words each TR packet conveys information for one entire frame of BCNT arrays of ACNT bytes Arrays can be separated by SBIDX and DBIDX as shown in Figure 5 15 Frames can be sep...

Page 722: ...MA active register set Stores the context src dst cnt etc for the DMA transfer request in progress in the read controller The active register set is split into independent source and distant register halves because the source local interconnect controller and distant local interconnect controller operate independently of each other Distant DMA register set Stores the context src dst cnt etc for th...

Page 723: ... TC external control use model the user does not directly program the active and program register sets Instead the TPCC is the user interface to the EDMA system and the TPTCs TPTC0 and TPTC1 are slaves to the TPCC This is the use case of the EDMA in device applications 5 3 2 1 2 2 Transfer Geometry The TPTC supports a transfer geometry fully defined by the registers summarized here see Figure 5 15...

Page 724: ... source active register set TPTCj_SAOPT TPTCj_SASRC TPTCj_SACNT TPTCj_SADST TPTCj_SABIDX TPTCj_SAMPPRXY TPTCj_SACNTRLD TPTCj_SASRCBREF and TPTCj_SADSTBREF tracks commands for the source side of the transfer and the distant FIFO register set TPTCj_DFOPTi TPTCj_DFSRCi TPTCj_DFCNTi TPTCj_DFDSTi TPTCj_DFBIDXi and TPTCj_DFMPPRXYi tracks commands for the distant side of the transfer As the source and di...

Page 725: ...nd TPTCj_DFOPTi 22 TCCHEN bits and TPTCj_DFOPTi 17 12 TCC where i 0 to 3 when j 0 and i 0 or 1 when j 1 If TCINTEN or TCCHEN is set to 1 the TPTC must return completion information on completion of the entire TR The TPCC uses completion information for chaining enabled by TCCHEN or for posting interrupts enabled by TCINTEN The TPTC generates status conditions based on completion of a transfer TPTC...

Page 726: ...iLF iME iVLCD to from external memories The DSP megamodule programs the EDMA through the IVA2 2 local interconnect whereas the sequencer programs the EDMA through the video and sequencer local interconnect The EDMA can access the following module registers and memories in the video accelerator sequencer iME configuration registers iLF configuration registers iVLCD configuration registers and memor...

Page 727: ...IVA2 2 modules connected to the DSP megamodule configuration port and it is useful for the DMA PaRAM entries To allow an easy configuration of IVA2 2 modules the IDMA channel contains five registers status mask source address destination address and window count For information about the use of channel 0 for an offloaded configuration see Section 5 4 4 6 5 Offloaded Configuration Using IDMA IDMA c...

Page 728: ... external addresses to physical addresses in the 32 bit MPU address space Address translation is performed by a translation table structure TTB that maps the most significant bits MSBs of the DSP byte address to another set of MSBs of a 32 bit MPU byte address The least significant bits LSBs of the DSP generated byte address are used as page section indices in the address translations and are not ...

Page 729: ...es software intervention the MPU services the event IVA2 2 MMU service requests are signaled to the MPU with a dedicated interrupt M_IRQ 28 Generally the MMU is initialized at boot time but it can also be dynamically reprogrammed Typically the MMU is programmed by the MPU through the IVA2 2 slave port on the L3 interconnect when a new task is created on the IVA2 2 subsystem But the DSP also has ac...

Page 730: ...y Mapping Device Name Start Address End Address Size Description Hex Hex L2 memory 0x0 0000 0x0 7FFF 32KB L2 shared SRAM Reserved 0x0 8000 0x1 FFFF 96KB Reserved DMA registers 0x2 0000 0x3 FFFF 128KB Configuration registers Reserved 0x4 0000 0x7 FFFF 256KB Reserved iVLCD registers 0x8 0000 0x8 1FFF 8KB Configuration registers Reserved 0x8 2000 0x8 3FFF 8KB Reserved iVLCD IBUF0_A 0x8 4000 0x8 43FF ...

Page 731: ...F 16KB Reserved 5 3 5 SL2 Interface The SL2 memory interface SL2IF provides access to L2 memory for the following units iME iLF Video accelerator sequencer interconnect The SL2 memory interface is composed of two modules Bandwidth optimizer BWO for video accelerator sequencer local interface interconnect Arbiter Figure 5 18 is a block diagram of the SL2 memory interface 731 SWPU177N December 2009 ...

Page 732: ...ription www ti com Figure 5 18 SL2 Memory Interface Block Diagram 5 3 5 1 BWO The BWO optimizes write bandwidth and read latency for connections from to the local interconnect from to the shared L2 memory It has two components 256b write buffer to gather bursted write data before sending them to the shared L2 732 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Tex...

Page 733: ...strictions on SL2 Memory Usage Because accesses to SL2 from iME iLF or any other initiator with access to the SL2IF interface are not checked for access permission the SL2 memory must not be used for memory protected or sensitive data SL2 memory must not be used to store sequencer instructions to be fetched directly by the sequencer the SL2IF is not designed to efficiently serve sequencer instruct...

Page 734: ...rt access This register is read only only by the DSP To modify the value of the individual mask write 1 to the associated bits of WUGEN_MEVTCLR0 WUGEN_MEVTCLR1 and WUGEN_MEVTCLR2 to clear and WUGEN_MEVTSET0 WUGEN_MEVTSET1 and WUGEN_MEVTSET2 to set The WUGEN_PENDEVT0 WUGEN_PENDEVT1 and WUGEN_PENDEVT2 registers are read only registers that track which external events are pending in the WUGEN module ...

Page 735: ...generated The event to DSP megamodule EDMA is deasserted after one WUGEN clock cycle D After some time the source of the event is released probably because it cleared in the corresponding interrupt status register E The release of the event is detected and clears the internal EVT_GENERATED flag for that interrupt 5 3 6 1 2 Individual Event Masking To mask individual events write 1 in the WUGEN_MEV...

Page 736: ...MEVT0 to IVA2 2 WUGEN_MEVT2 registers where i 0 to 2 for reads C An asynchronous event is asserted D The event is resynchronized and detected Because the event is masked it is not propagated to DSP megamodule EDMA The event pending flag is kept active sticky until the mask is removed 5 3 6 1 3 Individual Event Mask Clear To unmask individual events write 1 in the WUGEN_MEVTCLR0 WUGEN_MEVTCLR1 or W...

Page 737: ...f the event is not seen as active nothing happens D In both cases the event pending flag is cleared For more information about interrupts and the EDMA programming model see Section 5 4 8 Interrupt Management and Section 5 4 4 1 Transfers From to Device Memories Peripherals EDMA 5 3 6 2 Idle Handshake After reset the WUGEN waits for a request If the user executes the DSP IDLE instruction to put the...

Page 738: ...SC Block Diagram NOTE For more information see Section 5 2 1 Clocking Reset and Power Management Scheme 5 3 7 1 Divided Clock Generation The SYSC module generates the divided clocks used by the modules in the IVA2 2 subsystem The SYSC generates three clocks CD0_CLK CD1_CLK CD2_CLK Based on the IVA2 2_FCLK clock these three clocks are configured from the PRCM For details see Section 5 2 1 Clocking ...

Page 739: ... SYSC_GENERAL1 CONTROL_IVA2_BOOTMOD which are read write accessible by the MPU subsystem for MPU driven IVA2 2 boot sequence and or by the IVA2 2 DSP for autonomous boot For more information see Section 5 4 1 IVA2 2 Boot NOTE If the values of the SYSC_GENERAL1 CONTROL_ IVA2_BOOTADDR and SYSC_GENERAL1 CONTROL_IVA2_BOOTMOD registers change the new IVA2 2 SYSC_BOOTADDR and IVA2 2 SYSC_BOOTMOD registe...

Page 740: ...escription 7 Reserved Reserved 6 SEQ_MBX Sequencer mailbox IRQ 5 DMA_ERROR DMA error IRQ 4 HOST_ERROR HOST error IRQ 3 Reserved Reserved 2 IVLCD iVLCD IRQ 1 iLF iLF IRQ 0 iME iME IRQ Four registers are defined for IRQ operation The IVA VIDEOSYSC_IRQSTATE register tracks input events Each event is associated with a bit in this register When the bit is set after an active pulse on the associated eve...

Page 741: ... L1 Program Cache L1 Data Cache L2 Unified Cache SIZE Programmable to 0KB 4KB 8KB Programmable to 0KB 4KB 8KB Programmable to 0KB 32KB or 16KB or 32KB 16KB or 32KB 64KB ASSOCIATIVITY Direct mapped Two way set associative Four way set associative SRAM MODE Programmable to 0KB 16KB Programmable to 48KB 64KB Programmable to 32KB 64KB or memory mapped SRAM 24KB 28KB 32KB 32KB cache 72KB 76KB 80KB 80KB...

Page 742: ...figured so that the memory mapped RAM allocates 32KB 64KB or 96KB no cache of L2 memory The remaining memory is allocated to the cache controller By default L2 memory is used as 96 KB local memory mapped RAM However L2 RAM is typically used as 64KB allocated to the cache RAM This is programmable in the DSP megamodule UMC The L2 memory mapped SRAM is shared by the DSP megamodule and the SL2 interfa...

Page 743: ...TERR signal L3 out of band errors are also reported through the external L3 interrupt signal For details about interrupt mapping see Table 5 3 For information about L3 interconnect error reporting see Chapter 9 Interconnect The IDMA and EDMA have their own error reporting mechanism Error status registers and error interrupts inform the user of problems during IVA2 2 internal operation data error b...

Page 744: ...oot sequence followed by IVA2 on release from reset Figure 5 25 IVA2 Boot Mode Configuration When the IVA2 2 subsystem is released from reset and CONTROL CONTROL_IVA2_BOOTMOD 3 0 BootMode equals 0x0 the first fetch address of the C64x equals the address defined in the CONTROL CONTROL_IVA2_BOOTADDR 31 10 BOOTLOADADDR bit field This address can be aligned on any 1 K byte boundary in ROM in IVA2 2 lo...

Page 745: ...encies penalties for wake when megamodule is active and Static clock gating to the PMC when megamodule is in standby 5 4 1 1 2 Wait in Self Loop Mode In this mode boot loader puts the IVA2 in a self loop The MPU then has the option to download the bootstrap code from the MPU side directly into IVA2 internal memory through host port interface L3 slave interface MPU then sets up CONTROL CONTROL_IVA2...

Page 746: ...2 Header Format Used in User Defined Bootstrap Mode Offset from Base Address of Header in bytes Fields Description 0x00 Size of the boot strap code in bytes that will be downloaded into internal memory 0x04 0 Use DMA for transferring the bootstrap code 1 Use CPU copy for transferring the bootstrap code 0x08 Value of L2CFG register to be loaded 0x0C Absolute address of L2 memory where the boot stra...

Page 747: ...ZE bit field v Write MMU physical address 31 12 to the MMU2 MMU_RAM 31 12 PHYSICALADDRESS bit field vi Write 1 to the MMU2 MMU_LD_TLB 0 LDTLBITEM bit vii Write 0x1 to the MMU2 MMU_LOCK 8 4 CURRENTVICTIM bit field viii Write 0x1 to the MMU2 MMU_LOCK 14 10 BASEVALUE bit field c Write 1 to the MMU2 MMU_CNTL 2 TWLENABLE bit d Write 1 to the MMU2 MMU_CNTL 1 MMUENABLE bit e Read back the MMU2 MMU_CNTL r...

Page 748: ...keup the IVA2 2 subsystem is released from reset After hardware configuration of values for DSP megamodule generic parameters the IVA2 2 starts fetching from the address 0x00000000 in ROM The IVA2 2 must follow the nonexhaustive boot process 1 Configure memory protection a Specify cache RAMs versus IDMA and DMA accesses b Define accessible L2 space static shared L2 with the MPU LCD 2 Load the boot...

Page 749: ... reset see ARM968E S Technical Reference Manual ARM 5 4 3 Cache Management The IVA2 2 subsystem has a 2 level cache based architecture Level 1 data memory cache L1D consists of an 80 KB memory space dedicated to data L1D memory can be configured as mapped memory cache or a combination of the two The level 1 program memory cache L1P consists of a 32 KB memory space dedicated to program instructions...

Page 750: ... default 001b 32KB 010b 64KB When programs initiate a cache mode change the L1D cache must write back and invalidate its current contents without losing data This ensures that all updated data held in cache is written back and that no false hits occur because of a change in the interpretation of cache tags It also ensures that the L1D snoop tag RAM in the UMC stays in sync with L1D While the write...

Page 751: ...and bypass modes affect the operation of only the cache section no impact on the memory mapped section of the memory of each memory controller This feature allows real time applications to limit the amount of data evicted from cache controllers such as interrupt handlers during various sections of code Table 5 18 summarizes the freeze and bypass modes for each cache controller set through the OPER...

Page 752: ...L1D cache content and the L2 memory mapped memory region An L2 reference from the DSP CPU updating an L1D cache location is automatically made visible to the DMA and any master processor on the device with access to the DSP megamodule memory mapped L2 through the IVA2 2 slave port An L2 reference from the DMA and any other master processor on the device with access to the DSP megamodule memory map...

Page 753: ... lines are written back to end memory so that any local update by the DSP CPU is made visible by an alternate processor DMA This applies only to L1D cache and L2 cache not to L1P cache Write back and invalidate ensure that all required cache lines modified by the DSP CPU also called dirty lines are written back to end memory so that any local update by the DSP CPU is made visible by an alternate p...

Page 754: ...the following registers IVA_XMC L2BAR IVA_XMC L2IWC IVA_XMC L1DIBAR IVA_XMC L1DIWC IVA_XMC L1PIBAR and IVA_XMC L1PIWC Example of block invalidate Write base address of array to Base Address Register Then write length of the array in words to the Word Count register L2IBAR array 0 L2IWC sizeof array sizeof int The CPU can execute other code here Block cache operations proceed in parallel with CPU e...

Page 755: ... address range see Section 5 4 3 4 6 for additional programming steps and an example 5 4 3 4 6 Write Back Completion The SYSC_LICFG0 15 GEMTRUECOMPEN bit must be set to 1 before any DSP CPU C64x write for which completion must be ensured This applies to writes to noncacheable regions and to cache line write back completions By default SYSC_LICFG0 15 GEMTRUECOMPEN 0 This default is recommended to s...

Page 756: ...case of the C64x writing in the noncache area To ensure the completion of the C64x write in physical end memory set the SYSC_LICFG0 15 GEMTRUECOMPEN bit to 1 and also read back after the last C64x write 1 DSP write and DMA read The user writes to some noncache region with DSP and then reads from the same area with DMA To ensure completion of the DSP write in physical end memory set the SYSC LICFG0...

Page 757: ...this is a transfer from memory to memory or if this is a solid color fill An IDMA1 transfer where iDMA IDMA1_COUNT 16 FILL 0 copies IDMA IDMA1_COUNT 15 2 COUNT bytes from the address defined in the IDMA IDMA1_SOURCE register to the address defined in the IDMA IDMA1_DEST register The addresses must be aligned on word 4 byte boundaries The byte count must be a multiple of 4 bytes The IDMA IDMA1_COUN...

Page 758: ...nd the corresponding Figure 5 13 Logical channel definition relies on the following Base addresses PARAM LCH SRCi 32 bit source address PARAM LCH DSTi 32 bit destination address Transfer sizes Transfer size is common to source and destination A transfer can be constituted on a 3 dimensional array C is an array of CCNT arrays each composed of BCNT arrays each composed of ACNT bytes PARAM LCH ACNT N...

Page 759: ...wo dimensions meaning that a 3 dimensional transfer is always split into at least 2 dimensional transfers The user can also program the logical channel so that submitted requests are 1 dimensional transfers for example PARAM LCH SYNCDIM 0 submitted transfers are maximum 1D PARAM LCH SYNCDIM 1 submitted transfers are maximum 2D 5 4 4 4 3 Linking to Another Logical Channel A logical channel can be p...

Page 760: ... started after LCHi has completed PARAM LCHi OPT TCC trigEvtx trigEvtx trigger event number PARAM LCHi OPT TCCHEN 1 DCHMAP trigEvtx LCHj 5 4 4 5 Prioritizing Defined Transfers 5 4 4 5 1 Mapping Between DMA QDMA Events and Event Queues The assignment of 64 DMA and 8 QDMA channels to two event queues of the channel controller is achieved by configuring the DMA queue number registers TPCC_DMAQNUM0 an...

Page 761: ... is disabled SYSC_LICFG1 0x0 and arbitration priority is dictated by programmed values in QUEPRI and MDMAARBE 5 4 4 5 5 Optimizing 2D Transfers IVA2 2 EDMA can be configured so that DMA 2D transfers are optimized allowing for large bursts to be generated to the SDRAM This optimization has no effect on transfers issued as 1D transfers to the physical channels This is recommended to enable that feat...

Page 762: ...hannel is defined and prioritized the user can assign the logical channel or the first in the chained list to a trigger event from 0 to 19 by writing the number of the logical channel PaRAMEntry to one of the DMA channel mapping registers TPCC_DCHMAPi i 0 to 19 The user can allow this logical channel to be triggered by an associated hardware DMA request by writing 1 in the associated bit of the EE...

Page 763: ...another simple DMA internal to DSP megamodule IDMA For example disable_interrupts while IDMA0_STATUS 0x3 previous IDMA completion Update of logical channels definition table in L1D LCTable OPT opt LCTable SRC src LCTable ACNT num_bytes LCTable BCNT num_arrays LCTable DST dst LCTable DSTBIDX dbidx LCTable SRCBIDX sbidx LCTable LINK 0xFFFF LCTable BCNTRLD bcntrld LCTable DSTCIDX dcidx LCTable SRCCID...

Page 764: ...ns IPR IPRH bit update for polling scheme Interrupt generation for interrupt scheme CER CERH bit update for chaining 5 4 4 6 8 Partial Versus Total Completion DMA can be programmed so that IPR bit update and interrupt generation occur After each submission to the physical channel is complete After the last submission to the physical channel is complete Partial completion interrupt After the submit...

Page 765: ...myTCC myTCC does contribute to interrupt generation polling mode IER IER 1 myTCC 1 myTCC INTMUX 0 INTMUX 0 0x7F 0x1D map CPU it 4 CPU IER CPU IER 1 4 1 4 unmask CPU it 4 enable_interrupts start transfer DCHMAP myEvt DCHMAP myEvt 0x1FF 5 myLCH 5 ESR 1 myEvt do something useful that does not depend on DMA completion this code is interrupted when DMA completes 5 4 4 6 10 DMA Interrupt Service Routine...

Page 766: ...and in the QTHRXCDn field in the TPCC_CCERR register 5 4 5 IVA2 2 Extended Function Interface This section describes the extended function interface EFI signals timing and associated instructions The EFI runs at the CPU clock that allows the transfer of data between the CPU register file and registers at the CPU boundary that are attached to devices outside the CPU The C64x CPU does not support an...

Page 767: ...EFCMD instruction does not use any data path resources It is available for scheduling purposes on the S or M units Only one EFCMD instruction can be scheduled per side the S or M slot on a side can be used but not both in the same execute packet If used in an SPLOOP body the EFCMD instruction occupies an execution slot corresponding to the unit specified The 10 bit command is output at the CPU bou...

Page 768: ... Delay slots 0 See also EFRW EFRW Receive Word From EFI Syntax EFRW unit dst unit S1 S2 Compatibility C64x CPU only Opcode 3 2 2 2 2 2 1 1 1 1 1 6 5 4 3 2 1 0 1 9 8 7 3 2 8 7 3 2 1 0 0 0 0 dst 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 1 0 0 0 s p Opcode map field used For operand type Unit dst int S1 S2 Description A 32 bit data value is read from the EFI and is written to dst There is an A side EFI and a...

Page 769: ...register provides the 32 LSBs and the src1 register provides the 32 MSBs There is an A side EFI and a B side EFI The side used is determined by the L unit that is selected The data and constant are output at the CPU boundary in E2 The EFI ready signal is sampled in E2 of the EFSDW instruction and will cause the CPU to stall if the signal indicates the buffering external to the CPU is full Executio...

Page 770: ...cle Delay slots 0 See also EFSDW 5 4 5 3 C64x EFI Use in IVA2 2 The following programming model describes how to write and read a register using the EFI In the context of IVA2 2 only the EFSW EFRW and EFSDW instructions are used 5 4 5 3 1 Read Registers Using the EFI Programming Model To read a 32 bit value in a video accelerator register using the EFI the following sequence must be used EFSW addr...

Page 771: ...ol 5 4 5 3 2 Write Registers Using the EFI Programming Model To write a 32 bit value in a video accelerator register using the EFI the following instruction must be used EFSDW value_32b address_32b opcode_5b With The value_32b register contains the 32 bit word to write address_32b is the video accelerator address of the register in which value must be written opcode_5b is used to code the write op...

Page 772: ...ting to START in the iME_COMMANDREG or iLF_COMMANDREG register Step 8 Wait for the coprocessor interrupt the DSP or sequencer is free to perform other tasks during coprocessor processing Steps 2 3 and 4 can be performed with the help of the DSP EDMA which can be configured by both the sequencer and the DSP megamodule Steps 5 6 and 7 can be performed by both the sequencer and the DSP megamodule but...

Page 773: ...LF_ CPUSTATUSREG 30 26 0x00 Yes No Set ILF IME_COMMANDREG 2 0 CMD bit field to 0x02 to stop iME iLF module DSP EDMA DSP megacell or sequencer processor iva2 038 Public Version www ti com IVA2 2 Subsystem Basic Programming Model Figure 5 27 iME iLF Typical Use Flow Chart 5 4 7 iVLCD Basic Programming Model The iVLCD coprocessor is a parallel coprocessor where interrupt capabilities It is partially ...

Page 774: ...CD processing DSP EDMA DSP megacell or sequencer processor iva2 039 Public Version IVA2 2 Subsystem Basic Programming Model www ti com To accelerate transfer the IVA EDMA has access to iVLCD local memories see Section 5 3 2 2 EDMA Access to Video Accelerator Sequencer The EDMA can be programmed by the DSP megamodule or by the sequencer A typical use of iVLCD includes the 5 steps shown in Figure 5 ...

Page 775: ...MDELIQ field is set as follows if qp 0x1 0 delta_q qp 1 else delta_q qp where qp is the quantizer scale The IVA VLCD_MPEG_DELTA_Q 8 0 MDELQ field is set to 0 For MPEG1 2 the IVA VLCD_MPEG_DELTA_Q 8 0 MDELQ and IVA VLCD_MPEG_DELTA_IQ 8 0 MDELIQ fields are set to 0 5 4 7 1 4 Q IQ Threshold The IVA VLCD_MPEG_THRED 11 0 MTHRED field is the quantization threshold for intra AC coefficients and intercoef...

Page 776: ...101 for MPEG4 data partition 110 for MPEG4 RVLC D and value 111 is reserved IVA VLCD_VLCDIN_ADDR input address register IVA VLCD_VLCDOUT_ADDR output address register Because the bit size of a codeword can be other than 16 bits the bitstream buffer pointer register alone is not sufficient to determine the precise location of the next codeword to be written in the bitstream To get the complete locat...

Page 777: ...ollowing bits the iVLCD coprocessor enables great flexibility letting the programmer choose the type of decoded data format and the number of macroblocks decoded at a time IVA VLCD_MODE 2 0 FUNC field Determines the VLC encode function Value 000 for Q 001 for IQ 010 for VLC 011 for VLD 100 for Q IQ 101 for Q VLC 110 for Q IQ VLC 111 for VLD IQ IVA VLCD_MODE 7 MPEGINTRA bit Determines whether the b...

Page 778: ...inter to the starting word of the UVLD symbol table DC Y This address is relative to the base address of the iVLCD coefficient buffer and must be 32 bit aligned IVA VLCD_SYMTAB_ACi i 0 symbol look up table base address register Holds the address pointer to the starting word of the UVLD INTER AC symbol table This address is relative to the base address of the iVLCD coefficient buffer and must be 32...

Page 779: ... a bits2 VLCD_BITS_BPTR 3 0 BPTR value after VLD start b words2 VLCD_VLCDIN_ADDR 12 0 ADDR value after VLD start 4 Number of bits processed words2 wors1 16 bits1 bits2 5 4 7 5 Setting Up Registers for CAVLC Operation Before starting to encode a bitstream the iVLCD must be initialized correctly by initializing coprocessor registers and setting up the VLC look up tables Some initial register values ...

Page 780: ... same as that of the H 264 standard IVA CAVLC_HDPTR Set a pointer on Hmem memory to read the MB header symbol and its length IVA CAVLC_HDCOUNT This register contains the number of MB header pairs The range of this value is 0 to 1023 IVA CAVLC_NAPTR Set a pointer on Hmem memory from which nA parameters are stored IVA CAVLC_NBPTR Set a pointer on Hmem memory from which nB parameters are stored IVA C...

Page 781: ...1 RW 0 EVTFLAG1 R 0 EVTMASK1 RW 0 EVTCLR2 RW 0 EVTFLAG2 R 0 EVTMASK2 RW 0 EVTCLR3 RW 0 EVTFLAG3 R 0 EVTMASK3 RW 0 INTMUX3 INTMUX2 INTMUX1 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 INT7 INT6 INT5 INT4 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 GIE iva2 040 R 1 WR 0 R 0 R 0 ...

Page 782: ...amming Sequence The INTC allows programming independently which of the 128 inputs events is mapped to each DSP CPU interrupt by writing the event number in the bit field corresponding to the CPU interrupt in the IC INTMUXj registers where j 1 to 3 Example evtTable has the 12 evt CPU interrupt mapping evtTable 0 55 Mailbox event highest priority evtTable 1 61 McBSP1TX event evtTable 11 29 EDMA3 gbl...

Page 783: ...re that all wake up events are correctly mapped to enabled DSP CPU interrupts and are unmasked in combined event registers if combined events are used 2 Clear correct bits in the WUGEN_MEVT0 and WUGEN_MEVT1 registers to unmask wake up interrupts 3 Save necessary context all except interrupt related registers NOTE Steps 3 through 5 are automatic but interruptible If a wake up interrupt occurs at th...

Page 784: ...he TSR and CSR registers For a complete description of these registers see the C64x documentation Section 5 3 1 8 b Remap interrupts by configuring the IVA_IC INTMUXj registers where j 1 to 3 c Set the DSP CPU TSR 0 or CSR 0 GIE bit to 1 to enable all DSP CPU interrupts The DSP CPU software recognizes which degree of power state the C64x reaches when executing the IDLE instruction because the PRCM...

Page 785: ...t selector combiner If a noncombined event is mapped to an enabled DSP CPU interrupt the associated combined event is masked in the associated IVA_IC EVTMASKi where i 0 to 3 register and or the combined event is not mapped to the DSP CPU interrupt Reciprocally if a combined event is mapped to a DSP CPU interrupt all the unmasked events in the associated IVA_IC EVTMASKi with i 0 1 to 3 register are...

Page 786: ...Q interrupt This single interrupt is driven by all the video accelerator interrupts DSP EDMA interrupts DSP megamodule soft interrupts and error interrupts Registers are available to manage these interrupts in the sequencer Before servicing an interrupt the sequencer ISR must 1 Identify the source event s for the interrupt line assertion 2 For each source event a Clear the interrupt at the source ...

Page 787: ...ENTLOG If set iva2 041 Public Version www ti com IVA2 2 Subsystem Basic Programming Model Step 1 is done hierarchically through reading the IVA VIDEOSYSC_IRQSTATE register and depending on which bit is set through reading of the IVA module _IRQSTATUS registers or equivalent see Figure 5 30 Step 2 is done hierarchically as well but in the reverse order using IVA module _IRQCLEAR or equivalent first...

Page 788: ...etches L1P caches the memory range regardless of the values of the MAR bits 5 4 9 1 2 Virtual Addressing The device embeds two instances of MMU one instance is camera MMU also named MMU1 dedicated to the camera subsystem the other instance is IVA2 2 MMU also named MMU2 used by the IVA2 2 subsystem For more information about MMU2 software settings at IVA2 2 boot see Section 5 4 1 2 Example of IVA2 ...

Page 789: ... 0x007E 3000 0x007E 3FFF UMAP 0 64KB flat cache RAM Page size 2KB UMAP 1 16KB ROM Page size 4KB L2MPPA 36 L2MPPA 55 Unmapped memory reserved registers 0x007F 8000 0x107F 8FFF 0x107F F000 0x107F FFFF UMAP 1 32KB shared flat RAM Page size 4KB iva2 044 Public Version www ti com IVA2 2 Subsystem Basic Programming Model Figure 5 32 L1D Memory Protection Registers Figure 5 33 L2 Memory Protection Regist...

Page 790: ...0x0080 9000 0x0080 97FF 19 0x00E0 1800 0x00E0 1FFF 0x00F1 1800 0x00F1 1FFF 0x0080 9800 0x0080 9FFF 20 0x00E0 2000 0x00E0 27FF 0x00F1 2000 0x00F1 27FF 0x0080 A000 0x0080 A7FF 21 0x00E0 2800 0x00E0 2FFF 0x00F1 2800 0x00F1 2FFF 0x0080 A800 0x0080 AFFF 22 0x00E0 3000 0x00E0 37FF 0x00F1 3000 0x00F1 37FF 0x0080 B000 0x0080 B7FF 23 0x00E0 3800 0x00E0 3FFF 0x00F1 3800 0x00F1 3FFF 0x0080 B800 0x0080 BFFF 2...

Page 791: ...k The AIDX bit maps to PrivIDs that do not have dedicated AID bits associated with them This bit refers to external mastering peripherals especially on devices with a large number of CPUs If a given device must discriminate among external mastering peripherals it can assign lower numbered PrivIDs to these peripherals For the EDMA module the AIDX bit is the TPCC_MPPAj 9 and TPCC_MPPAj 9 EXT bits Th...

Page 792: ... ICFGMPFSR for IDMA and TPCC_MPFSR for EDMA Using the MPFSR register a memory protection fault can be decoded as follows by software If the LOCAL status bit is set to 1 the request was a local DSP CPU request to its own memories Otherwise if the LOCAL status bit is set to 0 the VBUS ID of the faulting requestor is in the MPFSR 15 9 field The value of the access type field SR SW SX UR UW UX indicat...

Page 793: ...priority requestor When contention occurs for multiple successive cycles a contention counter ensures that the lower priority requestor gets access to the resource every one out of n arbitration cycles where n is programmable through the MAXWAIT field For each identified requestor a corresponding MAXWAIT field controls the maximum number of cycles that a request can be blocked CPUARB registers CPU...

Page 794: ...uration bus transfers and IDMA channel 1 used for memory to memory transfers The IDMAARB 5 0 MAXWAIT field is used to determine the maximum wait time for IDMA transactions The priority level is not programmed through the IDMAARB register Instead the priority level is programmed directly through the IDMA control registers In summary IDMA transfer priority is IDMA channel 0 Always highest priority I...

Page 795: ...copied from the IVA_IDMA MDMAARBE 18 16 PRI field NOTE Because no internal arbitration results from the IVA_IDMA MDMAARBE register there is no need for the MAXWAIT field in this register 5 4 9 3 SL2 Memory Management 5 4 9 3 1 SL2 Performance Optimizations To limit the number of accesses through the SL2 interface and to optimize bandwidth it is recommended that the user access SL2 using as much as...

Page 796: ... The IVA2 2 SYSC module implements automatic clock gating on internal hardware detection of the absence of activity The transition from clock gated to clock nongated state is operated with no cycle latency penalty The automatic clock gating feature is enabled by setting the IVA_SYSC SYSC_SYSCONFIG 0 AUTOIDLE bit to 1 default value This feature can be disabled by setting the IVA_SYSC SYSC_SYSCONFIG...

Page 797: ...lled with the IVA_SYS PDCCMD 5 4 DMCLOG and IVA_SYS PDCCMD 7 6 xMCMEM fields The programming sequence for transition to clock off state is as follows Before executing the IDLE instruction the user must perform the following sequence 1 Write 1 to the IVA_SYS PDCCMD 16 GEMPD bit standby state by default the IVA_SYS PDCCMD xMCLOG 1 0 and IVA_SYS PDCCMD xMCMEM 1 0 x P D U field values are all 0x1 so t...

Page 798: ...SC_BOOTADDR 31 12 BOOTLOADADDR Configure the PDC IVA2 power down controller Start IVA2 power off IVA2 ready to go to off mode iva2 045 Public Version IVA2 2 Subsystem Basic Programming Model www ti com Figure 5 34 IVA2 Power Off The user must also ensure that no other instruction is executed parallel to the IDLE instruction When IVA2 is ready to go to off mode there are two ways to completely shut...

Page 799: ...ode MPU IVA2 power off auto mode MPU or IVA2 IVA2 is in off mode IVA2 will be put in off mode when IDLE instruction is executed iva2 046 Public Version www ti com IVA2 2 Subsystem Basic Programming Model Figure 5 35 IVA2 Power Down CAUTION The IVA2 clock must not be stopped manually otherwise the WUGEN module inside the IVA2 has no functional clock and cannot wake up the IVA subsystem When the IVA...

Page 800: ...ache SRAM is the only memory cache that supports this off mode while DSP is active L1D and L1P cache SRAM off modes are not supported while DSP is active The sequence to enter L2 off mode while DSP is active follows 1 Save L2CFG and disable the L2 by converting L2 cache SRAM to memory mapped SRAM only 96KB L2CFG L2MODE 0x0 2 Read back L2CFG to ensure that Step 1 is complete 3 Save L2MPPAj j 0 to 3...

Page 801: ...E_SYSCONFIG AutoIdle 1 IVA iLF_SYSCONFIG AutoIdle 1 IVA SEQ_SYSCONFIG AutoIdle 1 IVA VIDEOSYSC_SYSCONFIG AutoIdle 1 IVA iVLCD_SYSCONFIG AutoIdle 1 5 4 10 5 2 System Dynamic Power Savings For further system dynamic power savings a module root clock can be independently stopped when the module has no activity The root clock of a module can be stopped by writing 0 in the bit associated with that modu...

Page 802: ...USERR 10 8 XID and IVA_IDMA IBUSERR 2 0 STAT fields are updated accordingly An error signaled through a non 0 read status is detected on the read data status interface or a non 0 write status on the write status interface Alternately the EMC records an error if a read or write status response is detected for an unrecognized write ID NOTE The user must ensure that the EMC detects stores error infor...

Page 803: ... TPTCj_ERRSTAT 0 BUSERR bit is set If both read and write status are nonzero the write status is given priority for setting the TPTCj_ERRDET register The TPTCj_ERRDET register is cleared by writing 1 to the TPTCj_ERRCLR 0 BUSERR bit If an error is enabled by the TPTCj_ERREN register bits the first occurrence of an enabled error generates a pulsed interrupt to the CPU by the TCERRINT event output T...

Page 804: ...01C0 0000 64K bytes TPTC0 0x01C1 0000 1K byte TPTC1 0x01C1 0400 1K byte SYSC 0x01C2 0000 4K bytes WUGEN 0x01C2 1000 4K bytes iVLCD 1 0x0008 0000 8K bytes SEQ 1 0x0009 0000 2K bytes VIDEOSYSC 1 0x0009 C000 4K bytes iME 1 0x000A 0000 4K bytes iLF 1 0x000A 1000 4K bytes IA_GEM 0x000F 8800 1K bytes IA_EDMA 0x000F 8C00 1K bytes IA_SEQ 0x000F 9000 1K bytes 1 These modules are accessible through DSP EFI ...

Page 805: ...2 0x0000 01C0 0x0180 01C0 1 i 0 to 3 2 j 1 to 3 5 5 1 2 IC Register Descriptions Table 5 24 EVTFLAGi Address Offset 0x0000 0x4 i Physical address 0x0180 0000 0x4 i Instance IVA2 2 GEMIC Description Event Flag Register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EF Bits Field Name Description Type Reset 31 0 EF Event Flag status R 0 0 No event occurr...

Page 806: ...C Register Mapping Summary 1 Table 5 28 EVTCLRi Address Offset 0x0040 0x4 i Physical address 0x0180 0040 0x4 i Instance IVA2 2 GEMIC Description Event Clear Register Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EC Bits Field Name Description Type Reset 31 0 EC Event Clear W 0 Write 0 No action Write 1 Clear corresponding event flag Table 5 29 Registe...

Page 807: ...ng Model for Power Down of IVA2 2 Subsystem 10 Interrupt Controller Basic Programming Model for Power On of IVA2 2 Subsystem 11 12 13 14 15 IVA2 2 Subsystem Register Manual IC Register Mapping Summary 16 Table 5 32 MEVTFLAGi Address Offset 0x00A0 0x4 i Physical address 0x0180 00A0 0x4 i Instance IVA2 2 GEMIC Description Masked Event Flag Register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 808: ... address 0x0180 00E0 0x4 i Instance IVA2 2 GEMIC Description Masked Exception Flag Register 0 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MXF Bits Field Name Description Type Reset 31 0 MXF Masked Exception Flag R 0 0 No unmasked exception occurred 1 An unmasked exception occurred Table 5 37 Register Call Summary for Register MEXPFLAGi IVA2 2 Subsys...

Page 809: ... Mapping Programming Sequence 2 Interrupt Controller Basic Programming Model for Power Down of IVA2 2 Subsystem 3 Interrupt Controller Basic Programming Model for Power On of IVA2 2 Subsystem 4 5 6 7 8 9 IVA2 2 Subsystem Register Manual IC Register Mapping Summary 10 Table 5 40 INTXSTAT Address Offset 0x0000 0180 Physical address 0x0180 0180 Instance IVA2 2 GEMIC Description Interrupt Exception St...

Page 810: ...xception Programming Sequence 0 1 IVA2 2 Subsystem Register Manual IC Register Mapping Summary 2 Table 5 44 INTDMASK Address Offset 0x0000 0188 Physical address 0x0180 0188 Instance IVA2 2 GEMIC Description Dropped Interrupt Mask Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved IDM9 IDM8 IDM7 IDM6 IDM5 IDM4 IDM15 IDM14 IDM13 I...

Page 811: ...25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MXF7 MXF6 MXF5 MXF4 MXF3 MXF2 MXF1 MXF0 Bits Field Name Description Type Reset 31 8 Reserved write 0 for future compatibility W 0 7 MXF7 Event Assert output 7 W 0 EA7 0 No effect EA7 1 EVTOUT7 pulsed high for 4 clk1 cycles then low 6 MXF6 Event Assert output 6 W 0 EA6 0 No effect EA6 1 EVTOUT6 pulsed high for 4 clk1 cycle...

Page 812: ...al www ti com Table 5 47 Register Call Summary for Register EVTASRT IVA2 2 Subsystem Register Manual IC Register Mapping Summary 0 812 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 813: ...0 GEMPD 0 Normal operation Do not power down CPU or DSP megamodule when CPU is IDLE GEMPD 1 Sleep mode Power down CPU and DSP megamodule when CPU enters IDLE state 15 14 EMCMEM SRAM Sleep Modes RW 0x1 Determines the RAM sleep modes used by the EMC for powering down internal memories 0x0 No sleep mode supported 0x1 Sleep mode 1 Write 0x2 Sleep mode 2 equivalent to sleep mode 1 Write 0x3 Sleep mode ...

Page 814: ...sregions when DSP megamodule is active pmc_pd_pdstat 1 0 00 and Static clock gating when DSP megamodule is in standby pmc_pd_pdstat 1 0 11 3 2 PMCMEM SRAM Sleep Modes RW 0x1 Determines the RAM sleep modes used by the PMC for powering down L1P pages 0x0 No sleep mode supported 0x1 Sleep mode 1 Write 0x2 Sleep mode 2 equivalent to sleep mode 1 Write 0x3 Sleep mode 3 equivalent to sleep mode 1 1 0 PM...

Page 815: ...2 11 10 9 8 7 6 5 4 3 2 1 0 VERSION REVISION Bits Field Name Description Type Reset 31 16 VERSION Functional implementation of DSP megamodule R 0x0002 0x0002 MidGEM 15 0 REVISION Physical implementation of DSP megamodule version R 0x0000 Table 5 52 Register Call Summary for Register REVID IVA2 2 Subsystem Register Manual SYS Register Mapping Summary 0 815 SWPU177N December 2009 Revised November 20...

Page 816: ...MAARBE RW 32 0x0000 0208 0x0182 0208 MDMAARBE RW 32 0x0000 020C 0x0182 020C ICFGMPFAR R 32 0x0000 0300 0x0182 0300 ICFGMPFSR R 32 0x0000 0304 0x0182 0304 ICFGMPFCR W 32 0x0000 0308 0x0182 0308 IBUSERR R 32 0x0000 0400 0x0182 0400 IBUSERRCLR W 32 0x0000 0404 0x0182 0404 5 5 3 2 IDMA Register Descriptions Table 5 54 IDMA0_STAT Address Offset 0x0000 0000 Physical address 0x0182 0000 Instance IVA2 2 G...

Page 817: ...not masked 29 M29 Register Mask bit RW 0 M29 1 Register access blocked masked M29 0 Register access permitted not masked 28 M28 Register Mask bit RW 0 M28 1 Register access blocked masked M28 0 Register access permitted not masked 27 M27 Register Mask bit RW 0 M27 1 Register access blocked masked M27 0 Register access permitted not masked 26 M26 Register Mask bit RW 0 M26 1 Register access blocked...

Page 818: ...d 10 M10 Register Mask bit RW 0 M10 1 Register access blocked masked M10 0 Register access permitted not masked 9 M9 Register Mask bit RW 0 M9 1 Register access blocked masked M9 0 Register access permitted not masked 8 M8 Register Mask bit RW 0 M8 1 Register access blocked masked M8 0 Register access permitted not masked 7 M7 Register Mask bit RW 0 M7 1 Register access blocked masked M7 0 Registe...

Page 819: ... Summary for Register IDMA0_SOURCE IVA2 2 Subsystem Basic Programming Model Starting the Transfer 0 IVA2 2 Subsystem Register Manual IDMA Register Mapping Summary 1 Table 5 60 IDMA0_DEST Address Offset 0x0000 000C Physical address 0x0182 000C Instance IVA2 2 GEMIDMA Description IDMA Channel 0 Destination Address Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 820: ...ster Manual IDMA Register Mapping Summary 1 Table 5 64 IDMA1_STAT Address Offset 0x0000 0100 Physical address 0x0182 0100 Instance IVA2 2 GEMIDMA Description IDMA Channel 1 Status Register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ACTV PEND Bits Field Name Description Type Reset 31 2 Reserved Write 0s for future compatibility R 0x00000000...

Page 821: ...A2 2 Subsystem Basic Programming Model Internal Memory to Memory Transfer IDMA 0 1 2 3 IVA2 2 Subsystem Register Manual IDMA Register Mapping Summary 4 Table 5 68 IDMA1_DEST Address Offset 0x0000 010C Physical address 0x0182 010C Instance IVA2 2 GEMIDMA Description IDMA Channel 1 Destination Address Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 822: ...d to by the Destination address field FILL 0 Block transfer from the source address to the destination address 15 2 COUNT 16 bit byte count Must be a multiple of 4 bytes A transfer count of RW 0x0000 zero will not transfer any data but will generate an interrupt if requested in the INT field 1 0 Reserved Write 0s for future compatibility RW 0x0 Read returns 0 Table 5 71 Register Call Summary for R...

Page 823: ...s Table 5 73 Register Call Summary for Register CPUARBE IVA2 2 Subsystem Basic Programming Model Internal Memory 0 IVA2 2 Subsystem Register Manual IDMA Register Mapping Summary 1 Table 5 74 IDMAARBE Address Offset 0x0000 0204 Physical address 0x0182 0204 Instance IVA2 2 GEMIDMA Description IDMA Arbitration control Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 824: ...s 1 3 33 access 0x4 Maximum wait of 4 cycles 1 5 20 access 0x8 Maximum wait of 8 cycles 1 9 11 access 0x10 Maximum wait of 16 cycles 1 17 6 access 0x20 Maximum wait of 32 cycles 1 33 3 access Table 5 77 Register Call Summary for Register SDMAARBE IVA2 2 Subsystem Basic Programming Model Internal Memory 0 IVA2 2 Subsystem Register Manual IDMA Register Mapping Summary 1 Table 5 78 MDMAARBE Address O...

Page 825: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Bits Field Name Description Type Reset 31 0 ADDR Fault Address R 0x00000000 Table 5 81 Register Call Summary for Register ICFGMPFAR IVA2 2 Subsystem Basic Programming Model Internal Memory 0 IVA2 2 Subsystem Register Manual IDMA Register Mapping Summary 1 Table 5 82 ICFGMPFSR Address Offset 0x0000 0304 Physical address 0x0182 0304 Instance IVA2 2 GEMIDMA D...

Page 826: ...0s for future compatibility W Read returns 0 0 MPFCLR Write 0 No effect W 0 Write 1 Clear fault logged information Table 5 85 Register Call Summary for Register ICFGMPFCR IVA2 2 Subsystem Basic Programming Model Internal Memory 0 IVA2 2 Subsystem Register Manual IDMA Register Mapping Summary 1 Table 5 86 IBUSERR Address Offset 0x0000 0400 Physical address 0x0182 0400 Instance IVA2 2 GEMIDMA Descri...

Page 827: ...ogramming Model Error Reporting for IDMA Module 0 1 2 3 4 5 6 IVA2 2 Subsystem Register Manual IDMA Register Mapping Summary 7 Table 5 88 IBUSERRCLR Address Offset 0x0000 0404 Physical address 0x0182 0404 Instance IVA2 2 GEMIDMA Description Bus Access Error Clear Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CLR Bits Field Name Description Ty...

Page 828: ...0x0000 104C 0x0184 104C L2WBAR W 32 0x0000 4000 0x0184 4000 L2WWC RW 32 0x0000 4004 0x0184 4004 L2WIBAR W 32 0x0000 4010 0x0184 4010 L2WIWC RW 32 0x0000 4014 0x0184 4014 L2IBAR W 32 0x0000 4018 0x0184 4018 L2IWC RW 32 0x0000 401C 0x0184 401C L1PIBAR W 32 0x0000 4020 0x0184 4020 L1PIWC RW 32 0x0000 4024 0x0184 4024 L1DWIBAR W 32 0x0000 4030 0x0184 4030 L1DWIWC RW 32 0x0000 4034 0x0184 4034 L1DWBAR ...

Page 829: ...ure compatibility Read returns 0 R 0x0 27 24 NUM_MM Number of megamodules 1 always 0 for IVA2 R 0x0 23 20 Reserved Write 0s for future compatibility Read returns 0 R 0x0 19 16 MMID Megamodule ID always 0x0 for IVA2 R 0x0 15 11 Reserved Write 0s for future compatibility Read returns 0 W 0x00 10 NOINIT No init upon cache config when written 1 cache config is restored W 0 without re initializing cach...

Page 830: ... 4KB of L1P Cache 0x2 8KB of L1P Cache 0x3 16KB of L1P Cache 0x4 Maximum cache 32KB of L1P Cache Table 5 94 Register Call Summary for Register L1PCFG IVA2 2 Subsystem Basic Programming Model IVA2 2 Boot Configuration 0 1 2 3 Cache Size Configuration 4 5 6 7 8 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 9 Table 5 95 L1PCC Address Offset 0x0000 0024 Physical address 0x0184 0024 Ins...

Page 831: ...Reset 31 3 Reserved Write 0s for future compatibility Read returns 0 RW 0x00000000 2 0 L1DMODE L1D Configuration Register RW 0x0 0x0 0KB of L1D Cache 0x1 4KB of L1D Cache 0x2 8KB of L1D Cache 0x3 16KB of L1D Cache 0x4 32KB of L1D Cache 0x5 Not used 0x6 Not used 0x7 Maximum cache maps to 32KB of L1D Cache Table 5 98 Register Call Summary for Register L1DCFG IVA2 2 Subsystem Basic Programming Model ...

Page 832: ... 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PRI Reserved MAXWAIT Bits Field Name Description Type Reset 31 19 Reserved Write 0s for future compatibility Read returns 0 RW 0x0000 18 16 PRI Priority RW 0x1 0x0 Highest priority 0x1 2nd highest priority 0x2 3rd highest priority 0x3 4th highest priority 0x4 5th highest priority 0x5 6th highest priority 0x6 7th highest pri...

Page 833: ... of 8 cycles 1 9 11 access 0x10 Maximum wait of 16 cycles 1 17 6 access 0x20 Maximum wait of 32 cycles 1 33 3 access Table 5 104 Register Call Summary for Register IDMAARBU IVA2 2 Subsystem Basic Programming Model Internal Memory 0 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 1 Table 5 105 SDMAARBU Address Offset 0x0000 1008 Physical address 0x0184 1008 Instance IVA2 2 GEMXMC Desc...

Page 834: ...her priority requestor 0x1 Maximum wait of 1 cycles 1 2 50 access 0x2 Maximum wait of 2 cycles 1 3 33 access 0x4 Maximum wait of 4 cycles 1 5 20 access 0x8 Maximum wait of 8 cycles 1 9 11 access 0x10 Maximum wait of 16 cycles 1 17 6 access 0x20 Maximum wait of 32 cycles 1 33 3 access Table 5 108 Register Call Summary for Register UCARBU IVA2 2 Subsystem Basic Programming Model Internal Memory 0 IV...

Page 835: ...ster Manual XMC Register Mapping Summary 1 Table 5 111 IDMAARBD Address Offset 0x0000 1044 Physical address 0x0184 1044 Instance IVA2 2 GEMXMC Description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MAXWAIT Bits Field Name Description Type Reset 31 6 Reserved Write 0s for future compatibility Read returns 0 RW 0x0000000 5 0 MAXWAIT Maximum...

Page 836: ...gister Call Summary for Register SDMAARBD IVA2 2 Subsystem Basic Programming Model Internal Memory 0 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 1 Table 5 115 UCARBD Address Offset 0x0000 104C Physical address 0x0184 104C Instance IVA2 2 GEMXMC Description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MAXWAIT Bits Field Nam...

Page 837: ...A2 2 Subsystem Basic Programming Model Coherence Maintenance 0 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 1 Table 5 119 L2WWC Address Offset 0x0000 4004 Physical address 0x0184 4004 Instance IVA2 2 GEMXMC Description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WC Bits Field Name Description Type Reset 31 16 Reserved Writ...

Page 838: ...4 4014 Instance IVA2 2 GEMXMC Description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WC Bits Field Name Description Type Reset 31 16 Reserved Write 0s for future compatibility Read returns 0 RW 0x0000 15 0 WC Number of 32 bit words in the block RW 0x0000 Table 5 124 Register Call Summary for Register L2WIWC IVA2 2 Subsystem Basic Programm...

Page 839: ...00 Table 5 128 Register Call Summary for Register L2IWC IVA2 2 Subsystem Basic Programming Model Coherence Maintenance 0 1 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 2 Table 5 129 L1PIBAR Address Offset 0x0000 4020 Physical address 0x0184 4020 Instance IVA2 2 GEMXMC Description L1P Block Invalidate Base Address Register Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 840: ...ping Summary 1 Table 5 133 L1DWIBAR Address Offset 0x0000 4030 Physical address 0x0184 4030 Instance IVA2 2 GEMXMC Description Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Bits Field Name Description Type Reset 31 0 ADDR Block base address W 0x Table 5 134 Register Call Summary for Register L1DWIBAR IVA2 2 Subsystem Basic Programming Model Coher...

Page 841: ... base address W 0x Table 5 138 Register Call Summary for Register L1DWBAR IVA2 2 Subsystem Basic Programming Model Coherence Maintenance 0 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 1 Table 5 139 L1DWWC Address Offset 0x0000 4044 Physical address 0x0184 4044 Instance IVA2 2 GEMXMC Description L1D Block Writeback Word Count Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 842: ...2 GEMXMC Description L1D Block Invalidate Word Count Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WC Bits Field Name Description Type Reset 31 16 Reserved Write 0s for future compatibility Read returns 0 RW 0x0000 15 0 WC Number of 32 bit words in the block RW 0x0000 Table 5 144 Register Call Summary for Register L1DIWC IVA2 2 Subsystem Bas...

Page 843: ...5004 Instance IVA2 2 GEMXMC Description L2 global writeback invalidate Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved C Bits Field Name Description Type Reset 31 1 Reserved Write 0s for future compatibility Read returns 0 RW 0x 0 C L2 global write back invalidate command RW 0 Write 0 No effect Write 1 Initiates an L2 global write back invalid...

Page 844: ...y for Register L2INV IVA2 2 Subsystem Basic Programming Model Coherence Maintenance 0 1 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 2 Table 5 151 L1PINV Address Offset 0x0000 5028 Physical address 0x0184 5028 Instance IVA2 2 GEMXMC Description L1P Global Invalidate Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I Bits Field ...

Page 845: ...er Manual XMC Register Mapping Summary 1 Table 5 155 L1DWBINV Address Offset 0x0000 5044 Physical address 0x0184 5044 Instance IVA2 2 GEMXMC Description L1D Global Writeback Invalidate Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved C Bits Field Name Description Type Reset 31 1 Reserved Write 0s for future compatibility Read returns 0 RW 0x 0 ...

Page 846: ...Register Mapping Summary 1 Table 5 159 MARi Address Offset 0x8000 0x4 i Physical address 0x0184 8000 0x4 i Instance IVA2 2 GEMXMC Description Memory Attribute Register i 0 defines the cacheable memory attribute for Local L2 RAM fixed i 1 to 255 define a cachable memory attribute for 0x0100 0000 memory range starting at 0x0100 0000 Type RW R for i 0 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 847: ...et 0x0000 A004 Physical address 0x0184 A004 Instance IVA2 2 GEMXMC Description Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FLTID ATYP Reserved Bits Field Name Description Type Reset 31 16 Reserved Write 0s for future compatibility Read returns 0 R 0x0000 15 8 FLTID Faulted ID R 0x00 VBUS PrivID of faulting requestor This field is valid only...

Page 848: ...W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SX SR UX UR SW UW AID5 AID4 AID3 AID2 AID1 AID0 AIDX LOCAL Reserved Bits Field Name Description Type Reset 31 16 Reserved Write 0s for future compatibility Read returns 0 RW 0x0000 15 AID5 0 ID 5 does not have access permission RW 1 1 ID 5 has access permission 14 AID4 0 ID 4 does not have access permi...

Page 849: ...4 Powering Down L2 Memory While IVA2 is Active 5 6 7 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 8 Table 5 169 L1PMPFAR Address Offset 0x0000 A400 Physical address 0x0184 A400 Instance IVA2 2 GEMXMC Description PMC Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Bits Field Name Description Type Reset 31 0 ADDR Fault Address R 0x00...

Page 850: ...r Call Summary for Register L1PMPFSR IVA2 2 Subsystem Basic Programming Model Internal Memory 0 IVA2 2 Subsystem Register Manual XMC Register Mapping Summary 1 Table 5 173 L1PMPFCR Address Offset 0x0000 A408 Physical address 0x0184 A408 Instance IVA2 2 GEMXMC Description PMC Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MPFCLR Bits Field Name...

Page 851: ...ssion 10 AID0 0 ID 0 does not have access permission RW 1 1 ID 0 has access permission 9 AIDX 0 External access is not permitted RW 1 1 External access is permitted 8 LOCAL 0 DSP megamodule access is not permitted RW 1 1 DSP megamodule access is permitted 7 6 Reserved Write 0s for future compatibility RW 0 Read returns 0 5 SR 0 Supervisor Read access is not permitted RW 1 1 Supervisor Read access ...

Page 852: ...1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FLTID ATYP Reserved Bits Field Name Description Type Reset 31 16 Reserved Write 0s for future compatibility Read returns 0 R 0x0000 15 8 FLTID Faulted ID R 0x00 VBUS PrivID of faulting requestor This field is valid only if LE is zero 7 6 Reserved Write 0s for future compatibility Read returns 0 R 0x0 5 0 ATYP Access type R 0x00 Read 0...

Page 853: ...age number i Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SR UR SW UW AID5 AID4 AID3 AID2 AID1 AID0 AIDX LOCAL Reserved Reserved Reserved Bits Field Name Description Type Reset 31 16 Reserved Write 0s for future compatibility Read returns 0 RW 0x0000 15 AID5 0 ID 5 does not have access permission RW 1 1 ID 5 has access permission 14 AID4 0 ...

Page 854: ...module is described separately below 5 5 5 1 TPCC Register Mapping Summary Table 5 185 TPCC Register Summary Register Name Type Register Address Offset Physical Address Width Bits TPCC_PID R 32 0x0000 0x01C0 0000 TPCC_CCCFG R 32 0x0004 0x01C0 0004 TPCC_DCHMAPi 1 RW 32 0x0100 0x4 i 0x01C0 0100 0x4 i TPCC_QCHMAPj 2 RW 32 0x0200 0x4 j 0x01C0 0200 0x4 j TPCC_DMAQNUM0 RW 32 0x0240 0x01C0 0240 TPCC_DMAQ...

Page 855: ...0810 0x4 j TPCC_ER R 32 0x1000 0x01C0 1000 TPCC_ECR W 32 0x1008 0x01C0 1008 TPCC_ECRH W 32 0x100C 0x01C0 100C TPCC_ESR W 32 0x1010 0x01C0 1010 TPCC_ESRH W 32 0x1014 0x01C0 1014 TPCC_CER R 32 0x1018 0x01C0 1018 TPCC_CERH R 32 0x101C 0x01C0 101C TPCC_EER R 32 0x1020 0x01C0 1020 TPCC_EECR W 32 0x1028 0x01C0 1028 TPCC_EESR W 32 0x1030 0x01C0 1030 TPCC_SER R 32 0x1038 0x01C0 1038 TPCC_SERH R 32 0x103C ...

Page 856: ...CC_IECR_Rn 7 W 32 0x2058 0x200 n 0x01C0 2058 0x200 n TPCC_IECRH_Rn 7 W 32 0x205C 0x200 n 0x01C0 205C 0x200 n TPCC_IESR_Rn 7 W 32 0x2060 0x200 n 0x01C0 2060 0x200 n TPCC_IESRH_Rn 7 W 32 0x2064 0x200 n 0x01C0 2064 0x200 n TPCC_IPR_Rn 7 R 32 0x2068 0x200 n 0x01C0 2068 0x200 n TPCC_IPRH_Rn 7 R 32 0x206C 0x200 n 0x01C0 206C 0x200 n TPCC_ICR_Rn 7 W 32 0x2070 0x200 n 0x01C0 2070 0x200 n TPCC_ICRH_Rn 7 W ...

Page 857: ...n of EDMA R 0x0 5 0 MINOR Minor revision R 0x Table 5 187 Register Call Summary for Register TPCC_PID IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 188 TPCC_CCCFG Address Offset 0x0004 Physical address 0x01C0 0004 Instance IVA2 2 TPCC Description CC Configuration Register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserve...

Page 858: ...0x4 256 entries Read 0x5 512 entries 11 Reserved Read returns 0 R 0 10 8 NUMINTCH Number of Interrupt Channels R 0x4 Read 0x1 8 Interrupt channels Read 0x2 16 Interrupt channels Read 0x3 32 Interrupt channels Read 0x4 64 Interrupt channels 7 Reserved Read returns 0 R 0 6 4 NUMQDMACH Number of QDMA Channels R 0x2 Read 0x0 No QDMA Channels Read 0x1 2 QDMA Channels Read 0x2 4 QDMA Channels Read 0x3 6...

Page 859: ...ping Summary 5 Table 5 192 TPCC_QCHMAPj Address Offset 0x0200 0x4 j Physical address 0x01C0 0200 0x4 j Instance IVA2 2 TPCC Description QDMA Channel i Mapping Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PAENTRY TRWORD Reserved Bits Field Name Description Type Reset 31 14 Reserved Write 0s for future compatibility RW 0x00000 Read r...

Page 860: ... Write 0s for future compatibility RW 0 Read returns 0 26 24 E6 DMA Queue Number for event 6 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 23 Reserved Write 0s for future compatibility RW 0 Read returns 0 22 20 E5 DMA Queue Number for event 5 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 19 Rese...

Page 861: ...nstance IVA2 2 TPCC Description DMA Queue Number Register 1 Contains the Event queue number to be used for the corresponding DMA Channel Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bits Field Name Description Type Reset 31 Reserved Write 0s for fut...

Page 862: ...ueue Number for event 9 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 3 Reserved Write 0s for future compatibility RW 0 Read returns 0 2 0 E8 DMA Queue Number for event 8 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 Table 5 197 Register Call Summary for Register TPCC_DMAQNUM1 IVA2 2 Subsystem B...

Page 863: ...0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 15 Reserved Write 0s for future compatibility RW 0 Read returns 0 14 12 E19 DMA Queue Number for event 19 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 11 Reserved Write 0s for future compatibility RW 0 Read returns 0 10 8 E18 DMA Queue Number for event...

Page 864: ...e compatibility RW 0 Read returns 0 26 24 E30 DMA Queue Number for event 30 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 23 Reserved Write 0s for future compatibility RW 0 Read returns 0 22 20 E29 DMA Queue Number for event 29 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 19 Reserved Write 0s f...

Page 865: ...esponding DMA Channel Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E39 E38 E37 E36 E35 E34 E33 E32 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bits Field Name Description Type Reset 31 Reserved Write 0s for future compatibility RW 0 Read returns 0 30 28 E39 DMA Queue Number for event 39 RW 0x0 0x0 Event En is queued on Q0...

Page 866: ...2 2 3 Reserved Write 0s for future compatibility RW 0 Read returns 0 2 0 E32 DMA Queue Number for event 32 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 Table 5 203 Register Call Summary for Register TPCC_DMAQNUM4 IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 204 TPCC_DMAQNUM5 Address Offset 0x0254 Physical address 0x01...

Page 867: ...bility RW 0 Read returns 0 14 12 E43 DMA Queue Number for event 43 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 11 Reserved Write 0s for future compatibility RW 0 Read returns 0 10 8 E42 DMA Queue Number for event 42 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 7 Reserved Write 0s for future c...

Page 868: ... on Q1 Others Not applicable for IVA2 2 23 Reserved Write 0s for future compatibility RW 0 Read returns 0 22 20 E53 DMA Queue Number for event 53 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 19 Reserved Write 0s for future compatibility RW 0 Read returns 0 18 16 E52 DMA Queue Number for event 52 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En i...

Page 869: ...E61 E60 E59 E58 E57 E56 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bits Field Name Description Type Reset 31 Reserved Write 0s for future compatibility RW 0 Read returns 0 30 28 E63 DMA Queue Number for event 63 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 27 Reserved Write 0s for future compatibility RW 0 Read retur...

Page 870: ...0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 Table 5 209 Register Call Summary for Register TPCC_DMAQNUM7 IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 210 TPCC_QDMAQNUM Address Offset 0x0260 Physical address 0x01C0 0260 Instance IVA2 2 TPCC Description QDMA Queue Number Register Contains the Event queue number to be used f...

Page 871: ... 3 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 11 Reserved Write 0s for future compatibility RW 0 Read returns 0 10 8 E2 QDMA Queue Number for event 2 RW 0x0 0x0 Event En is queued on Q0 0x1 Event En is queued on Q1 Others Not applicable for IVA2 2 7 Reserved Write 0s for future compatibility RW 0 Read returns 0 6 4 E1 QDMA Queue Number for eve...

Page 872: ...en to 0x0 TRs from this queue are routed to TPTC0 0x1 TRs from this queue are routed to TPTC1 Others Not applicable for IVA2 2 Table 5 213 Register Call Summary for Register TPCC_QUETCMAP IVA2 2 Subsystem Basic Programming Model Prioritizing Defined Transfers 0 IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 1 Table 5 214 TPCC_QUEPRI Address Offset 0x0284 Physical address 0x01C0 028...

Page 873: ... address 0x01C0 0300 Instance IVA2 2 TPCC Description Event Missed Register The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced Chained events CER Set Events ESR and normal events ER are treated individually If any bit in the EMR register is set and all errors including QEMR CCERR were previously clear then an error will be si...

Page 874: ...ng Summary 1 Table 5 218 TPCC_EMRH Address Offset 0x0304 Physical address 0x01C0 0304 Instance IVA2 2 TPCC Description Event Missed Register High Part The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced Chained events CER Set Events ESR and normal events ER are treated individually If any bit in the EMR register is set and all...

Page 875: ... 32 R 0 Table 5 219 Register Call Summary for Register TPCC_EMRH IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 220 TPCC_EMCR Address Offset 0x0308 Physical address 0x01C0 0308 Instance IVA2 2 TPCC Description Event Missed Clear Register CPU write of 1 to the EMCR En bit causes the EMR En bit to be cleared CPU write of 0 has no effect All error bits must be cleared before...

Page 876: ...ar 3 W 0 2 E2 Event Missed Clear 2 W 0 1 E1 Event Missed Clear 1 W 0 0 E0 Event Missed Clear 0 W 0 Table 5 221 Register Call Summary for Register TPCC_EMCR IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 222 TPCC_EMCRH Address Offset 0x030C Physical address 0x01C0 030C Instance IVA2 2 TPCC Description Event Missed Clear Register High Part CPU write of 1 to the EMCR En bit ...

Page 877: ...nt Missed Clear 36 W 0 3 E35 Event Missed Clear 35 W 0 2 E34 Event Missed Clear 34 W 0 1 E33 Event Missed Clear 33 W 0 0 E32 Event Missed Clear 32 W 0 Table 5 223 Register Call Summary for Register TPCC_EMCRH IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 224 TPCC_QEMR Address Offset 0x0310 Physical address 0x01C0 0310 Instance IVA2 2 TPCC Description QDMA Event Missed Re...

Page 878: ...t to be cleared CPU write of 0 has no effect All error bits must be cleared before additional error interrupts will be asserted by CC Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 Bits Field Name Description Type Reset 31 8 Reserved Write 0s for future compatibility W 0x000000 7 E7 Event Missed Clear 7 W 0 6 E6 Event M...

Page 879: ...g 1 to corresponding bit in CCERRCLR register If any bit in the CCERR register is set and all errors including EMR QEMR were previously clear then an error will be signaled with the TPCC error interrupt 0 QTHRXCD0 Queue Threshold Error for Q0 R 0 QTHRXCD0 0 Watermark threshold has not been exceeded QTHRXCD0 1 Watermark threshold has been exceeded CCERR QTHRXCD0 can be cleared by writing 1 to corre...

Page 880: ...dress 0x01C0 0320 Instance IVA2 2 TPCC Description Error Eval Register Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SET EVAL Bits Field Name Description Type Reset 31 2 Reserved Write 0s for future compatibility W 0x00000000 1 SET Error Interrupt Set W 0 CPU write of 1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of...

Page 881: ... E25 DMA Region Access enable for Region i bit 25 RW 0 24 E24 DMA Region Access enable for Region i bit 24 RW 0 23 E23 DMA Region Access enable for Region i bit 23 RW 0 22 E22 DMA Region Access enable for Region i bit 22 RW 0 21 E21 DMA Region Access enable for Region i bit 21 RW 0 20 E20 DMA Region Access enable for Region i bit 20 RW 0 19 E19 DMA Region Access enable for Region i bit 19 RW 0 18 ...

Page 882: ... for Region i bit 59 RW 0 26 E58 DMA Region Access enable for Region i bit 58 RW 0 25 E57 DMA Region Access enable for Region i bit 57 RW 0 24 E56 DMA Region Access enable for Region i bit 56 RW 0 23 E55 DMA Region Access enable for Region i bit 55 RW 0 22 E54 DMA Region Access enable for Region i bit 54 RW 0 21 E53 DMA Region Access enable for Region i bit 53 RW 0 20 E52 DMA Region Access enable ...

Page 883: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 Bits Field Name Description Type Reset 31 8 Reserved Write 0s for future compatibility RW 0x000000 Read returns 0 7 E7 QDMA Region Access enable for Region i bit 7 RW 0 6 E6 QDMA Region Access enable for Region i bit 6 RW 0 5 E5 QDMA Region Access enable for Region i bit 5 RW 0 4 E4 QD...

Page 884: ...0 0x4 k Instance IVA2 2 TPCC Description Event Queue Entry Diagram for Queue j Entry i j 0 to1 and i 0 to 15 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENUM ETYPE Bits Field Name Description Type Reset 31 8 Reserved Read returns 0 R 0x000000 7 6 ETYPE Event Type R 0x Specifies the specific Event Type for the given entry in the Event Queue ...

Page 885: ...k tracks the most entries that have been in QueueN since reset or since the last time that the watermark WM was cleared QSTATn WM is cleared through CCERR WMCLRn bit Legal values 0x0 empty to 0x10 full 15 13 Reserved Read returns 0 R 0x0 12 8 NUMVAL Number of Valid Entries in Queuei R 0x00 Represents the total number of entries residing in the Queue Manager FIFO at a given instant Always enabled L...

Page 886: ...for Register TPCC_QWMTHRA IVA2 2 Subsystem Basic Programming Model Starting the Transfer 0 IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 1 Table 5 248 TPCC_QWMTHRB Address Offset 0x0624 Physical address 0x01C0 0624 Instance IVA2 2 TPCC Description Queue Threshold B for Q 7 4 CCERR QTHRXCDn and QSTATn THRXCD error bit is set when the number of Events in QueueN at an instant in time...

Page 887: ...s are queued in Q2 QUEACTV2 1 At least one TR is queued in Q2 17 QUEACTV1 Queue 1 Active R 0 QUEACTV1 0 No Evts are queued in Q1 QUEACTV1 1 At least one TR is queued in Q1 16 QUEACTV0 Queue 0 Active R 0 QUEACTV0 0 No Evts are queued in Q0 QUEACTV0 1 At least one TR is queued in Q0 15 14 Reserved Read returns 0 R 0x0 13 8 COMPACTV Completion Request Active R 0x00 Counter that tracks the total numbe...

Page 888: ...C0 0800 Instance IVA2 2 TPCC Description Memory Protection Fault Address Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FADDR Bits Field Name Description Type Reset 31 0 FADDR Fault Address R 0x00000000 32 bit read only status register containing the faulting address when a memory protection violation is detected This register can only be cleared throu...

Page 889: ...d to Read from a MP Page without UR permissions 1 UWE User Write Error R 0 UWE 0 No error detected UWE 1 User level task attempted to Write to a MP Page without UW permissions 0 UXE User Execute Error R 0 UXE 0 No error detected UXE 1 User level task attempted to Execute from a MP Page without UX permissions Table 5 255 Register Call Summary for Register TPCC_MPFSR IVA2 2 Subsystem Basic Programmi...

Page 890: ...gs UW UR SW SR 13 AID3 Allowed ID 3 RW 1 AID3 0 VBus requests with PrivID 3 are notallowed regardless of permission settings UW UR SW SR AID3 1 VBus requests with PrivID 3 are permitted if access type is allowed as defined by permission settings UW UR SW SR 12 AID2 Allowed ID 2 RW 1 AID2 0 VBus requests with PrivID 2 are notallowed regardless of permission settings UW UR SW SR AID2 1 VBus requests...

Page 891: ...mary 3 Table 5 260 TPCC_MPPAj Address Offset 0x0810 0x4 j Physical address 0x01C0 0810 0x4 j Instance IVA2 2 TPCC Description MP Permission Attribute for DMA Region n Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved SX SR UX UR SW UW EXT AID5 AID4 AID3 AID2 AID1 AID0 Bits Field Name Description Type Reset 31 16 Reserved Write 0s for fu...

Page 892: ...rmitted if access type is allowed as defined by permission settings UW UR SW SR 8 6 Reserved Write reset value for future compatibility Read returns reset value RW 0x3 5 SR Supervisor Read permission RW 1 SR 0 Supervisor read accesses are not allowed SR 1 Supervisor write accesses are allowed 4 SW Supervisor Write permission RW 1 SW 0 Supervisor write accesses are not allowed SW 1 Supervisor write...

Page 893: ...nt N can be cleared through sw by writing 1 to the ECR pseudo register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field Name Description Type Reset 31 20 Reserved Reserved R 0 19 E19 Event 19 R 0 18 E18 Event 18 R 0 17 E17 Event 17 R 0 16 E16 Event 16 R 0 15 E15 Eve...

Page 894: ... 0 28 E28 Event 28 W 0 27 E27 Event 27 W 0 26 E26 Event 26 W 0 25 E25 Event 25 W 0 24 E24 Event 24 W 0 23 E23 Event 23 W 0 22 E22 Event 22 W 0 21 E21 Event 21 W 0 20 E20 Event 20 W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W 0 15 E15 Event 15 W 0 14 E14 Event 14 W 0 13 E13 Event 13 W 0 12 E12 Event 12 W 0 11 E11 Event 11 W 0 10 E10 Event 10 W 0 9 E9 Event 9 W 0 ...

Page 895: ...W 0 28 E60 Event 60 W 0 27 E59 Event 59 W 0 26 E58 Event 58 W 0 25 E57 Event 57 W 0 24 E56 Event 56 W 0 23 E55 Event 55 W 0 22 E54 Event 54 W 0 21 E53 Event 53 W 0 20 E52 Event 52 W 0 19 E51 Event 51 W 0 18 E50 Event 50 W 0 17 E49 Event 49 W 0 16 E48 Event 48 W 0 15 E47 Event 47 W 0 14 E46 Event 46 W 0 13 E45 Event 45 W 0 12 E44 Event 44 W 0 11 E43 Event 43 W 0 10 E42 Event 42 W 0 9 E41 Event 41 W...

Page 896: ...7 Event 27 W 0 26 E26 Event 26 W 0 25 E25 Event 25 W 0 24 E24 Event 24 W 0 23 E23 Event 23 W 0 22 E22 Event 22 W 0 21 E21 Event 21 W 0 20 E20 Event 20 W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W 0 15 E15 Event 15 W 0 14 E14 Event 14 W 0 13 E13 Event 13 W 0 12 E12 Event 12 W 0 11 E11 Event 11 W 0 10 E10 Event 10 W 0 9 E9 Event 9 W 0 8 E8 Event 8 W 0 7 E7 Event ...

Page 897: ... E38 E37 E36 E35 E34 E33 E32 Bits Field Name Description Type Reset 31 E63 Event 63 W 0 30 E62 Event 62 W 0 29 E61 Event 61 W 0 28 E60 Event 60 W 0 27 E59 Event 59 W 0 26 E58 Event 58 W 0 25 E57 Event 57 W 0 24 E56 Event 56 W 0 23 E55 Event 55 W 0 22 E54 Event 54 W 0 21 E53 Event 53 W 0 20 E52 Event 52 W 0 19 E51 Event 51 W 0 18 E50 Event 50 W 0 17 E49 Event 49 W 0 16 E48 Event 48 W 0 15 E47 Event...

Page 898: ...he corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set CER En cannot be set or cleared through software Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field ...

Page 899: ... event is prioritized and serviced If the CERH En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set CERH En cannot be set or cleared through software Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E5...

Page 900: ... disabled no action is taken If EER En is enabled at a later point and ER En has not been cleared through SW then the event will be recognized as a valid TR Sync EER En is not directly writeable Events can be enabled through writes to EESR and can be disabled through writes to EECR register EER En 0 ER En is not enabled to trigger DMA transfers EER En 1 ER En is enabled to trigger DMA transfers Ty...

Page 901: ...auses the EER En bit to be cleared CPU write of 0 has no effect Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field Name Description Type Reset 31 20 Reserved Reserved W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W 0 15 E15 Event 15 W...

Page 902: ... E3 E2 E1 E0 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field Name Description Type Reset 31 20 Reserved Reserved W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W 0 15 E15 Event 15 W 0 14 E14 Event 14 W 0 13 E13 Event 13 W 0 12 E12 Event 12 W 0 11 E11 Event 11 W 0 10 E10 Event 10 W 0 9 E9 Event 9 W 0 8 E8 Event 8 W 0 7 E7 Event 7 W 0 6 E6 Event 6 W 0 5 E5 Event 5...

Page 903: ...Name Description Type Reset 31 E31 Event 31 R 0 30 E30 Event 30 R 0 29 E29 Event 29 R 0 28 E28 Event 28 R 0 27 E27 Event 27 R 0 26 E26 Event 26 R 0 25 E25 Event 25 R 0 24 E24 Event 24 R 0 23 E23 Event 23 R 0 22 E22 Event 22 R 0 21 E21 Event 21 R 0 20 E20 Event 20 R 0 19 E19 Event 19 R 0 18 E18 Event 18 R 0 17 E17 Event 17 R 0 16 E16 Event 16 R 0 15 E15 Event 15 R 0 14 E14 Event 14 R 0 13 E13 Event...

Page 904: ... Name Description Type Reset 31 E63 Event 63 R 0 30 E62 Event 62 R 0 29 E61 Event 61 R 0 28 E60 Event 60 R 0 27 E59 Event 59 R 0 26 E58 Event 58 R 0 25 E57 Event 57 R 0 24 E56 Event 56 R 0 23 E55 Event 55 R 0 22 E54 Event 54 R 0 21 E53 Event 53 R 0 20 E52 Event 52 R 0 19 E51 Event 51 R 0 18 E50 Event 50 R 0 17 E49 Event 49 R 0 16 E48 Event 48 R 0 15 E47 Event 47 R 0 14 E46 Event 46 R 0 13 E45 Even...

Page 905: ... W 0 30 E30 Event 30 W 0 29 E29 Event 29 W 0 28 E28 Event 28 W 0 27 E27 Event 27 W 0 26 E26 Event 26 W 0 25 E25 Event 25 W 0 24 E24 Event 24 W 0 23 E23 Event 23 W 0 22 E22 Event 22 W 0 21 E21 Event 21 W 0 20 E20 Event 20 W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W 0 15 E15 Event 15 W 0 14 E14 Event 14 W 0 13 E13 Event 13 W 0 12 E12 Event 12 W 0 11 E11 Event 11...

Page 906: ...63 W 0 30 E62 Event 62 W 0 29 E61 Event 61 W 0 28 E60 Event 60 W 0 27 E59 Event 59 W 0 26 E58 Event 58 W 0 25 E57 Event 57 W 0 24 E56 Event 56 W 0 23 E55 Event 55 W 0 22 E54 Event 54 W 0 21 E53 Event 53 W 0 20 E52 Event 52 W 0 19 E51 Event 51 W 0 18 E50 Event 50 W 0 17 E49 Event 49 W 0 16 E48 Event 48 W 0 15 E47 Event 47 W 0 14 E46 Event 46 W 0 13 E45 Event 45 W 0 12 E44 Event 44 W 0 11 E43 Event ...

Page 907: ... with TCC 23 R 0 22 I22 Interrupt associated with TCC 22 R 0 21 I21 Interrupt associated with TCC 21 R 0 20 I20 Interrupt associated with TCC 20 R 0 19 I19 Interrupt associated with TCC 19 R 0 18 I18 Interrupt associated with TCC 18 R 0 17 I17 Interrupt associated with TCC 17 R 0 16 I16 Interrupt associated with TCC 16 R 0 15 I15 Interrupt associated with TCC 15 R 0 14 I14 Interrupt associated wit...

Page 908: ...ted with TCC 55 R 0 22 I54 Interrupt associated with TCC 54 R 0 21 I53 Interrupt associated with TCC 53 R 0 20 I52 Interrupt associated with TCC 52 R 0 19 I51 Interrupt associated with TCC 51 R 0 18 I50 Interrupt associated with TCC 50 R 0 17 I49 Interrupt associated with TCC 49 R 0 16 I48 Interrupt associated with TCC 48 R 0 15 I47 Interrupt associated with TCC 47 R 0 14 I46 Interrupt associated ...

Page 909: ... 0 21 I21 Interrupt associated with TCC 21 W 0 20 I20 Interrupt associated with TCC 20 W 0 19 I19 Interrupt associated with TCC 19 W 0 18 I18 Interrupt associated with TCC 18 W 0 17 I17 Interrupt associated with TCC 17 W 0 16 I16 Interrupt associated with TCC 16 W 0 15 I15 Interrupt associated with TCC 15 W 0 14 I14 Interrupt associated with TCC 14 W 0 13 I13 Interrupt associated with TCC 13 W 0 1...

Page 910: ...W 0 21 I53 Interrupt associated with TCC 53 W 0 20 I52 Interrupt associated with TCC 52 W 0 19 I51 Interrupt associated with TCC 51 W 0 18 I50 Interrupt associated with TCC 50 W 0 17 I49 Interrupt associated with TCC 49 W 0 16 I48 Interrupt associated with TCC 48 W 0 15 I47 Interrupt associated with TCC 47 W 0 14 I46 Interrupt associated with TCC 46 W 0 13 I45 Interrupt associated with TCC 45 W 0 ...

Page 911: ...21 I21 Interrupt associated with TCC 21 W 0 20 I20 Interrupt associated with TCC 20 W 0 19 I19 Interrupt associated with TCC 19 W 0 18 I18 Interrupt associated with TCC 18 W 0 17 I17 Interrupt associated with TCC 17 W 0 16 I16 Interrupt associated with TCC 16 W 0 15 I15 Interrupt associated with TCC 15 W 0 14 I14 Interrupt associated with TCC 14 W 0 13 I13 Interrupt associated with TCC 13 W 0 12 I...

Page 912: ... 21 I53 Interrupt associated with TCC 53 W 0 20 I52 Interrupt associated with TCC 52 W 0 19 I51 Interrupt associated with TCC 51 W 0 18 I50 Interrupt associated with TCC 50 W 0 17 I49 Interrupt associated with TCC 49 W 0 16 I48 Interrupt associated with TCC 48 W 0 15 I47 Interrupt associated with TCC 47 W 0 14 I46 Interrupt associated with TCC 46 W 0 13 I45 Interrupt associated with TCC 45 W 0 12 ...

Page 913: ...pt associated with TCC 21 R 0 20 I20 Interrupt associated with TCC 20 R 0 19 I19 Interrupt associated with TCC 19 R 0 18 I18 Interrupt associated with TCC 18 R 0 17 I17 Interrupt associated with TCC 17 R 0 16 I16 Interrupt associated with TCC 16 R 0 15 I15 Interrupt associated with TCC 15 R 0 14 I14 Interrupt associated with TCC 14 R 0 13 I13 Interrupt associated with TCC 13 R 0 12 I12 Interrupt a...

Page 914: ...associated with TCC 54 R 0 21 I53 Interrupt associated with TCC 53 R 0 20 I52 Interrupt associated with TCC 52 R 0 19 I51 Interrupt associated with TCC 51 R 0 18 I50 Interrupt associated with TCC 50 R 0 17 I49 Interrupt associated with TCC 49 R 0 16 I48 Interrupt associated with TCC 48 R 0 15 I47 Interrupt associated with TCC 47 R 0 14 I46 Interrupt associated with TCC 46 R 0 13 I45 Interrupt asso...

Page 915: ...22 I22 Interrupt associated with TCC 22 W 0 21 I21 Interrupt associated with TCC 21 W 0 20 I20 Interrupt associated with TCC 20 W 0 19 I19 Interrupt associated with TCC 19 W 0 18 I18 Interrupt associated with TCC 18 W 0 17 I17 Interrupt associated with TCC 17 W 0 16 I16 Interrupt associated with TCC 16 W 0 15 I15 Interrupt associated with TCC 15 W 0 14 I14 Interrupt associated with TCC 14 W 0 13 I...

Page 916: ... 22 I54 Interrupt associated with TCC 54 W 0 21 I53 Interrupt associated with TCC 53 W 0 20 I52 Interrupt associated with TCC 52 W 0 19 I51 Interrupt associated with TCC 51 W 0 18 I50 Interrupt associated with TCC 50 W 0 17 I49 Interrupt associated with TCC 49 W 0 16 I48 Interrupt associated with TCC 48 W 0 15 I47 Interrupt associated with TCC 47 W 0 14 I46 Interrupt associated with TCC 46 W 0 13 ...

Page 917: ... Register Mapping Summary 1 Table 5 312 TPCC_QER Address Offset 0x1080 Physical address 0x01C0 1080 Instance IVA2 2 TPCC Description QDMA Event Register If QER En bit is set then the corresponding QDMA channel is prioritized vs other qdma events for submission to the TC QER En bit is set when a vbus write byte matches the address defined in the QCHMAPn register QER En bit is cleared when the corre...

Page 918: ...rresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER En QEER En 0 The corresponding QDMA channel comparator is disabled Events will not be recognized latched in QER En Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 Bits Field Name Description Type Reset 31 8 Reserved Read retur...

Page 919: ... Event 0 W 0 Table 5 317 Register Call Summary for Register TPCC_QEECR IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 318 TPCC_QEESR Address Offset 0x108C Physical address 0x01C0 108C Instance IVA2 2 TPCC Description QDMA Event Enable Set Register CPU write of 1 to the QEESR En bit causes the QEESR En bit to be set CPU write of 0 has no effect Type W 31 30 29 28 27 26 25 ...

Page 920: ...5 W 0 4 E4 Event 4 W 0 3 E3 Event 3 W 0 2 E2 Event 2 W 0 1 E1 Event 1 W 0 0 E0 Event 0 W 0 Table 5 321 Register Call Summary for Register TPCC_QSER IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 322 TPCC_QSECR Address Offset 0x1094 Physical address 0x01C0 1094 Instance IVA2 2 TPCC Description QDMA Secondary Event Clear Register The secondary event clear register is used t...

Page 921: ... bit is already set and a new inactive to active transition is detected on the input event n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set Event N can be cleared through sw by writing 1 to the ECR pseudo register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved E9 E8 E7 ...

Page 922: ... E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field Name Description Type Reset 31 E31 Event 31 W 0 30 E30 Event 30 W 0 29 E29 Event 29 W 0 28 E28 Event 28 W 0 27 E27 Event 27 W 0 26 E26 Event 26 W 0 25 E25 Event 25 W 0 24 E24 Event 24 W 0 23 E23 Event 23 W 0 22 E22 Event 22 W 0 21 E21 Event 21 W 0 20 E20 Event 20 W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 ...

Page 923: ...43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32 Bits Field Name Description Type Reset 31 E63 Event 63 W 0 30 E62 Event 62 W 0 29 E61 Event 61 W 0 28 E60 Event 60 W 0 27 E59 Event 59 W 0 26 E58 Event 58 W 0 25 E57 Event 57 W 0 24 E56 Event 56 W 0 23 E55 Event 55 W 0 22 E54 Event 54 W 0 21 E53 Event 53 W 0 20 E52 Event 52 W 0 19 E51 Event 51 W 0 18 E50 Event 50 W 0 17 E49 Event 49 W 0 16 E48 Event 4...

Page 924: ...20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field Name Description Type Reset 31 E31 Event 31 W 0 30 E30 Event 30 W 0 29 E29 Event 29 W 0 28 E28 Event 28 W 0 27 E27 Event 27 W 0 26 E26 Event 26 W 0 25 E25 Event 25 W 0 24 E24 Event 24 W 0 23 E23 Event 23 W 0 22 E22 Event 22 W 0 21 E21 Event 21 W 0 20 E20 Event 20 W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W ...

Page 925: ...E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32 Bits Field Name Description Type Reset 31 E63 Event 63 W 0 30 E62 Event 62 W 0 29 E61 Event 61 W 0 28 E60 Event 60 W 0 27 E59 Event 59 W 0 26 E58 Event 58 W 0 25 E57 Event 57 W 0 24 E56 Event 56 W 0 23 E55 Event 55 W 0 22 E54 Event 54 W 0 21 E53 Event 53 W 0 20 E52 Event 52 W 0 19 E51 Event 51 W 0 18 E50 Event 50 W 0 17 E49 Event 49 W 0 16 E48 Event 48 W...

Page 926: ... TC then the corresponding bit in the Event Missed Register is set CER En cannot be set or cleared through software Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field Name Description Type Reset 31 E31 Event 31 R 0 30 E30 Event 3...

Page 927: ... and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set CERH En cannot be set or cleared through software Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E3...

Page 928: ... been cleared through SW then the event will be recognized as a valid TR Sync EER En is not directly writeable Events can be enabled through writes to EESR and can be disabled through writes to EECR register EER En 0 ER En is not enabled to trigger DMA transfers EER En 1 ER En is enabled to trigger DMA transfers Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 929: ...ved E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field Name Description Type Reset 31 20 Reserved Reserved W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W 0 15 E15 Event 15 W 0 14 E14 Event 14 W 0 13 E13 Event 13 W 0 12 E12 Event 12 W 0 11 E11 Event 11 W 0 10 E10 Event 10 W 0 9 E9 Event 9 W 0 8 E8 Event 8 W 0 7 E7 Event 7 W 0 6 E6 Eve...

Page 930: ... E11 E10 Bits Field Name Description Type Reset 31 20 Reserved Reserved W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W 0 15 E15 Event 15 W 0 14 E14 Event 14 W 0 13 E13 Event 13 W 0 12 E12 Event 12 W 0 11 E11 Event 11 W 0 10 E10 Event 10 W 0 9 E9 Event 9 W 0 8 E8 Event 8 W 0 7 E7 Event 7 W 0 6 E6 Event 6 W 0 5 E5 Event 5 W 0 4 E4 Event 4 W 0 3 E3 Event 3 W 0 2 E2 ...

Page 931: ...6 5 4 3 2 1 0 Reserved E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 Bits Field Name Description Type Reset 31 20 Reserved Reserved R 0 19 E19 Event 19 R 0 18 E18 Event 18 R 0 17 E17 Event 17 R 0 16 E16 Event 16 R 0 15 E15 Event 15 R 0 14 E14 Event 14 R 0 13 E13 Event 13 R 0 12 E12 Event 12 R 0 11 E11 Event 11 R 0 10 E10 Event 10 R 0 9 E9 Event 9 R 0 8 E8 Event 8 R 0 7 E7 E...

Page 932: ...33 E32 Bits Field Name Description Type Reset 31 E63 Event 63 R 0 30 E62 Event 62 R 0 29 E61 Event 61 R 0 28 E60 Event 60 R 0 27 E59 Event 59 R 0 26 E58 Event 58 R 0 25 E57 Event 57 R 0 24 E56 Event 56 R 0 23 E55 Event 55 R 0 22 E54 Event 54 R 0 21 E53 Event 53 R 0 20 E52 Event 52 R 0 19 E51 Event 51 R 0 18 E50 Event 50 R 0 17 E49 Event 49 R 0 16 E48 Event 48 R 0 15 E47 Event 47 R 0 14 E46 Event 4...

Page 933: ...t 31 E31 Event 31 W 0 30 E30 Event 30 W 0 29 E29 Event 29 W 0 28 E28 Event 28 W 0 27 E27 Event 27 W 0 26 E26 Event 26 W 0 25 E25 Event 25 W 0 24 E24 Event 24 W 0 23 E23 Event 23 W 0 22 E22 Event 22 W 0 21 E21 Event 21 W 0 20 E20 Event 20 W 0 19 E19 Event 19 W 0 18 E18 Event 18 W 0 17 E17 Event 17 W 0 16 E16 Event 16 W 0 15 E15 Event 15 W 0 14 E14 Event 14 W 0 13 E13 Event 13 W 0 12 E12 Event 12 W ...

Page 934: ...set 31 E63 Event 63 W 0 30 E62 Event 62 W 0 29 E61 Event 61 W 0 28 E60 Event 60 W 0 27 E59 Event 59 W 0 26 E58 Event 58 W 0 25 E57 Event 57 W 0 24 E56 Event 56 W 0 23 E55 Event 55 W 0 22 E54 Event 54 W 0 21 E53 Event 53 W 0 20 E52 Event 52 W 0 19 E51 Event 51 W 0 18 E50 Event 50 W 0 17 E49 Event 49 W 0 16 E48 Event 48 W 0 15 E47 Event 47 W 0 14 E46 Event 46 W 0 13 E45 Event 45 W 0 12 E44 Event 44 ...

Page 935: ...errupt associated with TCC 23 R 0 22 I22 Interrupt associated with TCC 22 R 0 21 I21 Interrupt associated with TCC 21 R 0 20 I20 Interrupt associated with TCC 20 R 0 19 I19 Interrupt associated with TCC 19 R 0 18 I18 Interrupt associated with TCC 18 R 0 17 I17 Interrupt associated with TCC 17 R 0 16 I16 Interrupt associated with TCC 16 R 0 15 I15 Interrupt associated with TCC 15 R 0 14 I14 Interru...

Page 936: ... Interrupt associated with TCC 55 R 0 22 I54 Interrupt associated with TCC 54 R 0 21 I53 Interrupt associated with TCC 53 R 0 20 I52 Interrupt associated with TCC 52 R 0 19 I51 Interrupt associated with TCC 51 R 0 18 I50 Interrupt associated with TCC 50 R 0 17 I49 Interrupt associated with TCC 49 R 0 16 I48 Interrupt associated with TCC 48 R 0 15 I47 Interrupt associated with TCC 47 R 0 14 I46 Int...

Page 937: ...ted with TCC 22 W 0 21 I21 Interrupt associated with TCC 21 W 0 20 I20 Interrupt associated with TCC 20 W 0 19 I19 Interrupt associated with TCC 19 W 0 18 I18 Interrupt associated with TCC 18 W 0 17 I17 Interrupt associated with TCC 17 W 0 16 I16 Interrupt associated with TCC 16 W 0 15 I15 Interrupt associated with TCC 15 W 0 14 I14 Interrupt associated with TCC 14 W 0 13 I13 Interrupt associated ...

Page 938: ...ated with TCC 54 W 0 21 I53 Interrupt associated with TCC 53 W 0 20 I52 Interrupt associated with TCC 52 W 0 19 I51 Interrupt associated with TCC 51 W 0 18 I50 Interrupt associated with TCC 50 W 0 17 I49 Interrupt associated with TCC 49 W 0 16 I48 Interrupt associated with TCC 48 W 0 15 I47 Interrupt associated with TCC 47 W 0 14 I46 Interrupt associated with TCC 46 W 0 13 I45 Interrupt associated...

Page 939: ... with TCC 22 W 0 21 I21 Interrupt associated with TCC 21 W 0 20 I20 Interrupt associated with TCC 20 W 0 19 I19 Interrupt associated with TCC 19 W 0 18 I18 Interrupt associated with TCC 18 W 0 17 I17 Interrupt associated with TCC 17 W 0 16 I16 Interrupt associated with TCC 16 W 0 15 I15 Interrupt associated with TCC 15 W 0 14 I14 Interrupt associated with TCC 14 W 0 13 I13 Interrupt associated wit...

Page 940: ...d with TCC 54 W 0 21 I53 Interrupt associated with TCC 53 W 0 20 I52 Interrupt associated with TCC 52 W 0 19 I51 Interrupt associated with TCC 51 W 0 18 I50 Interrupt associated with TCC 50 W 0 17 I49 Interrupt associated with TCC 49 W 0 16 I48 Interrupt associated with TCC 48 W 0 15 I47 Interrupt associated with TCC 47 W 0 14 I46 Interrupt associated with TCC 46 W 0 13 I45 Interrupt associated wi...

Page 941: ... I22 Interrupt associated with TCC 22 R 0 21 I21 Interrupt associated with TCC 21 R 0 20 I20 Interrupt associated with TCC 20 R 0 19 I19 Interrupt associated with TCC 19 R 0 18 I18 Interrupt associated with TCC 18 R 0 17 I17 Interrupt associated with TCC 17 R 0 16 I16 Interrupt associated with TCC 16 R 0 15 I15 Interrupt associated with TCC 15 R 0 14 I14 Interrupt associated with TCC 14 R 0 13 I13...

Page 942: ...22 I54 Interrupt associated with TCC 54 R 0 21 I53 Interrupt associated with TCC 53 R 0 20 I52 Interrupt associated with TCC 52 R 0 19 I51 Interrupt associated with TCC 51 R 0 18 I50 Interrupt associated with TCC 50 R 0 17 I49 Interrupt associated with TCC 49 R 0 16 I48 Interrupt associated with TCC 48 R 0 15 I47 Interrupt associated with TCC 47 R 0 14 I46 Interrupt associated with TCC 46 R 0 13 I...

Page 943: ... with TCC 23 W 0 22 I22 Interrupt associated with TCC 22 W 0 21 I21 Interrupt associated with TCC 21 W 0 20 I20 Interrupt associated with TCC 20 W 0 19 I19 Interrupt associated with TCC 19 W 0 18 I18 Interrupt associated with TCC 18 W 0 17 I17 Interrupt associated with TCC 17 W 0 16 I16 Interrupt associated with TCC 16 W 0 15 I15 Interrupt associated with TCC 15 W 0 14 I14 Interrupt associated wit...

Page 944: ...d with TCC 55 W 0 22 I54 Interrupt associated with TCC 54 W 0 21 I53 Interrupt associated with TCC 53 W 0 20 I52 Interrupt associated with TCC 52 W 0 19 I51 Interrupt associated with TCC 51 W 0 18 I50 Interrupt associated with TCC 50 W 0 17 I49 Interrupt associated with TCC 49 W 0 16 I48 Interrupt associated with TCC 48 W 0 15 I47 Interrupt associated with TCC 47 W 0 14 I46 Interrupt associated wi...

Page 945: ...TPCC_QER_Rn Address Offset 0x2080 0x200 n n 0 to 7 Physical address 0x01C0 2080 0x200 n n Instance IVA2 2 TPCC 0 to 7 Description QDMA Event Register If QER En bit is set then the corresponding QDMA channel is prioritized vs other qdma events for submission to the TC QER En bit is set when a vbus write byte matches the address defined in the QCHMAPn register QER En bit is cleared when the correspo...

Page 946: ...3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 Bits Field Name Description Type Reset 31 8 Reserved Read returns 0 R 0x000000 7 E7 Event 7 R 0 6 E6 Event 6 R 0 5 E5 Event 5 R 0 4 E4 Event 4 R 0 3 E3 Event 3 R 0 2 E2 Event 2 R 0 1 E1 Event 1 R 0 0 E0 Event 0 R 0 Table 5 377 Register Call Summary for Register TPCC_QEER_Rn IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 378 TPCC_QE...

Page 947: ...bility W 0x000000 7 E7 Event 7 W 0 6 E6 Event 6 W 0 5 E5 Event 5 W 0 4 E4 Event 4 W 0 3 E3 Event 3 W 0 2 E2 Event 2 W 0 1 E1 Event 1 W 0 0 E0 Event 0 W 0 Table 5 381 Register Call Summary for Register TPCC_QEESR_Rn IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 382 TPCC_QSER_Rn Address Offset 0x2090 0x200 n n 0 to 7 Physical address 0x01C0 2090 0x200 n n 0 to 7 Instance I...

Page 948: ... of the QSER and QER register note that this is slightly different than the SER operation which does not clear the ER En register CPU write of 1 to the QSECR En bit clears the QSER En and QER En register fields CPU write of 0 has no effect Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 Bits Field Name Description Type R...

Page 949: ...ete chaining enable RW 0 Transfer complete chaining is disabled 1 Transfer complete chaining is enabled 21 ITCINTEN Intermediate transfer completion interrupt enable RW 0 Intermediate transfer complete interrupt is disabled 1 Intermediate transfer complete interrupt is enabled corresponding IER TCC bit must be set to 1 to generate interrupt 20 TCINTEN Transfer complete interrupt enable RW 0 Transf...

Page 950: ...y increments Source is not a FIFO 1 FIFO Src addressing within an array wraps around upon reaching FIFO width Table 5 387 Register Call Summary for Register TPCC_OPTm IVA2 2 Subsystem Functional Description EDMA 0 IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 1 Table 5 388 TPCC_SRCm Address Offset 0x4004 0x20 m Physical address 0x01C0 4004 0x20 m 4 Instance IVA2 2 TPCC Description...

Page 951: ...the maximum number of bytes in an array is 65535 bytes 64K 1 bytes ACNT must be greater than or equal to 1 for a TR to be submitted to TC An ACNT of 0 is considered as either a null or dummy transfer A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field Table 5 391 Register Call Summary for Register TPCC_ABCNTm IVA2 2 Subsy...

Page 952: ...inning of the source array to the beginning of the next source array It applies to both A sync and AB sync transfers Table 5 395 Register Call Summary for Register TPCC_BIDXm IVA2 2 Subsystem Register Manual TPCC Register Mapping Summary 0 Table 5 396 TPCC_LNKm Address Offset 0x4014 0x20 m Physical address 0x01C0 4014 0x20 m Instance IVA2 2 TPCC Description Link and Reload parameters Type RW 31 30...

Page 953: ...s a Null Linkand all 0s plus 0xFFFF will be written to the current entry location A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF The Priv Privid state is overwritten to 0x0 when linking MSBs and LSBS should not be masked when comparing against the 0xFFFF value I e...

Page 954: ...0 Read returns 0 15 0 CCNT CCNT Count for 3rd Dimension RW 0x CCNT is a 16 bit unsigned value that specifies the number of frames in a block Valid values for CCNT can be anywhere between 1 and 65535 Therefore the maximum number of frames in a block is 65535 64K 1 frames CCNT of 1 means 1 frame in the block and CCNT of 0 means 0 frames in the block A CCNT value of 0 is considered as either a null o...

Page 955: ...0x240 0x01C1 0240 0x01C1 0640 TPTCj_SASRC R 32 0x244 0x01C1 0244 0x01C1 0644 TPTCj_SACNT R 32 0x248 0x01C1 0248 0x01C1 0648 TPTCj_SADST R 32 0x24C 0x01C1 024C 0x01C1 064C TPTCj_SABIDX R 32 0x250 0x01C1 0250 0x01C1 0650 TPTCj_SAMPPRXY R 32 0x254 0x01C1 0254 0x01C1 0654 TPTCj_SACNTRLD R 32 0x258 0x01C1 0258 0x01C1 0658 TPTCj_SASRCBREF R 32 0x25C 0x01C1 025C 0x01C1 065C TPTCj_SADSTBREF R 32 0x260 0x0...

Page 956: ...on RW 0x 10 8 MAJOR Major revision RW 0x3 7 6 CUSTOM Custom revision field Not used on this version of EDMA RW 0x0 5 0 MINOR Minor revision RW 0x Table 5 404 Register Call Summary for Register TPTCj_PID IVA2 2 Subsystem Register Manual TPTC0 and TPTC1 Register Mapping Summary 0 Table 5 405 TPTCj_TCCFG Address Offset 0x004 Physical address 0x01C1 0004 Instance IVA2 2 TPTC0 Physical address 0x01C1 0...

Page 957: ...10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved DSTACTV ACTV Reserved Reserved WSACTV SRCACTV PROGBUSY DFSTRTPTR Bits Field Name Description Type Reset 31 14 Reserved Read returns 0 R 0x00000 13 12 DFSTRTPTR Dst FIFO Start Pointer R 0x0 Represents the offset to the head entry of Dst Register FIFO in units of entries Legal values 0x0 to 0x3 11 9 Reserved Read returns 0 R 0x0 8 ACTV Channel Active R 1 Chan...

Page 958: ...Table 5 408 Register Call Summary for Register TPTCj_TCSTAT IVA2 2 Subsystem Functional Description EDMA 0 IVA2 2 Subsystem Register Manual TPTC0 and TPTC1 Register Mapping Summary 1 Table 5 409 TPTCj_INTSTAT Address Offset 0x104 Physical address 0x01C1 0104 Instance IVA2 2 TPTC0 Physical address 0x01C1 0504 Instance IVA2 2 TPTC1 Description Interrupt Status Register Type R 31 30 29 28 27 26 25 24...

Page 959: ...rns 0 1 TRDONE TR Done Event Enable RW 0 INTEN TRDONE 0 TRDONE Event is disabled INTEN TRDONE 1 TRDONE Event is enabled and contributes to interrupt generation 0 PROGEMPTY Program Set Empty Event Enable RW 0 INTEN PROGEMPTY 0 PROGEMPTY Event isdisabled INTEN PROGEMPTY 1 PROGEMPTY Event isenabled and contributes to interrupt generation Table 5 412 Register Call Summary for Register TPTCj_INTEN IVA2...

Page 960: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SET EVAL Bits Field Name Description Type Reset 31 2 Reserved Write 0s for future compatibility W 0x00000000 1 SET Set TPTC interrupt W 0 Write of 1 to SET causes TPTC interrupt to be pulsed unconditionally Writes of 0 have no effect 0 EVAL Evaluate state of TPTC interrupt W 0 Write of 1 to EVAL causes TPTC interrupt to be pulsed if any of the INTS...

Page 961: ...0 and TPTC1 Register Mapping Summary 6 Table 5 419 TPTCj_ERREN Address Offset 0x124 Physical address 0x01C1 0124 Instance IVA2 2 TPTC0 Physical address 0x01C1 0524 Instance IVA2 2 TPTC1 Description Error Enable Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRERR BUSERR Reserved MMRAERR Bits Field Name Description Type Reset 31 4 Res...

Page 962: ...RCLR MMRAERR 0 Writes of 0 have no effect ERRCLR MMRAERR 1 Write of 1 clearsERRSTAT MMRAERR bit Write of 1 to ERRCLR MMRAERR does not clear the ERRDET register 2 TRERR Interrupt clear for ERRSTAT TRERR W 0 ERRCLR TRERR 0 Writes of 0 have no effect ERRCLR TRERR 1 Write of 1 clears ERRSTAT TRERR bit Write of 1 to ERRCLR TRERR does not clear the ERRDET register 1 Reserved Write 0s for future compatib...

Page 963: ...Status R 0x0 Stores the non zero status error code that was detected on the read status or write status bus MS bit effectively serves as the read vs write error code If read status and write status are returned on the same cycle then the TC chooses non zero version If both are non zero then write status is treated as higherpriority Encoding of errors matches the CBA spec and issummarized here 0xF ...

Page 964: ...IVA2 2 Subsystem Register Manual TPTC0 and TPTC1 Register Mapping Summary 0 Table 5 427 TPTCj_RDRATE Address Offset 0x140 Physical address 0x01C1 0140 Instance IVA2 2 TPTC0 Physical address 0x01C1 0540 Instance IVA2 2 TPTC1 Description Read Rate Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RDRATE Bits Field Name Description Type Re...

Page 965: ...complete interrupt is enabled 19 18 Reserved Write 0s for future compatibility RW 0x0 Read returns 0 17 12 TCC Transfer Complete Code RW 0x00 The 6 bit code is used to set the relevant bit in CER or IPR of the TPCC module 11 Reserved Write 0s for future compatibility RW 0 Read returns 0 10 8 FWID FIFO width control RW 0x0 Applies if either SAM or DAM is set to FIFO mode 0x0 FIFO width is 8 bit 0x1...

Page 966: ... RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SADDR Bits Field Name Description Type Reset 31 0 SADDR Source address for Program Register Set RW 0x00000000 Table 5 432 Register Call Summary for Register TPTCj_PSRC IVA2 2 Subsystem Functional Description EDMA 0 IVA2 2 Subsystem Register Manual TPTC0 and TPTC1 Register Mapping Summary 1 Table 5 433 TPTCj_P...

Page 967: ...PBIDX Address Offset 0x210 Physical address 0x01C1 0210 Instance IVA2 2 TPTC0 Physical address 0x01C1 0610 Instance IVA2 2 TPTC1 Description Prog Set B Dim Idx Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBIDX SBIDX Bits Field Name Description Type Reset 31 16 DBIDX Dest B Idx for Program Register Set RW 0x0000 B Idx offset between Destination arra...

Page 968: ... in the Program set along with the remainder of the parameter values The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction 7 4 Reserved Read returns 0 R 0x0 3 0 PRIVID Privilege ID R 0x0 PMPPRXY PRIVID is always updated with the value from configu...

Page 969: ...omplete Code R 0x00 The 6 bit code is used to set the relevant bit in CER or IPR of the TPCC module 11 Reserved Read returns 0 R 0 10 8 FWID FIFO width control R 0x0 Applies if either SAM or DAM is set to FIFO mode Read 0x0 FIFO width is 8 bit Read 0x1 FIFO width is 16 bit Read 0x2 FIFO width is 32 bit Read 0x3 FIFO width is 64 bit Read 0x4 FIFO width is 128 bit Read 0x5 FIFO width is 256 bit 7 Re...

Page 970: ...ource addressing mode OPT SAM and or source index value BIDX SBIDX after each read command is issued When a TR is complete the final value should be the address of the last read command issued Table 5 444 Register Call Summary for Register TPTCj_SASRC IVA2 2 Subsystem Functional Description EDMA 0 IVA2 2 Subsystem Register Manual TPTC0 and TPTC1 Register Mapping Summary 1 Table 5 445 TPTCj_SACNT A...

Page 971: ...ts Field Name Description Type Reset 31 0 DADDR Destination address is not applicable for Src Active Register Set R 0x00000000 Reads return 0x0 Table 5 448 Register Call Summary for Register TPTCj_SADST IVA2 2 Subsystem Functional Description EDMA 0 IVA2 2 Subsystem Register Manual TPTC0 and TPTC1 Register Mapping Summary 1 Table 5 449 TPTCj_SABIDX Address Offset 0x250 Physical address 0x01C1 0250...

Page 972: ...h the value from the configuration bus Privilege field on any every write to Program Set BIDX Register trigger register The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on t...

Page 973: ... for Register TPTCj_SACNTRLD IVA2 2 Subsystem Functional Description EDMA 0 IVA2 2 Subsystem Register Manual TPTC0 and TPTC1 Register Mapping Summary 1 Table 5 455 TPTCj_SASRCBREF Address Offset 0x25C Physical address 0x01C1 025C Instance IVA2 2 TPTC0 Physical address 0x01C1 065C Instance IVA2 2 TPTC1 Description Src Actv Set Src Addr A Reference Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 974: ...ddress 0x01C1 0280 Instance IVA2 2 TPTC0 Physical address 0x01C1 0680 Instance IVA2 2 TPTC1 Description Dst FIFO Set Cnt Reload Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ACNTRLD Bits Field Name Description Type Reset 31 16 Reserved Read returns 0 R 0x0000 15 0 ACNTRLD A Cnt Reload value for Destination FIFO Register set Value copied R 0x0...

Page 975: ...nce Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DADDRBREF Bits Field Name Description Type Reset 31 0 DADDRBREF Destination address reference for Dst FIFO Register Set R 0x00000000 Represents the starting address for the array currently being written The next arrays starting address is calculated as the reference address plus the dest bidxvalue Tabl...

Page 976: ...bit Read 0x5 FIFO width is 256 bit 7 Reserved Read returns 0 R 0 6 4 PRI Transfer Priority R 0x0 0 Priority 0 Highest priority 1 Priority 1 7 Priority 7 Lowest priority Read 0x0 Priority 0 Highest priority Read 0x1 Priority 1 Read 0x2 Priority 2 Read 0x3 Priority 3 Read 0x4 Priority 4 Read 0x5 Priority 5 Read 0x6 Priority 6 Read 0x7 Priority 7 Lowest Priority 3 2 Reserved Read returns 0 R 0x0 1 DA...

Page 977: ...R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCNT ACNT Bits Field Name Description Type Reset 31 16 BCNT B Count Remaining for Dst Register Set R 0x0000 Number of arrays to be transferred where each array is ACNT in length Represents the amount of data remaining to be written Initial value is copied from PCNT TC decrements ACNT and BCNT as necessary after...

Page 978: ... Instance IVA2 2 TPTC0 Physical address 0x01C1 0710 0x40 i Instance IVA2 2 TPTC1 Description Dst FIFO i Set B Dim Idx Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBIDX SBIDX Bits Field Name Description Type Reset 31 16 DBIDX Dest B Idx for Dest FIFO Register Set Value copied from PBIDX R 0x0000 B Idx offset between Destination arrays Represents the ...

Page 979: ... PRIVID Privilege ID R 0x0 DFMPPRXYi PRIVID is always updated with the value from configuration bus Privilege ID field on any every write to Program Set BIDX Register trigger register The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values The privilege ID is issued on the VBusM read and write command bus such that th...

Page 980: ...le 5 477 SYSC Register Summary continued Register Name Type Register Width Address Offset Physical Address Bits SYSC_BOOTMOD R 32 0x104 0x01C2 0104 980 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 981: ...ry 0 Table 5 480 SYSC_SYSCONFIG Address Offset 0x008 Physical address 0x01C2 0008 Instance IVA2 2 SYSC Description This register allows controlling various parameters of the SYSC module Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved AUTOIDLE Bits Field Name Description Type Reset 31 1 Reserved Write 0s for future compatibility RW 0x00000000 R...

Page 982: ...ate 14 10 Reserved Write 0s for future compatibility RW 0x00 Read returns 0 9 DMA2DOPTEN 2D transfers optimization control RW 0 0 2D DMA transfers optimization is disabled 1 2D DMA transfers optimization is enabled 8 DMATRUECOMPEN DMA write transfer true completion control RW 0 0 DMA write transfer completion is not accurate 1 DMA write transfer completion is accurate 7 4 Reserved Write 0xF for co...

Page 983: ...ity Disabled There is no aged priority in SCR DMA transaction keeps the fixed priority defined internally and has to wait for the bus to be freed by higher priority initiators Table 5 485 Register Call Summary for Register SYSC_LICFG1 IVA2 2 Subsystem Functional Description Interconnect Optimization 0 IVA2 2 Subsystem Basic Programming Model Prioritizing Defined Transfers 1 2 IVA2 2 Subsystem Regi...

Page 984: ...sed from reset Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BOOTMODE Bits Field Name Description Type Reset 31 4 Reserved Read returns 0 R 0x0000000 3 0 BOOTMODE Boot mode of the IVA2 R 0x This is the read only copy of the IVA2_BOOTMOD when the IVA2 is released from reset The value meaning is defined by the IVA2 ROM boot code Table 5 489 Reg...

Page 985: ...0 WUGEN_MEVT1 R 32 0x064 0x01C2 1064 WUGEN_MEVT2 R 32 0x068 0x01C2 1068 WUGEN_MEVTCLR0 W 32 0x070 0x01C2 1070 WUGEN_MEVTCLR1 W 32 0x074 0x01C2 1074 WUGEN_MEVTCLR2 W 32 0x078 0x01C2 1078 WUGEN_MEVTSET0 W 32 0x080 0x01C2 1080 WUGEN_MEVTSET1 W 32 0x084 0x01C2 1084 WUGEN_MEVTSET2 W 32 0x088 0x01C2 1088 WUGEN_PENDEVT0 R 32 0x090 0x01C2 1090 WUGEN_PENDEVT1 R 32 0x094 0x01C2 1094 WUGEN_PENDEVT2 R 32 0x09...

Page 986: ...ry 0 Table 5 493 WUGEN_SYSCONFIG Address Offset 0x008 Physical address 0x01C2 1008 Instance IVA2 2 WUGEN Description This register allows controlling various parameters of the WUGEN module Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved AUTOIDLE Bits Field Name Description Type Reset 31 1 Reserved Write 0s for future compatibility RW 0x0000000...

Page 987: ...k bit 25 R 1 24 MIRQ24 Interrupt Mask bit 24 R 1 23 MIRQ23 Interrupt Mask bit 23 R 1 22 MIRQ22 Interrupt Mask bit 22 R 1 21 MIRQ21 Interrupt Mask bit 21 R 1 20 MIRQ20 Interrupt Mask bit 20 R 1 19 MIRQ19 Interrupt Mask bit 19 R 1 18 MIRQ18 Interrupt Mask bit 18 R 1 17 MIRQ17 Interrupt Mask bit 17 R 1 16 MIRQ16 Interrupt Mask bit 16 R 1 15 MIRQ15 Interrupt Mask bit 15 R 1 14 MIRQ14 Interrupt Mask bi...

Page 988: ...s 0 R 0x0000 15 MIRQ47 Interrupt Mask bit 47 R 1 14 MIRQ46 Interrupt Mask bit 46 R 1 13 MIRQ45 Interrupt Mask bit 45 R 1 12 MIRQ44 Interrupt Mask bit 44 R 1 11 MIRQ43 Interrupt Mask bit 43 R 1 10 MIRQ42 Interrupt Mask bit 42 R 1 9 MIRQ41 Interrupt Mask bit 41 R 1 8 MIRQ40 Interrupt Mask bit 40 R 1 7 MIRQ39 Interrupt Mask bit 39 R 1 6 MIRQ38 Interrupt Mask bit 38 R 1 5 MIRQ37 Interrupt Mask bit 37 ...

Page 989: ...ask bit 15 R 1 14 MDMARQ14 DMA request Mask bit 14 R 1 13 MDMARQ13 DMA request Mask bit 13 R 1 12 MDMARQ12 DMA request Mask bit 12 R 1 11 MDMARQ11 DMA request Mask bit 11 R 1 10 MDMARQ10 DMA request Mask bit 10 R 1 9 MDMARQ9 DMA request Mask bit 9 R 1 8 MDMARQ8 DMA request Mask bit 8 R 1 7 MDMARQ7 DMA request Mask bit 7 R 1 6 MDMARQ6 DMA request Mask bit 6 R 1 5 MDMARQ5 DMA request Mask bit 5 R 1 ...

Page 990: ...RQCLR11 MIRQCLR10 Bits Field Name Description Type Reset 31 MIRQCLR31 MIRQ clear 31 W 0 1toSet 30 MIRQCLR30 MIRQ clear 30 W 0 1toSet 29 MIRQCLR29 MIRQ clear 29 W 0 1toSet 28 MIRQCLR28 MIRQ clear 28 W 0 1toSet 27 MIRQCLR27 MIRQ clear 27 W 0 1toSet 26 MIRQCLR26 MIRQ clear 26 W 0 1toSet 25 MIRQCLR25 MIRQ clear 25 W 0 1toSet 24 MIRQCLR24 MIRQ clear 24 W 0 1toSet 23 MIRQCLR23 MIRQ clear 23 W 0 1toSet 2...

Page 991: ...gement 1 2 IVA2 2 Subsystem Register Manual WUGEN Register Mapping Summary 3 Table 5 503 WUGEN_MEVTCLR1 Address Offset 0x074 Physical address 0x01C2 1074 Instance IVA2 2 WUGEN Description This register is used to clear the interrupt mask bits MSB Write 0 No effect Write 1 Clears the corresponding mask bit in the WUGEN_MEVT1 register Reads always return 0 Type W 1toSet 31 30 29 28 27 26 25 24 23 22...

Page 992: ...n Interrupt Requests 0 IVA2 2 Subsystem Functional Description Interrupts DMA Requests and Event Management 1 2 IVA2 2 Subsystem Register Manual WUGEN Register Mapping Summary 3 Table 5 505 WUGEN_MEVTCLR2 Address Offset 0x078 Physical address 0x01C2 1078 Instance IVA2 2 WUGEN Description This register is used to clear the dma request mask bits Write 0 No effect Write 1 Clears the corresponding mas...

Page 993: ...MDMARQ clear 10 W 0 1toSet 9 MDMARQCLR9 MDMARQ clear 9 W 0 1toSet 8 MDMARQCLR8 MDMARQ clear 8 W 0 1toSet 7 MDMARQCLR7 MDMARQ clear 7 W 0 1toSet 6 MDMARQCLR6 MDMARQ clear 6 W 0 1toSet 5 MDMARQCLR5 MDMARQ clear 5 W 0 1toSet 4 MDMARQCLR4 MDMARQ clear 4 W 0 1toSet 3 MDMARQCLR3 MDMARQ clear 3 W 0 1toSet 2 MDMARQCLR2 MDMARQ clear 2 W 0 1toSet 1 MDMARQCLR1 MDMARQ clear 1 W 0 1toSet 0 MDMARQCLR0 MDMARQ cl...

Page 994: ...SET13 MIRQSET12 MIRQSET11 MIRQSET10 Bits Field Name Description Type Reset 31 MIRQSET31 MIRQ set 31 W 0 1toSet 30 MIRQSET30 MIRQ set 30 W 0 1toSet 29 MIRQSET29 MIRQ set 29 W 0 1toSet 28 MIRQSET28 MIRQ set 28 W 0 1toSet 27 MIRQSET27 MIRQ set 27 W 0 1toSet 26 MIRQSET26 MIRQ set 26 W 0 1toSet 25 MIRQSET25 MIRQ set 25 W 0 1toSet 24 MIRQSET24 MIRQ set 24 W 0 1toSet 23 MIRQSET23 MIRQ set 23 W 0 1toSet 2...

Page 995: ... 2 IVA2 2 Subsystem Register Manual WUGEN Register Mapping Summary 3 Table 5 509 WUGEN_MEVTSET1 Address Offset 0x084 Physical address 0x01C2 1084 Instance IVA2 2 WUGEN Description This register is used to set the interrupt mask bits MSB Write 0 No effect Write 1 Sets the corresponding mask bit in the WUGEN_MEVT1 register Reads always return 0 Type W 1toSet 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 996: ...equests 0 IVA2 2 Subsystem Functional Description Interrupts DMA Requests and Event Management 1 2 IVA2 2 Subsystem Register Manual WUGEN Register Mapping Summary 3 Table 5 511 WUGEN_MEVTSET2 Address Offset 0x088 Physical address 0x01C2 1088 Instance IVA2 2 WUGEN Description This register is used to set the dma requests mask bits Write 0 No effect Write 1 Sets the corresponding mask bit in the WUG...

Page 997: ...0 MDMARQ set 10 W 0 1toSet 9 MDMARQSET9 MDMARQ set 9 W 0 1toSet 8 MDMARQSET8 MDMARQ set 8 W 0 1toSet 7 MDMARQSET7 MDMARQ set 7 W 0 1toSet 6 MDMARQSET6 MDMARQ set 6 W 0 1toSet 5 MDMARQSET5 MDMARQ set 5 W 0 1toSet 4 MDMARQSET4 MDMARQ set 4 W 0 1toSet 3 MDMARQSET3 MDMARQ set 3 W 0 1toSet 2 MDMARQSET2 MDMARQ set 2 W 0 1toSet 1 MDMARQSET1 MDMARQ set 1 W 0 1toSet 0 MDMARQSET0 MDMARQ set 0 W 0 1toSet Tab...

Page 998: ...ng interrupt number 23 R 0 22 PENDIRQ22 Masked pending interrupt number 22 R 0 21 PENDIRQ21 Masked pending interrupt number 21 R 0 20 PENDIRQ20 Masked pending interrupt number 20 R 0 19 PENDIRQ19 Masked pending interrupt number 19 R 0 18 PENDIRQ18 Masked pending interrupt number 18 R 0 17 PENDIRQ17 Masked pending interrupt number 17 R 0 16 PENDIRQ16 Masked pending interrupt number 16 R 0 15 PENDIR...

Page 999: ...upt number 46 R 0 13 PENDIRQ45 Masked pending interrupt number 45 R 0 12 PENDIRQ44 Masked pending interrupt number 44 R 0 11 PENDIRQ43 Masked pending interrupt number 43 R 0 10 PENDIRQ42 Masked pending interrupt number 42 R 0 9 PENDIRQ41 Masked pending interrupt number 41 R 0 8 PENDIRQ40 Masked pending interrupt number 40 R 0 7 PENDIRQ39 Masked pending interrupt number 39 R 0 6 PENDIRQ38 Masked pe...

Page 1000: ...dma request number 0 R 0 13 PENDDMARQ13 Masked pending dma request number 0 R 0 12 PENDDMARQ12 Masked pending dma request number 0 R 0 11 PENDDMARQ11 Masked pending dma request number 0 R 0 10 PENDDMARQ10 Masked pending dma request number 0 R 0 9 PENDDMARQ9 Masked pending dma request number 0 R 0 8 PENDDMARQ8 Masked pending dma request number 0 R 0 7 PENDDMARQ7 Masked pending dma request number 0 ...

Page 1001: ... pending interrupt number 24 W 0 23 PENDIRQ23 Masked pending interrupt number 23 W 0 22 PENDIRQ22 Masked pending interrupt number 22 W 0 21 PENDIRQ21 Masked pending interrupt number 21 W 0 20 PENDIRQ20 Masked pending interrupt number 20 W 0 19 PENDIRQ19 Masked pending interrupt number 19 W 0 18 PENDIRQ18 Masked pending interrupt number 18 W 0 17 PENDIRQ17 Masked pending interrupt number 17 W 0 16 ...

Page 1002: ... pending interrupt number 47 W 0 14 PENDIRQ46 Masked pending interrupt number 46 W 0 13 PENDIRQ45 Masked pending interrupt number 45 W 0 12 PENDIRQ44 Masked pending interrupt number 44 W 0 11 PENDIRQ43 Masked pending interrupt number 43 W 0 10 PENDIRQ42 Masked pending interrupt number 42 W 0 9 PENDIRQ41 Masked pending interrupt number 41 W 0 8 PENDIRQ40 Masked pending interrupt number 40 W 0 7 PEN...

Page 1003: ...Masked pending dma request number 0 W 0 15 PENDDMARQ15 Masked pending dma request number 0 W 0 14 PENDDMARQ14 Masked pending dma request number 0 W 0 13 PENDDMARQ13 Masked pending dma request number 0 W 0 12 PENDDMARQ12 Masked pending dma request number 0 W 0 11 PENDDMARQ11 Masked pending dma request number 0 W 0 10 PENDDMARQ10 Masked pending dma request number 0 W 0 9 PENDDMARQ9 Masked pending dm...

Page 1004: ...038 0x4 j VLCD_MPEG_INVQ RW 32 0x0000 1050 0x0008 1050 VLCD_MPEG_Q RW 32 0x0000 1054 0x0008 1054 VLCD_MPEG_DELTA_Q RW 32 0x0000 1058 0x0008 1058 VLCD_MPEG_DELTA_IQ RW 32 0x0000 105C 0x0008 105C VLCD_MPEG_THRED RW 32 0x0000 1060 0x0008 1060 VLCD_MPEG_CBP RW 32 0x0000 1064 0x0008 1064 VLCD_LUMA_VECTOR RW 32 0x0000 1068 0x0008 1068 VLCD_HUFFTAB_DCY RW 32 0x0000 106C 0x0008 106C VLCD_HUFFTAB_DCUV RW 3...

Page 1005: ... 32 0x0000 1108 0x0008 1108 VLCD_FIRST_FRAME RW 32 0x0000 110C 0x0008 110C VLCD_H264_MODE RW 32 0x0000 1110 0x0008 1110 VLCD_NRBITSTH RW 32 0x0000 1114 0x0008 1114 CAVLC_GO_REG RW 32 0x0000 1140 0x0008 1140 CAVLC_MBTYPE RW 32 0x0000 1144 0x0008 1144 CAVLC_RBTOP RW 32 0x0000 1148 0x0008 1148 CAVLC_RBEND RW 32 0x0000 114C 0x0008 114C CAVLC_BUFPTR RW 32 0x0000 1150 0x0008 1150 CAVLC_BITPTR RW 32 0x00...

Page 1006: ...P interface Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AUTOIDLE RESERVED RESERVED SIDLEMODE SOFTRESET CLOCKACTIVITY Bits Field Name Description Type Reset 31 9 RESERVED Read returns 0 RW 0x0 Write has no effect write a 0 for forward compatibility 8 CLOCKACTIVITY Clock activity during wake up mode period R 0x0 0 OCP clock can be switched o...

Page 1007: ...Description Type Reset 31 1 RESERVED Reserved for OCP socket status information R 0x00 Read returns 0 0 RESETDONE Internal reset monitoring R 0x1 0 Internal module reset is on going 1 Reset completed Table 5 531 Register Call Summary for Register IVLCD_SYSSTATUS IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 532 IVLCD_CPUSTATUSREG Address Offset 0x0000 0AE8 Physical Addr...

Page 1008: ...host OCP access to this memory Bytes RW 0x0 0 1 2 3 are swapped to 3 2 1 0 for both reads and writes 0 Disabled Native order 1 Swapped 25 IBUF0BSWAP IBUF0B 4 byte swap enable RW 0x0 24 IBUF0ASWAP IBUF0A 4 byte swap enable RW 0x0 23 21 RESERVED read returns 0 R 0x0 20 QMEM QMEM ownership RW 0x1 0 QMEM is owned by xVLCD 1 QMEM is owned by HOST 19 HMEM HMEM ownership RW 0x1 0 HMEM is owned by xVLCD 1...

Page 1009: ...0x3 Debug enable 0x4 Debug disable 0x5 Debug Step 0x6 Debug Halt Table 5 537 Register Call Summary for Register IVLCD_COMMAND IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 538 VLCD_START Address Offset 0x0000 1000 Physical Address 0x0008 1000 Instance iVLCD Description This register starts the VLCD and enables or disables the VLCD interrupt Type RW 31 30 29 28 27 26 25 ...

Page 1010: ...ion RW 0x0 0 Round off 1 Round on 14 12 NUMBLKS Sets the number of blocks RW 0x0 Range from 1 001 to 6 110 11 JPEGSYNC Sets the JPEG Sync Insertion RW 0x0 0 Off 1 On Inserts 0x00 after 0xFF 10 MPEGTYPE Sets the MPEG picture coding type RW 0x0 0 I P B picture 1 D picture 9 ESCAPE MPEG4 escape encoding RW 0x0 0 Escape3 only 1 Escape 1 2 and 3 8 INTRAVLC MPEG intra VLC format RW 0x0 7 MPEGINTRA Sets ...

Page 1011: ... 1008 Physical Address 0x0008 1008 Instance iVLCD Description This register sets the input address for the quantization computation Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ADDR MEMSEL RESERVED Bits Field Name Description Type Reset 31 16 RESERVED Write 0s for future compatibility RW 0x0000 Read returns 0 15 MEMSEL Sets the buffer used ...

Page 1012: ...DR IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 546 VLCD_IQIN_ADDR Address Offset 0x0000 1010 Physical Address 0x0008 1010 Instance iVLCD Description This register sets the input address for the inverse quantization computation Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ADDR MEMSEL RESERVED Bits Field Name Des...

Page 1013: ...Table 5 549 Register Call Summary for Register VLCD_IQOUT_ADDR IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 550 VLCD_VLCDIN_ADDR Address Offset 0x0000 1018 Physical Address 0x0008 1018 Instance iVLCD Description This register sets the input address for the variable length coder and decoder operations Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 1014: ...ts the buffer used for the computation RW 0x0 0 IMG BUF A B 1 IMG BUF1 14 13 RESERVED Write 0s for future compatibility RW 0x0 Read returns 0 12 0 ADDR Sets the start address for the computation RW 0x0000 Table 5 553 Register Call Summary for Register VLCD_VLCDOUT_ADDR IVA2 2 Subsystem Basic Programming Model Setting Up Registers for VLC Operation 0 Setting Up Registers for VLD Operation 1 IVA2 2 ...

Page 1015: ... predictor value RW 0x000 Table 5 557 Register Call Summary for Register VLCD_IDC_PREDj IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 558 VLCD_MPEG_INVQ Address Offset 0x0000 1050 Physical Address 0x0008 1050 Instance iVLCD Description This register sets the inverse quantization value used in MPEG Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 1016: ...lue used in MPEG quantization Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MDELQ Bits Field Name Description Type Reset 31 9 RESERVED Write 0s for future compatibility RW 0x00 Read returns 0 8 0 MDELQ Number of delta values RW 0x000 2 s complement Table 5 563 Register Call Summary for Register VLCD_MPEG_DELTA_Q IVA2 2 Subsystem Basic Progra...

Page 1017: ...12 RESERVED Write 0s for future compatibility RW 0x0 Read returns 0 11 0 MTHRED Number of threads RW 0x000 Table 5 567 Register Call Summary for Register VLCD_MPEG_THRED IVA2 2 Subsystem Basic Programming Model Setting Up Registers for Q IQ Operation 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 Table 5 568 VLCD_MPEG_CBP Address Offset 0x0000 1064 Physical Address 0x0008 1064...

Page 1018: ...CD Description This register sets the luma bit vector Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LUMVECT Bits Field Name Description Type Reset 31 6 RESERVED Write 0s for future compatibility RW 0x000 Read returns 0 5 0 LUMVECT Luma bit vector RW 0x00 1XXXXX Luma bit of the 1st block X1XXXX Luma bit of the 2nd block XX1XXX Luma bit of the...

Page 1019: ...n 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 Table 5 574 VLCD_HUFFTAB_DCUV Address Offset 0x0000 1070 Physical Address 0x0008 1070 Instance iVLCD Description This register sets the base address for Huffman DC tables Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED HDCUV Bits Field Name Description Type Reset 31 11 RESER...

Page 1020: ...fset 0x0000 107C 0x4 i Physical Address 0x0008 107C 0x4 i Instance iVLCD Description This register sets the base address for MPEG max level tables Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MAX Bits Field Name Description Type Reset 31 11 RESERVED Write 0s for future compatibility RW 0x00 Read returns 0 10 0 MAX Start address RW 0x000 Mus...

Page 1021: ...t boundary Table 5 583 Register Call Summary for Register VLCD_CTLTAB_DCUV IVA2 2 Subsystem Basic Programming Model Setting Up Registers for VLD Operation 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 Table 5 584 VLCD_CTLTAB_ACi Address Offset 0x0000 108C 0x4 i Physical Address 0x0008 108C 0x4 i Instance iVLCD Description This register sets the base address of the control tab...

Page 1022: ... 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 Table 5 588 VLCD_OFFSET_DCUV Address Offset 0x0000 1098 Physical Address 0x0008 1098 Instance iVLCD Description This register sets the offset value used to address the symbol table DC UV LUT Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ODCUV Bits Field Name Description Typ...

Page 1023: ...IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 2 Table 5 592 VLCD_SYMTAB_DCY Address Offset 0x0000 10A4 Physical Address 0x0008 10A4 Instance iVLCD Description This register sets the base address of the symbol table DC Y LUT Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SDCY Bits Field Name Description Type Reset 31 11 RESER...

Page 1024: ...C 0x4 i Physical Address 0x0008 10AC 0x4 i Instance iVLCD Description This register sets the base address of the symbol table ACi UV LUT Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SAC Bits Field Name Description Type Reset 31 11 RESERVED Write 0s for future compatibility RW 0x00 Read returns 0 10 0 SAC Start address RW 0x000 Must be align...

Page 1025: ...ngth in DC UV table RW 0x0 0 12 bit symbol 1 11 bit symbol 1 AC0SYMLEN Decoded symbol bit length in AC0 table RW 0x 0 12 bit symbol 1 11 bit symbol 0 AC1SYMLEN Decoded symbol bit length in AC1 table RW 0x 0 12 bit symbol 1 11 bit symbol Table 5 599 Register Call Summary for Register VLCD_VLD_CTL IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 600 VLCD_VLD_NRBIT_DC Address...

Page 1026: ...W 0x00 7 5 RESERVED Write 0s for future compatibility RW 0x0 Read returns 0 4 0 AC1 Number of bits to test for the AC1 term as input to UVLD RW 0x00 Table 5 603 Register Call Summary for Register VLCD_VLD_NRBIT_AC IVA2 2 Subsystem Basic Programming Model Setting Up Registers for VLD Operation 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 Table 5 604 VLCD_BITS_BPTR Address Off...

Page 1027: ...mary for Register VLCD_BITS_WORD IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 608 VLCD_BYTE_ALIGN Address Offset 0x0000 10C8 Physical Address 0x0008 10C8 Instance iVLCD Description VLC byte align Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ENABLE DEFAULT Bits Field Name Description Type Reset 31 2 RESERVED Writ...

Page 1028: ...0x0008 10D0 Instance iVLCD Description This register sets the number of header data to be inserted Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED HDNUM Bits Field Name Description Type Reset 31 10 RESERVED Write 0s for future compatibility RW 0x00 Read returns 0 9 0 HDNUM Number of header data to be inserted RW 0x000 1 to 1023 Table 5 613 Reg...

Page 1029: ...ll Summary for Register VLCD_QIQ_CONFIGj IVA2 2 Subsystem Basic Programming Model Setting Up Registers for Q IQ Operation 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 Table 5 616 VLCD_VLD_ERRCTL Address Offset 0x0000 10EC Physical Address 0x0008 10EC Instance iVLCD Description This register control the VLCD error enables Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 1030: ...0 UVLD UVLD error R 0x0 Table 5 619 Register Call Summary for Register VLCD_VLD_ERRSTAT IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 620 VLCD_RING_START Address Offset 0x0000 10F4 Physical Address 0x0008 10F4 Instance iVLCD Description This register sets the ring buffer start address Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 1031: ...ogramming Model Setting Up Registers for VLC Operation 0 Setting Up Registers for VLD Operation 1 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 2 Table 5 624 VLCD_CTRL Address Offset 0x0000 10FC Physical Address 0x0008 10FC Instance iVLCD Description VLCD control register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CLKON ...

Page 1032: ...s 1 2 Table 5 626 VLCD_VLD_PREFIX_DC Address Offset 0x0000 1100 Physical Address 0x0008 1100 Instance iVLCD Description This register sets the ring buffer end address Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED NBITS_DC_Y NBITS_DC_UV RESERVED Bits Field Name Description Type Reset 31 13 RESERVED Write 0s for future compatibility RW 0x0 Rea...

Page 1033: ... the UVLD Table 5 629 Register Call Summary for Register VLCD_VLD_PREFIX_AC IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 0 Table 5 630 VLCD_WMV9_CONFIG Address Offset 0x0000 1108 Physical Address 0x0008 1108 Instance iVLCD Description This register controls the WMV9 parameters Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ...

Page 1034: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FIRSTFRAME Bits Field Name Description Type Reset 31 1 RESERVED Write 0s for future compatibility RW 0x0000 Read returns 0 0 FIRSTFRAME Setting 1 specifies the first case of escape mode 3 in a frame this RW 0x0 register is cleared when found a ESCAPE3 WMV9 Table 5 633 Register Call Summary for Register VLCD_FIRST_FRAME IVA2 2 Subsystem Reg...

Page 1035: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED NRBITSTH Bits Field Name Description Type Reset 31 4 RESERVED Write 0s for future compatibility RW 0x000 Read returns 0 3 0 NRBITSTH Threshold level of nrbits number of bits in WMV9 decoding RW 0x6 When the nrbits gotten from the Huffman table is greater than this threshold value UVLD error happens Current ...

Page 1036: ...11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CODBLKPAT INTRA1616 RESERVED Bits Field Name Description Type Reset 31 9 RESERVED Write 0s for future compatibility RW 0x00 Read returns 0 8 INTRA1616 Set high when intra16x16 macroblock RW 0x0 7 6 RESERVED Write 0s for future compatibility RW 0x0 Read returns 0 5 0 CODBLKPAT Set coded block pattern as the H 264 standard describes RW 0x00 Table 5 641 Register Cal...

Page 1037: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RBEND Bits Field Name Description Type Reset 31 13 RESERVED Write 0s for future compatibility RW 0x0 Read returns 0 12 0 RBEND Set Ring Buffer End pointer in Image Buffer The value must be RW 0x0000 even RBEND 1 will be the final word address of Ring Buffer CAVLC_RBEND Table 5 645 Register Call Summary for Register CAVLC_RBEND IVA2 2 Sub...

Page 1038: ...atibility RW 0x000 Read returns 0 4 0 BITPTR Set the number of valid MSBs in stream word registers The RW 0x00 bitstream to be generated follows the valid bits It shows the number of valid MSBs in stream word registers after completion of the job Table 5 649 Register Call Summary for Register CAVLC_BITPTR IVA2 2 Subsystem Basic Programming Model Setting Up Registers for CAVLC Operation 0 1 IVA2 2 ...

Page 1039: ... Table 5 653 Register Call Summary for Register CAVLC_STRMWDL IVA2 2 Subsystem Basic Programming Model Setting Up Registers for CAVLC Operation 0 1 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 2 Table 5 654 CAVLC_HDPTR Address Offset 0x0000 1160 Physical Address 0x0008 1160 Instance iVLCD Description This register sets Huffman memory read pointer Type RW 31 30 29 28 27 26 25 24 ...

Page 1040: ...LCD Register Mapping Summary 1 Table 5 658 CAVLC_NAPTR Address Offset 0x0000 1168 Physical Address 0x0008 1168 Instance iVLCD Description This register sets Huffman memory write nA pointer Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED NAPTR Bits Field Name Description Type Reset 31 12 RESERVED Write 0s for future compatibility RW 0x0 Read re...

Page 1041: ...Operation 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 Table 5 662 CAVLC_COEFFPTR Address Offset 0x0000 1170 Physical Address 0x0008 1170 Instance iVLCD Description This register sets coefficients memory pointer Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEFFPTR Bits Field Name Description Type Reset 31 13 RESERVED...

Page 1042: ... to be assigned to the same port 0 OUTPRTSEL Select output port RW 0x0 0 ibuf0 port 1 ibuf1 port Input port and output port are allowed to be assigned to the same port Table 5 665 Register Call Summary for Register CAVLC_IBUFSEL IVA2 2 Subsystem Basic Programming Model Setting Up Registers for CAVLC Operation 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 iVLCD Register Descri...

Page 1043: ...ming Model Setting Up Registers for CAVLC Operation 0 IVA2 2 Subsystem Register Manual iVLCD Register Mapping Summary 1 Table 5 670 CAVLC_NUMRESI Address Offset 0x0000 1180 Physical Address 0x0008 1180 Instance iVLCD Description Showing how many bits are generated from residual coefficients Automatically cleared when the job starts Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12...

Page 1044: ... 32 0x0000 0064 0x0009 0064 SEQ_SWISTATE R 32 0x0000 0068 0x0009 0068 5 5 10 2 SEQ Register Descriptions Table 5 673 SEQ_REVISION Address Offset 0x0000 0000 Physical Address 0x0009 0000 Instance SEQ Description This register contains the IP revision code reset value to be defined by design team for each version of the module Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ...

Page 1045: ...x0009 0040 Instance SEQ Description This register contains the interrupt mask bits when SEQ_IRQMASK MirqN is set input event N does not trigger the interrupt line to the sequencer default when SEQ_IRQMASK MirqN is clear input event N triggers the interrupt line to the sequencer Type RW Bits Field Name Description Type Reset 31 23 RESERVED Reserved RW 0x07 Reads returns 0 Write 0 for SW forward com...

Page 1046: ...ysical Address 0x0009 0044 Instance SEQ Description Type W Bits Field Name Description Type Reset 31 23 RESERVED Reserved W 0x0 Reads returns 0 Write 0 for SW forward compatibility 22 TCERRINT1 TCERRINT1 IRQ clear w 1toSet 0x0 21 TCERRINT0 TCERRINT0 IRQ clear w 1toSet 0x0 20 CCERRINT CCERRINT IRQ clear w 1toSet 0x0 19 CCINT2 CCINT2 IRQ clear w 1toSet 0x0 18 CCINT1 CCINT1 IRQ clear w 1toSet 0x0 17 ...

Page 1047: ...n Type Reset 31 23 RESERVED Reserved W 0x0 Reads returns 0 Write 0 for SW forward compatibility 22 TCERRINT1 TCERRINT1 IRQ set w 1toSet 0x0 21 TCERRINT0 TCERRINT0 IRQ set w 1toSet 0x0 20 CCERRINT CCERRINT IRQ set w 1toSet 0x0 19 CCINT2 CCINT2 IRQ set w 1toSet 0x0 18 CCINT1 CCINT1 IRQ set w 1toSet 0x0 17 CCINT8 CCINT8 IRQ set w 1toSet 0x0 16 CCINT7 CCINT7 IRQ set w 1toSet 0x0 15 CCINT6 CCINT6 IRQ s...

Page 1048: ... R 0x0 16 CCINT7 CCINT7 IRQ status R 0x0 15 CCINT6 CCINT6 IRQ status R 0x0 14 CCINT5 CCINT5 IRQ status R 0x0 13 CCINT4 CCINT4 IRQ status R 0x0 12 CCINT3 CCINT3 IRQ status R 0x0 11 CCINTG CCINTG IRQ status R 0x0 10 CCMPINT CCMPINT IRQ status R 0x0 9 RESERVED Reserved R 0x0 8 HOST_MBX HOST_MBX IRQ status R 0x0 7 SPARE_2 Spare 2 interrupt set reserved for future use R 0x0 Reads returns 0 6 SPARE_1 Sp...

Page 1049: ...EQ_SWICLR IVA2 2 Subsystem Register Manual SEQ Register Mapping Summary 0 Table 5 687 SEQ_SWISET Address Offset 0x0000 0064 Physical Address 0x0009 0064 Instance SEQ Description This register is used to set the software interrupt bit Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SWISET Bits Field Name Description Type Reset 31 1 RESERVED Rese...

Page 1050: ...1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SWISTATE Bits Field Name Description Type Reset 31 1 RESERVED Reserved R 0x00000000 Read returns 0 0 SWISTATE SW interrupt status w 1toSet 0x0 Table 5 690 Register Call Summary for Register SEQ_SWISTATE IVA2 2 Subsystem Register Manual SEQ Register Mapping Summary 0 1050 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Co...

Page 1051: ...000 0060 0x0009 C060 VIDEOSYSC_CLKDIV RW 32 0x0000 0064 0x0009 C064 VIDEOSYSC_CLKST R 32 0x0000 0068 0x0009 C068 5 5 11 2 Video System Controller Register Descriptions Table 5 692 VIDEOSYSC_REVISION Address Offset 0x0000 0000 Physical Address 0x0009 C000 Instance VIDEOSYSC Description This register contains the IP revision code reset value to be defined by design team for each version of the modul...

Page 1052: ...ysical Address 0x0009 C040 Instance VIDEOSYSC Description This register contains the interrupt mask bits when VIDEOSYSC_IRQMASK MirqN is set input event N does not trigger the interrupt line to the sequencer default when SEQ_IRQMASK MirqN is clear input event N triggers the interrupt line to the sequencer Type w 1toSet Bits Field Name Description Type Reset 31 8 RESERVED Reserved not implemented w...

Page 1053: ...d Sequencer Module interrupt Handling 1 IVA2 2 Subsystem Register Manual Video System Controller Register Mapping Summary 2 Table 5 700 VIDEOSYSC_IRQSET Address Offset 0x0000 0048 Physical Address 0x0009 C048 Instance VIDEOSYSC Description This register is used to set the interrupt bits used to test interrupt write 0 no effect write 1 sets the corresponding bit in the VIDEOSYSC_IRQSTATE register a...

Page 1054: ...on Video accelerator clock control Writing a 0 forces the module to leave the idle state modules input clock goes active Writing a 1 requests the module enter the idle state when no request commands pending for the module Allows module input clock to be stopped Module automatically exits the idle state and clock starts each time new requests commands are present Clock status can be checked in VIDE...

Page 1055: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SEQCLKDIV Bits Field Name Description Type Reset 31 2 RESERVED Reserved RW 0x00000000 Read returns 0 1 0 SEQCLKDIV Sequencer clock division control RW 0x0 0x0 No clock division SEQ operates at the same clock as video accelerators 0x1 Clock divide by two SEQ operates at half the video accelerators clock 0x2 Clock divide by three SEQ operates a...

Page 1056: ...module R 0x0 0 SL2IF logic is active 1 SL2IF logic is idled 4 SEQMEMCLKST Clock control of the SEQ memory and slave port R 0x0 0 SEQ Slave port is active 1 SEQ Slave port is Idled 3 RESERVED Reserved R 0x0 Read returns 0 2 IVLCDCLKST Clock control of the iVLCD module R 0x0 0 iVLCD logic is active 1 iVLCD logic is idled 1 iMECLKST Clock control of the iME module R 0x0 0 iME logic is active 1 iME lo...

Page 1057: ...ERENCEBLOCKk 3 RW 32 0x0000 0880 0x4 k 0x000A 0880 0x4 k iME_COEFFREGBANKl 4 RW 32 0x0000 0980 0x4 l 0x000A 0980 0x4 l iME_PARAMETERSTACKLj 2 RW 32 0x0000 0990 0x4 j 0x000A 0990 0x4 j iME_PARAMETERSTACKHj 2 RW 32 0x0000 09D0 0x4 j 0x000A 09D0 0x4 j iME_XMVCTm 5 RW 32 0x0000 0AA0 0x4 m 0x000A 0AA0 0x4 m iME_YMVCTm 5 RW 32 0x0000 0AC0 0x4 m 0x000A 0AC0 0x4 m iME_MINERRORTHRESHOLD RW 32 0x0000 0AE0 0...

Page 1058: ...terface Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AUTOIDLE RESERVED RESERVED SIDLEMODE SOFTRESET CLOCKACTIVITY Bits Field Name Description Type Reset 31 9 RESERVED Read returns 0 R 0x0 8 CLOCKACTIVITY Clock activity during wake up mode period R 0x0 0 OCP clock can be switched off 7 5 RESERVED Read returns 0 R 0x0 4 3 SIDLEMODE Slave inte...

Page 1059: ...eset monitoring R 0x 0 Internal module reset is on going 1 Reset completed Table 5 716 Register Call Summary for Register iME_SYSSTATUS IVA2 2 Subsystem Register Manual iME Register Mapping Summary 0 Table 5 717 iME_PROGRAMBUFFERLINENLSBi Address Offset 0x0000 0040 0x8 i Physical Address 0x000A 0040 0x8 i Instance iME Description Lower part of the macro instruction bits 31 0 Type RW 31 30 29 28 27...

Page 1060: ... for SAD computation containing final errors Each entry in the register comprises a 16 bit Error field and a 16 bit Address field Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ET_ADDRESSN ET_ERRORN Bits Field Name Description Type Reset 31 16 ET_ADDRESSN Error Table line i Address value RW 0x 15 0 ET_ERRORN Error Table line i Error value RW 0x Table ...

Page 1061: ... RW 0x 15 7 RESERVED read returns 0 RW 0x000 6 0 COEFF_EVEN Coefficient even index RW 0x Table 5 726 Register Call Summary for Register iME_COEFFREGBANKl IVA2 2 Subsystem Register Manual iME Register Mapping Summary 0 Table 5 727 iME_PARAMETERSTACKLj Address Offset 0x0000 0990 0x4 j Physical Address 0x000A 0990 0x4 j Instance iME Description Parameter stack register 0 to 15 16 bit wide Contains pa...

Page 1062: ...ide are packed in one 32 bit word Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XMVCT_ODD XMVCT_EVEN Bits Field Name Description Type Reset 31 16 XMVCT_ODD MV Cost value of odd index RW 0x 15 0 XMVCT_EVEN MV Cost value of even index RW 0x Table 5 732 Register Call Summary for Register iME_XMVCTm IVA2 2 Subsystem Register Manual iME Register Mapping S...

Page 1063: ...Table 5 736 Register Call Summary for Register iME_MINERRORTHRESHOLD IVA2 2 Subsystem Register Manual iME Register Mapping Summary 0 Table 5 737 iME_ABSMINREACHED Address Offset 0x0000 0AE4 Physical Address 0x000A 0AE4 Instance iME Description Absolute Minimum Reached bit register used in Mcomp operator Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R...

Page 1064: ...instruction of the Program R 0x0 Buffer is reached and no EndPgm or LoadInstBuf instruction have been detected in the program buffer This bit is cleared by a StartSeq command 27 OPCODEERROR This bit is set to 1 when a unknown opcode is decoded R 0x0 from the main program This bit is cleared by StartSeq command when in INITIALIZED state or by a Stop command 26 WRITEREGERROR This bit is set to 1 whe...

Page 1065: ...m instruction event log R 0x0 Table 5 742 Register Call Summary for Register iME_IRQLOG IVA2 2 Subsystem Register Manual iME Register Mapping Summary 0 Table 5 743 iME_LATESTERRORS Address Offset 0x0000 0AF0 Physical Address 0x000A 0AF0 Instance iME Description Best Match Location minimum error data and its address generated by Multi compare unit Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 1066: ...OLDEN Enable Min Threshold Comparison bit RW 0x0 0 ITENABLE Interrupt Enable bit RW 0x0 Table 5 746 Register Call Summary for Register iME_CONFIGREG IVA2 2 Subsystem Register Manual iME Register Mapping Summary 0 Table 5 747 iME_SL2INSTADDRESS Address Offset 0x0000 0AF8 Physical Address 0x000A 0AF8 Instance iME Description This register contains the SL2 address passed in the instruction Type RW 31...

Page 1067: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CMD Bits Field Name Description Type Reset 31 3 RESERVED Read returns an error W 0x 2 0 CMD DATA COMMAND W 0x 0x1 StartSeq 0x2 StopSeq 0x3 DbgEnable 0x4 DbgDisable 0x5 DbgStep 0x6 Halt 0x7 Sync Table 5 750 Register Call Summary for Register iME_COMMANDREG IVA2 2 Subsystem Basic Programming Model Typical Use 0 IVA2 2 Subsystem R...

Page 1068: ...RAMETERSTACKLWk 3 RW 32 0x0000 0460 0x4 k 0x000A 1460 0x4 k iLF_EFPTABLEENTRYl 4 RW 32 0x0000 04C0 0x4 l 0x000A 14C0 0x4 l iLF_INOUTBUFFERm 5 RW 32 0x0000 0550 0x4 m 0x000A 1550 0x4 m iLF_CPUSTATUSREG R 32 0x0000 05F0 0x000A 15F0 iLF_IRQLOG R 32 0x0000 05F4 0x000A 15F4 iLF_EFPTD R 32 0x0000 05F8 0x000A 15F8 iLF_CONFIGREG RW 32 0x0000 05FC 0x000A 15FC iLF_PARSEDDATAREG0 RW 32 0x0000 0600 0x000A 160...

Page 1069: ...terface Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AUTOIDLE RESERVED RESERVED SIDLEMODE SOFTRESET CLOCKACTIVITY Bits Field Name Description Type Reset 31 9 RESERVED Read returns 0 R 0x0 8 CLOCKACTIVITY Clock activity during wake up mode period R 0x0 0 OCP clock can be switched off 7 5 RESERVED read returns 0 R 0x0 4 3 SIDLEMODE Slave inte...

Page 1070: ...eset monitoring R 0x 0 Internal module reset is on going 1 Reset completed Table 5 757 Register Call Summary for Register iLF_SYSSTATUS IVA2 2 Subsystem Register Manual iLF Register Mapping Summary 0 Table 5 758 iLF_PROGRAMBUFFERLINENLSBi Address Offset 0x0000 0040 0x8 i Physical Address 0x000A 1040 0x8 i Instance iLF Description Lower part of the macro instruction bits 31 0 Type RW 31 30 29 28 27...

Page 1071: ...4 j Instance iLF Description parameter stack register file contains parameters used by program to control the iLF units Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PARAMSTACK Bits Field Name Description Type Reset 31 16 RESERVED Read returns 0 R 0x 15 0 PARAMSTACK Parameter of 0 to 7 RW 0x Table 5 763 Register Call Summary for Register iLF...

Page 1072: ...gister Mapping Summary 0 Table 5 768 iLF_INOUTBUFFERm Address Offset 0x0000 0550 0x4 m Physical Address 0x000A 1550 0x4 m Instance iLF Description 32 bit entry in the buffer Contains 4 8 bit fields Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOFB_BYTE3 IOFB_BYTE2 IOFB_BYTE1 IOFB_BYTE0 Bits Field Name Description Type Reset 31 24 IOFB_BYTE3 High ord...

Page 1073: ...ectively executed 28 ENDPGMERROR This bit is set to 1 when the last instruction of the R 0x0 program buffer is reached and no EndPgm or LoadInstBuf instruction have been detected in the program buffer This bit is cleared by a StartSeq command when in INITIALIZED or COMPLETED state 27 OPCODEERROR This bit is set to 1 when an unknown opcode is decoded R 0x0 from the main program The following instru...

Page 1074: ...on event log R 0x0 Table 5 773 Register Call Summary for Register iLF_IRQLOG IVA2 2 Subsystem Register Manual iLF Register Mapping Summary 0 Table 5 774 iLF_EFPTD Address Offset 0x0000 05F8 Physical Address 0x000A 15F8 Instance iLF Description 32 bit generic data extracted from EFPT Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HIGHBITS LOWBITS RESERV...

Page 1075: ...c byte increments Physical Address 0x000A 1600 Instance iLF Description Lower part of the Loop Filter parameters set Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC0_FIELD TC0B_FIELD BETA2_FIELD BETA_FIELD ALPHA_FIELD RESERVED RESERVED Bits Field Name Description Type Reset 31 RESERVED read returns 0 R 0x 30 26 TC0_FIELD Tc0 parameter 5 bits unsigne...

Page 1076: ...Effective edge number unsigned 7 4 CR_FIELD Clipping limit right parameter 4 bits unsigned RW 0x 3 0 CL_FIELD Clipping limit left parameter 4 bits unsigned RW 0x Table 5 781 Register Call Summary for Register iLF_PARSEDDATAREG1 IVA2 2 Subsystem Register Manual iLF Register Mapping Summary 0 Table 5 782 iLF_PARSEDDATAREG2 Address Offset 0x608 0x608 in 0xC byte increments Physical Address 0x5E0A 160...

Page 1077: ...ntains for each line of pixel orthogonal to the edge the filter prototype reference on Right and Left side of the edge LFPC_Qi and LFPC_Pi These references are indexes into the Filter tables of the parameter stack to extract all filter parameters Status register that can be used to reconstruct the filter structure used at any place along the edge Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 1078: ... CLIP_A 9 bits signed R 0x000 Value when not used according to the standard 255 Table 5 789 Register Call Summary for Register iLF_CLIPLIMITSENTRYn IVA2 2 Subsystem Register Manual iLF Register Mapping Summary 0 Table 5 790 iLF_COMMANDREG Address Offset 0x0000 0FFC Physical Address 0x000A 1FFC Instance iLF Description iLF command register a write to this register decodes a command a read returns a...

Page 1079: ... CORE_RESET RESP_WAITING RESP_TIMEOUT BURST_TIMEOUT INBAND_ERROR_PRIMARY INBAND_ERROR_SECONDARY Bits Field Name Description Type Reset 31 30 RESERVED Reserved R 0x0 29 INBAND_ERROR_ Error Status for in band errors with MErrSteer indicating RW 0x0 SECONDARY a secondary error Read 0x0 No in band error received Write 0x0 Ignored Read 0x1 In band error received Write 0x1 Clear in band error 28 INBAND_...

Page 1080: ...ster in the module is described separately below 5 5 15 1 IA_EDMA Register Mapping Summary Table 5 795 IA_EDMA Register Mapping Summary Register Name Type Register Width Bits Address Offset Physical Address EDMA_AGENT_STATUS R 32 0x0000 0028 0x000F 8C28 5 5 15 2 IA_EDMA Register Descriptions Table 5 796 EDMA_AGENT_STATUS Address Offset 0x0000 0028 Physical Address 0x000F 8C28 Instance IA_EDMA Desc...

Page 1081: ... verification R 0x0 11 9 RESERVED Reserved R 0x0 8 RESP_TIMEOUT Response timeout status R 0x0 7 READEX Status of ReadEx Write R 0x0 6 BURST Status of open burst R 0x0 5 RESP_WAITING Responses waiting R 0x0 4 REQ_ACTIVE Requests outstanding R 0x0 3 1 RESERVED Reserved R 0x0 0 CORE_RESET Reset input from core interface R 0x0 Table 5 797 Register Call Summary for Register EDMA_AGENT_STATUS IVA2 2 Sub...

Page 1082: ...MARY Error Status for in band errors with MErrSteer indicating RW 0x0 Primary Error Read 0x0 No in band error received Write 0x0 Ignored Read 0x1 In band error received Write 0x1 Clear in band error 27 25 RESERVED Reserved R 0x0 24 MERROR MError assertion detected R 0x0 23 17 RESERVED Reserved R 0x00 16 BURST_TIMEOUT Status of open burst and R 0x0 15 12 TIMEBASE Observation of timebase signals for...

Page 1085: ...dential All rights reserved This material is reprinted with the permission of the MIPI Alliance Inc No part s of this document may be disclosed reproduced or used for any purpose other than as needed to support the use of the products of TI See OMAP36xx MIPI Disclaimer for details Topic Page 6 1 Camera ISP Overview 1086 6 2 Camera ISP Environment 1091 6 3 Camera ISP Integration 1139 6 4 Camera ISP...

Page 1086: ...Moreover on the outside boundaries of camera ISP before the mentioned above receivers are located two MIPI D PHY CSI2 compliant physical layers CSIPHY1 and CSIPHY2 The two PHYs are MIPI CSI2 and MIPI CSI1 SMIA CCP2 compliant Their purpose is to act as a physical connection between the outside pins for connecting external sensors and the internal receivers By configuring the outside PHYs and feedin...

Page 1087: ...d 5 2 Public Version www ti com Camera ISP Overview Figure 6 1 Camera ISP Overview Diagram 1 The mode for each PHY can be selected from CSI2 CSI1 CCP2B and GPI at SCM CONTROL_CAMERA_PHY_CTRL register It can also control the connection between one of the PHY s and CSI1 CCP2B receiver via multiplexing 2 There is no top level muxmode padconf SCM register control bit for the different camera modes sup...

Page 1088: ... up to 1000M bps per data lane Data merger configuration for CSI2A two data lanes and CSI2C one data lane Error detection and correction by the protocol engine DMA engine integrated with dedicated FIFO Streaming 1 D and 2 D addressing mode rotation is not supported by the 2D mode Ping pong mechanism for double buffering Burst support RAW frame transcoding Including DPCM and A law compression JPEG ...

Page 1089: ...White balance Programmable color filter array CFA interpolation 5x5 kernel Black adjustment Programmable color correction RGB to RGB Programmable gamma correction 1024 entries for each color Programmable color conversion RGB to YCbCr 4 4 4 Color subsampling YCbCr 4 4 4 to YCbCr 4 2 2 Luminance enhancement non linear chrominance suppression and offset The preview module can also work from memory to...

Page 1090: ...the memory fragmentation issue Enables the camera driver to dynamically allocate and deallocate memory the MMU handles memory fragmentation Clock generator Generates two independent clocks that can be used by two external image sensors Timing control Generation clocks passed to the clock generator Generation of signals for strobe flash mechanical shutter and global reset Support for red eye remova...

Page 1091: ... video from the ITU R BT 656 bit stream 8 bit and 10 bit modes are supported CSI1 CCP2B serial interface The camera ISP supports one CCP2B serial interface compatible MIPI CSI1 configuration serial mode MIPI CSI2 serial interfaces CSI2A and The camera ISP supports two MIPI CSI2 serial interface CSI2C configuration serial mode NOTE The two CSI2A and CSI2C receivers and the CSI1 CCP2B receiver can b...

Page 1092: ...t release shutter reset signal csi2_dx0 I Serial CSI2 mode Fully configurable pair clock or data positive or negative csi2_dy0 I Serial CSI2 mode Fully configurable pair clock or data positive or negative csi2_dx1 I Serial CSI2 mode Fully configurable pair clock or data positive or negative csi2_dy1 I Serial CSI2 mode Fully configurable pair clock or data positive or negative csi2_dx2 I Serial CSI...

Page 1093: ...on must also be done For information about initializing and configuring the CSIPHY see Section 6 5 2 Programming the CSI1 CCP2B or CSI2 Receiver Associated PHY In GPI mode the PHY can be connected to a parallel camera CAM_D 1 0 in CSIPHY1 and CAM_D 9 6 in CSIPHY2 In CCP mode the PHY can be connected to a CCPV2 camera strobe data pairs or a CSI1 camera clock data pairs In D PHY mode the PHY can be ...

Page 1094: ...r rail VIO pwr rail VIO pwr rail CCP pwr rail CCP cam_d10 cam_d11 cam_xclkb CPI CPI CPI cam_wen cam_strobe csi2_dx0 ccpv2_dx0 csi2_dy0 ccpv2_dy0 CSI1 CCP2B with CSI1 CCP2B with CSI2A 7 CSI2A 8 CSI2A 7 CSI2A 7 CSIPHY2 CSIPHY2 csi2_dx1 ccpv2_dx1 csi2_dy1 ccpv2_dy1 vdda_csiphy2 pwr rail CSI pwr rail CSI pwr rail CCP pwr rail CSI pwr rail CSI pwr rail CSI 1 CPI Interface in orange 2 Full All data cloc...

Page 1095: ... sensor and the other camera sensor CCP2 or CSI2 are connected to the same CSIPHY the CONTROL_CAMERAx_PHY_CAMMOD bit must be set for CCP2 or CSI2 mode respectively even if only one pair is used as GPI for CPI mode In that case the corresponding CSI2_COMPLEXIO_CFG1 DATAx_POSITION bit must be set to 0x0 for the lane used in GPI mode 1095 SWPU177N December 2009 Revised November 2010 Camera Image Sign...

Page 1096: ...al synchronization cam_vs During the image sensor readout these signals define when a row of valid data begins and ends and when a frame starts and ends NOTE For correct operation the clock cam_pclk must run during blanking periods cam_hs and cam_vs inactive cam_pclk must start before sending cam_d and start cam_vs and cam_hs Figure 6 2 and Figure 6 3 show the frame and data timing respectively ba...

Page 1097: ...Public Version www ti com Camera ISP Environment Figure 6 4 Camera ISP SYNC Mode Clock Gating 6 2 4 2 Camera ISP Parallel Generic Configuration JPEG Sensor Connection on the Parallel Interface Some camera modules integrate an image signal processor ISP and a JPEG encoder The CCDC can interface with these camera modules and transfer the received JPEG stream to memory To use this mode set the ISP_CT...

Page 1098: ...er of wires required for a BT 656 video interface There are two timing reference codes The start of active video SAV reference code precedes each video data block and the end of active video EAV follows each video data block Each timing reference signal consists of a 4 byte sequence in the following hexadecimal format FF 00 00 XY The first 3 bytes are a fixed preamble see the ITU R BT 656 specific...

Page 1099: ...gister field to 1 In addition the NPH register field must be set to accurately represent the number of active pixels 6 2 4 4 Camera ISP CSI1 CCP2 Protocol and Data Formats The CSI1 CCP2B receiver supports two protocols MIPI CSI1 protocol CCP2 protocol The MIPI CSI1 protocol is compatible with the CCP2 protocol with the following constraints Class 0 CCP2 sensors are used Data clock No RAW6 or RAW7 ...

Page 1100: ...M10 VP sent to VP decompression CCP2 only 0xB RAW10 RAW6 6 64 40 No DPCM DPCM compression CCP2 only 0xC RAW7 EXP8 8 16 14 No CCP2 only 0xD RAW7 16 8 129 No DPCM DPCM10 decompression EXP16 CCP2 only 0xE RAW7 N A data are 32 N A N A DPCM DPCM10 VP sent to VP decompression CCP2 only 0xF RAW10 RAW6 8 16 20 No DPCM DPCM EXP8 compression CCP2 only 0x10 RAW6 6 64 N A No CCP2 only 0x10 RAW7 7 128 N A No C...

Page 1101: ...1 0 RGB444 EXP32 Data expansion to 32 bits padding with alpha CCP2_LCx_CTRL 15 8 ALPHA can be used to set an alpha value For RGB888 EXP32 data_out 31 24 ALPHA 7 0 and data_out 23 0 RGB888 FSP False synchronization code protection decoding Applies only to JPEG8 data format VP Output to the video processing hardware is enabled The programmer must ensure that only one logical channel is enabled to th...

Page 1102: ... to the video port The CSI1 CCP2B receiver can cope with all data formats if the data line length sent through the associated PHY is a multiple of 32 bits This condition is required for the CSI1 CCP2B receiver to work correctly However some data formats impose stronger line length constraints to correctly finish pixel reconstruction at the end of the lines If the additional constraints are not res...

Page 1103: ...1 1 2 1 1 First two pixels of first even line are y v u and y v u n 1 n 1 n 1 n 2 n 1 n 1 u1 v1 y1 y2 u3 y3 un 1 yn 1 vn 1 yn 3 yn 2 un 3 u1 v1 y1 y2 u1 v1 y1 y2 Public Version www ti com Camera ISP Environment Figure 6 9 Camera ISP CSI1 CCP2 YUV422 Little Endian The line length sent through the associated configured PHY is a multiple of 32 bits Furthermore the line length is a multiple of 3 x 32 ...

Page 1104: ...st odd line are y1 v1 u1 and y2 v1 u1 First two pixels of first even line are yn 1 v1 u1 and yn 2 v1 u1 u3 u1 Odd lines Even lines Picture width n y u y Picture height v u y v y y y y y y u y v u y v y y y y y Transmitted frame Public Version Camera ISP Environment www ti com Figure 6 10 Camera ISP CSI1 CCP2 YUV420 6 2 4 4 1 2 Camera ISP CSI1 CCP2 RGB Pixel Data Formats RGB888 data format can be o...

Page 1105: ...5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 Receiver Line width must be a multiple of three 32 bit words 31 0 FIFO Data mem org a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 B1 G1 R1 31 0 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 B2 G2 R2 31 0 0 0 0 0 0 0 0 0 B3 G3 R3 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 31 0 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d...

Page 1106: ...P2 RGB565 RGB444 data format is output to memory with data expansion If data expansion is used the value of the 4 upper bits is programmable and can be set with an alpha value for computer graphics applications The line length sent through the associated PHY is a multiple of 32 bits see Figure 6 13 Figure 6 13 Camera ISP CSI1 CCP2 RGB444 6 2 4 4 1 3 Camera ISP CSI1 CCP2 RAW Bayer RGB Pixel Data Fo...

Page 1107: ... a4 a3 a2 a1 a0 0 0 0 0 0 b9 b8 0 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 d9 d8 d6 d5 d3 d4 d2 d1 d0 0 0 0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 b2 Public Version www ti com Camera ISP Environment Figure 6 14 Camera ISP CSI1 CCP2 RAW 6 6 2 4 4 1 3 2 Camera ISP CSI1 CCP2 RAW7 CCP2 Only RAW7 data format can be output to memory in two formats with no data expansion and ...

Page 1108: ...7 DPCM10 EXP16 RAW7 DPCM10 VP t0 VP_DATA 9 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 t1 VP_DATA 9 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t2 VP_DATA 9 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 t3 VP_DATA 9 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a6 b6 c6 d6 Public Version Camera ISP Environment www ti com Figure 6 15 Camera ISP CSI1 CCP2 RAW 7 6 2 4 4 1 3 3 Camera ISP CSI1 CCP2 RAW8 RAW8 data format can be output to memory in two fo...

Page 1109: ...d1 d0 Public Version www ti com Camera ISP Environment Figure 6 16 Camera ISP CSI1 CCP2 RAW8 6 2 4 4 1 3 4 Camera ISP CSI1 CCP2 RAW10 RAW10 data format can be output to memory in two formats with no data expansion and with data expansion If data expansion is used the 10 bit data are padded with 0s on a 16 bit word The line length sent through the associated PHY is a multiple of 32 bits Furthermore...

Page 1110: ...7 o6 o5 o4 o3 o2 31 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 b8 e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 f7 f6 f5 f4 f3 f2 f1 f0 f8 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 d8 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 j7 j6 j5 j4 j3 j2 j1 j0 j8 g9 g8 g7 g6 g5 g4 g3 g2 g1 g0 h7 h6 h5 h4 h3 h2 h1 h0 h8 m9 m8 m7 m6 m5 m4 m3 m2 m1 m0 n7 n6 n5 n4 n3 n2 n1 n0 n8 k9 k8 k7 k6 k5 k4 k3 k2 k1 k0 l7 l6 ...

Page 1111: ...9 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t2 VP_DATA 9 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 t3 VP_DATA 9 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 expansion EXP16 d10 d11 a8 a9 a10 a11 b4 b5 b6 b7 b8 b9 b10 b11 a0 a1 a2 a3 b0 b1 b2 c10 c0 c1 c2 c3 d0 d1 d2 d3 e10 e11 f4 f5 f6 f7 f8 f9 f10 f11 g10 g11 h10 h11 c11 f10 h10 b11 d11 f11 h11 c10 b11 b10 a11 a9 a8 a7 a6 a5 a4 a10 e11 e10 d11 d9 d8 d7 d6 d5 d4 d10 g11 g10 c11 a...

Page 1112: ... equal to an illegal combination synchronization codes the byte 0xA5 that comes after byte n 1 is removed from the bitstream The 0xA5 padding bytes at the end of the frame are also removed by FSP decoding so that padding does not generate additional data in the FIFO FSP decoding is then transparent to the software Normally the module detects the illegal combination and then the 0xA5 When the 0xA5 ...

Page 1113: ...P CSI2 Two Data Lane Merger Configuration Figure 6 21 Camera ISP CSI2 One Data Lane Configuration 6 2 4 5 2 Camera ISP CSI2 Protocol Layer The low level protocol LLP is a byte oriented protocol from the lane merger layer It supports short and long packet formats The CSI2 protocol layer defines how image sensor data is transported onto the physical layer The feature set of the protocol layer implem...

Page 1114: ...e frame number is always 0 The frame number is inoperative The frame number increments by 1 for every FS packet with the same virtual channel and is periodically reset to 1 1 2 1 2 1 2 1 2 or 1 2 3 4 1 2 3 4 For line start code LSC and line end code LEC synchronization packets the short packet data field contains a 16 bit line number This line number is the same for the LS and LE packets correspon...

Page 1115: ...an 8 bit data identifier a 16 bit word count field and an 8 bit ECC The packet footer has one element a 16 bit checksum Figure 6 24 and Table 6 9 show the structure of a long packet Figure 6 24 Camera ISP CSI2 Long Packet Structure Table 6 9 Camera ISP CSI2 Long Packet Structure Description Packet Part Field Name Size Bit Description Header Data ID 8 Contains the virtual channel identifier and the...

Page 1116: ...tart and line end A set of registers is associated with each context defined by the virtual channel ID and the data type Figure 6 26 shows a virtual channel Figure 6 26 Camera ISP CSI2 Virtual Channel Pixel Formats Image sensor data can have multiple data types Table 6 10 summarizes the pixel formats supported by the CSI2 receiver interface Table 6 10 Camera ISP CSI2 Pixel Format Modes Mode Descri...

Page 1117: ...mage data RAW14 RAW Bayer 14 bit image data RAW14 EXP16 RAW Bayer 14 bit image data RAW14 VP RAW Bayer 14 bit image data JPEG 8 bit data JPEG8 For more information on how the data formats are transmitted and how the data are stored in memory see Section 6 2 4 5 3 Camera ISP CSI2 Pixel Data Format 6 2 4 5 2 4 Camera ISP CSI2 Synchronization Codes Data reception from the image sensor module uses fou...

Page 1118: ...and after the picture data can be sent as start of frame SOF and end of frame EOF information by the image sensor to the memory through the L3 port For each frame the pixel data arbitrary data or user defined byte data are valid only after an SOF short packet If the data are invalid they are discarded by the protocol engine A frame comprises embedded data and image sensor data Figure 6 27 shows wh...

Page 1119: ...d or user defined byte based data Frame of arbitrary pixels and or user defined byte based data Data per line is a multiple of 8 bits Key PH Packet header PF Packet footer FS Frame start FE Frame end Public Version www ti com Camera ISP Environment Figure 6 27 Camera ISP CSI2 General Frame Structure Informative Figure 6 28 shows the frame structure of a YUV422 interlaced video frame without embedd...

Page 1120: ... period The time between the FEC and the new FSC is the frame blanking period The receiver works with the line blanking period set to 0 6 2 4 5 3 Camera ISP CSI2 Pixel Data Format 6 2 4 5 3 1 Camera ISP CSI2 YUV Pixel Data Format 6 2 4 5 3 1 1 Camera ISP CSI2 YUV420 8 Bit YUV420 8 bit data can be stored to memory in little endian format The line length sent through the CSI2 physical protocol is a ...

Page 1121: ...ation e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 t0 VP_DATA 0 0 0 0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 t1 VP_DATA 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 t2 VP_DATA 0...

Page 1122: ...g2 g3 g4 g5 g6 g7 U1 9 2 Y1 9 2 V1 9 2 Y2 9 2 U3 9 2 Y3 9 2 V3 9 2 t0 t31 t32 t63 Receiver odd line FIFO data memory organization Y4 9 2 U5 9 2 Y5 9 2 t64 t95 Time a8 a9 b8 b9 c8 c9 d8 d9 a0 a1 b0 b1 c0 c1 d0 d1 U1 1 0 Y1 1 0 V1 1 0 Y2 1 0 e0 e1 f0 f1 g0 g1 h0 h1 h2 h3 h4 h5 h6 h7 e8 e9 f8 f9 g8 g9 h8 h9 I2 I3 I4 I5 I6 I7 J2 J3 J4 J5 J6 J7 I8 I9 J8 J9 U3 1 0 Y3 1 0 V3 1 0 Y4 1 0 a2 a3 a4 a5 a6 a7 ...

Page 1123: ...4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 Public Version www ti com Camera ISP Environment Figure 6 31 Camera ISP CSI2 ...

Page 1124: ...ine FIFO data memory organization e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 Public Version Camera ISP Environment www ti com Figure 6 32 Camera ISP CSI2 Y...

Page 1125: ... f4 f5 f6 f7 g2 g3 g4 g5 g6 g7 U1 9 2 Y1 9 2 V1 9 2 Y2 9 2 U3 9 2 Y3 9 2 V3 9 2 t0 t31 t32 t63 Receiver odd line FIFO data memory organization Y4 9 2 U5 9 2 Y5 9 2 t64 t95 Time a8 a9 b8 b9 c8 c9 d8 d9 a0 a1 b0 b1 c0 c1 d0 d1 U1 1 0 Y1 1 0 V1 1 0 Y2 1 0 e0 e1 f0 f1 g0 g1 h0 h1 h2 h3 h4 h5 h6 h7 e8 e9 f8 f9 g8 g9 h8 h9 I2 I3 I4 I5 I6 I7 J2 J3 J4 J5 J6 J7 I8 I9 J8 J9 U3 1 0 Y3 1 0 V3 1 0 Y4 1 0 a2 a3...

Page 1126: ...I6 I7 J2 J3 J4 J5 J6 J7 I8 I9 J8 J9 U3 1 0 Y3 1 0 V3 1 0 Y4 1 0 a2 a3 a4 a5 a6 a7 b2 b3 b4 b5 b6 b7 c2 c3 c4 c5 c6 c7 d2 d3 d4 d5 d6 d7 e2 e3 e4 e5 e6 e7 f2 f3 f4 f5 f6 f7 g2 g3 g4 g5 g6 g7 U1 9 2 Y1 9 2 V1 9 2 Y2 9 2 U3 9 2 Y3 9 2 V3 9 2 Y4 9 2 U5 9 2 Y5 9 2 a8 a9 b8 b9 c8 c9 d8 d9 a0 a1 b0 b1 c0 c1 d0 d1 Y2 1 0 V1 1 0 Y1 1 0 U1 1 0 e0 e1 f0 f1 g0 g1 h0 h1 h2 h3 h4 h5 h6 h7 e8 e9 f8 f9 g8 g9 h8 h...

Page 1127: ...17 Public Version www ti com Camera ISP Environment 6 2 4 5 3 2 Camera ISP CSI2 RGB Operating Modes 6 2 4 5 3 2 1 Camera ISP CSI2 RGB565 RGB565 data is output to memory without data expansion The line length sent through the CSI2 physical layer is always a multiple of 16 bits Figure 6 36 shows the storage format for RGB565 data Figure 6 36 Camera ISP CSI2 RGB565 6 2 4 5 3 2 2 Camera ISP CSI2 RGB88...

Page 1128: ... f4 f5 f6 f7 B1 G1 R1 G2 R2 31 31 0 0 X X X X X X X X d0 d1 d2 d3 d4 d5 d6 d7 B2 X X X X X X X X Receiver FIFO data memory organization with 32 bit data expansion Public Version Camera ISP Environment www ti com Figure 6 37 Camera ISP CSI2 RGB888 6 2 4 5 3 2 3 Camera ISP CSI2 RGB666 RGB666 data is always output to memory with data expansion The value of the 14 upper bits is programmable and can be...

Page 1129: ... b3 b4 b5 c0 c1 c2 c3 c4 c5 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4 f5 B1 G1 R1 G2 R2 31 31 0 0 X X X X X X X X d0 d1 d2 d3 d4 d5 B2 X X X X X X X X X X X X X X X X X X X X FIFO data memory organization with 32 bit data expansion FIFO data memory organization with 24 bit data expansion on 32 bit word Public Version www ti com Camera ISP Environment Figure 6 38 Camera ISP CSI2 RGB666 6 2 4 5 3 2 4 Camera ...

Page 1130: ... d4 c0 c1 c2 c3 c4 g0 g1 g2 g3 g4 h0 h1 h2 h3 h4 i0 i1 i2 i3 i4 k0 k1 k2 k3 k4 l0 l1 l2 l3 l4 j0 j1 j2 j3 j4 B1 4 0 G1 5 0 R1 4 0 B2 4 0 G2 5 0 R2 4 0 B3 4 0 G3 5 0 R3 4 0 B4 4 0 G4 5 0 R4 4 0 B1 4 0 G1 5 0 R1 4 0 B2 4 0 G2 5 0 R2 4 0 B3 4 0 G3 5 0 R3 4 0 B4 4 0 G4 5 0 R4 4 0 0 0 0 0 0 0 0 0 FIFO data memory organization with 16 bit data expansion Public Version Camera ISP Environment www ti com F...

Page 1131: ...a3 a2 a1 a0 b5 b4 b3 b2 b1 b0 c5 c4 c3 c2 c1 c0 i5 i4 i3 i2 i1 k3 k2 k1 k0 j5 j4 j3 j2 j1 i0 j0 P7 P8 P9 P10 P11 Receiver CSI2_CTX_CTRL2 9 0 FORMAT RAW6 f1 f0 P6 e5 e4 e3 e2 e1 e0 P5 P4 d5 d4 d3 d2 d1 d0 camisp 272 CSI2_CTX_CTRL2 9 0 FORMAT RAW6 DPCM10 VP t0 VP_DATA 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 t1 VP_DATA 0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t2 VP_DATA 0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 ...

Page 1132: ...c3 c2 c1 c0 31 31 0 0 Receiver CSI2_CTX_CTRL2 9 0 FORMAT RAW7 CSI2_CTX_CTRL2 9 0 FORMAT RAW7 DPCM10 VP t0 VP_DATA 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 t1 VP_DATA 0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t2 VP_DATA 0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 t3 VP_DATA 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 P1 P2 P3 P4 P5 e3 e2 e1 e0 e6 e5 f6 f5 f4 f3 f2 f1 g6 g5 g4 g3 g2 g1 h6 h5 h4 h3 h2 h1 a6 a5 a4 a3 a2...

Page 1133: ...b0 t2 VP_DATA 0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 t3 VP_DATA 0 0 0 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 CSI2_CTX_CTRL2 9 0 FORMAT RAW78 CSI2_CTX_CTRL2 9 0 FORMAT RAW8 VP t0 VP_DATA 0 0 0 0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 t1 VP_DATA 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 t2 VP_DATA 0 0 0 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0 t3 VP_DATA 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 Public Version www ti com Camera ISP Environm...

Page 1134: ... d4 d5 d6 d7 P1 9 0 P2 9 0 P3 9 0 P4 9 0 a8 a9 b8 b9 c8 c9 d8 d9 a0 a1 b0 b1 c0 c1 d0 d1 31 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO data memory organization without data expansion FIFO data memory organization with 16 bit data expansion t0 VP_DATA 0 0 0 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 t1 VP_DATA 0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t2 VP_DATA 0 0 0 0 c9 c8 c7 c6 c5 c4 c3 c2 c1...

Page 1135: ... d6 d7 P1 11 0 P2 11 0 P3 11 0 P4 11 0 a8 a9 b8 b9 c8 c9 d8 d9 a0 a1 b0 b1 c0 c1 d0 d1 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a10 a11 b10 b11 c10 c11 d11d10 FIFO data memory organization without data expansion FIFO data memory organization with 16 bit data expansion t0 VP_DATA 0 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 t1 VP_DATA 0 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 t2 VP_DATA 0 0 c11 c10 c9 c...

Page 1136: ... 13 6 P6 1 0 P6 5 2 P7 5 0 P8 5 0 a12 a13 b12 b13 c12 c13 d12 d13 e12 e13 f12 f13 g12 g13 h12 h13 f4 f5 f2 f3 f0 f1 g2 g3 g4 g5 g0 g1 h0 h1 h2 h3 h4 h5 Receiver 31 a2 a3 a4 a5 a6 a7 b2 b3 b4 b5 b6 b7 c2 c3 c4 c5 c6 c7 d2 d3 d4 d5 d6 d7 P1 13 0 P2 13 0 P3 13 0 P4 13 0 a8 a9 b8 b9 c8 c9 d8 d9 a0 a1 b0 b1 c0 c1 d0 d1 31 0 0 0 0 0 0 0 0 0 0 a10 a11 b10 b11 c10 c11 d11d10 a12 a13 b12 b13 c12 c13 d12 d1...

Page 1137: ...efines how the data stream is decoded When generic mode is enabled GENERIC 1 MIPI data type code is ignored and data is decoded using the FORMAT bit Whatever the MIPI data type code it is ignored the data stream is processed even if the FORMAT bit does not match the MIPI data type code When generic mode is not used GENERIC 0 the data stream is processed only when the MIPI data type code matches th...

Page 1138: ...c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 For example CSI2_CTx_CTRL2 9 0 FORMAT RAW8 Public Version Camera ISP Environment www ti com Figure 6 49 Camera ISP CSI2 Byte Swap 1138 Camera Image Signal Processor SWPU177N Dece...

Page 1139: ...igure 6 50 shows the Camera ISP integration Figure 6 50 Camera ISP Integration 6 3 1 Camera ISP Clocking Reset and Power Management Scheme 6 3 1 1 Camera ISP Clocks There are six clock domains in the camera ISP Functional clock domain this clock is from L3 interconnect along with Interface master write port clock It is required to be 2x faster than the pixel clock CSI1 CCP2B Serial interface clock...

Page 1140: ...interface clock domain from L4 interconnect 6 3 1 1 1 Camera ISP Clock Tree Figure 6 51 shows the clock tree for the camera ISP module Figure 6 51 Camera ISP Clock Tree Diagram 6 3 1 1 2 Camera ISP Clock Descriptions Table 6 12 describes the camera ISP clocks Table 6 12 Camera ISP Clock Descriptions Signal Name IO Description CAM_FCLK Input Functional clock L3 interconnect clock domain Functional ...

Page 1141: ...ace Its source is the PRCM CAM_L4_ICLK output When the camera ISP no longer needs CAM_ICLK the software can disable it at PRCM level by setting to 0x0 the PRCM CM_ICLKEN_CAM 0 EN_CAM bit The clock is not effectively shut down until the camera ISP module has reached the IDLE state that is It does not generate anymore traffic on the device interconnect and is internally idled As information note an ...

Page 1142: ...terconnect clock is based on interface activity regardless of hardware handshake protocols After a reset this mode is enabled by default NOTE It is recommended that this mode be enabled to reduce power consumption 6 3 1 2 2 Camera ISP System Power Management As part of the system power management scheme the camera ISP module interacts with the PRCM through an automatic standby hardware protocol th...

Page 1143: ...the PRCM according with its internal activity namely when there is no more activity on the camera ISP master interface that is when there is no more data in the central resource buffer NOTE The CSI1 CCP2B receiver must also be configured to smart standby mode when the camera ISP is set to smart standby CCP2_SYSCONFIG 13 12 MSTANDBY_MODE set to 0x2 CSI2A and CSI2C receivers must also be configured ...

Page 1144: ...cedure If after five reads CCP2_SYSSTATUS 0 RESET_DONE still returns 0 it can be assumed that an error occurred during the reset stage The CSI2A and CSI2C receivers accept a general software reset propagated through the hierarchy This reset can be performed to initialize the module and has the same effect as a hardware reset The CSI2A and CSI2C receivers can be reset by writing CSI2_SYSCONFIG 1 SO...

Page 1145: ... interrupts CAM_IRQ0 is an interrupt to the MPU subsystem interrupt controller It is mapped on M_IRQ_24 CAM_IRQ1 is an interrupt to the IVA2 2 subsystem interrupt controller It is mapped on IVA2_IRQ 11 Table 6 15 summarizes events that cause interrupts Table 6 15 Camera ISP Interrupts Event Mask Description ISP_IRQ0STATUS 31 HS_VS_IRQ ISP_IRQ0ENABLE 31 HS_VS_IRQ HS or VS synchronization event trig...

Page 1146: ... CCDC_LSC_DONE internal state of LSC toggles from BUSY to IDLE This happens when the LSC module has completed processing the current frame ISP_IRQ0STATUS 16 ISP_IRQ0ENABLE 16 HIST_DONE_IRQ HIST module Processing done event triggered at HIST_DONE_IRQ the end of the frame when processing is complete for the current frame ISP_IRQ0STATUS 13 ISP_IRQ0ENABLE 13 H3A module Auto exposure and auto white H3A...

Page 1147: ...pends on the CBUFFx_CTRL ALLOW_NW_EQ_CR flag and the circular buffer mode read or write This event indicates a bandwidth mismatch between data producer and data consumer When it occurs CBUFFx does NOT go into error state However the data in the physical buffer is very likely to be corrupted CBUFF_IRQSTATUS 4 CBUFF_IRQENABLE 4 Invalid access IRQ_CBUFF1_INVALID IRQ_CBUFF1_INVALID Camera controller w...

Page 1148: ...tion code detection for LC1_FE_IRQ logical channel 1 This interrupt is triggered on the detection of a frame end synchronization code into the CCP2 data stream CCP2_LC01_IRQSTATUS 23 CCP2_LC01_IRQENABLE 23 Frame counter reached for logical channel 1 LC1_COUNT_IRQ LC1_COUNT_IRQ This interrupt is triggered when the frame counter has reached its programmable target value CCP2_LC01_IRQSTATUS 21 CCP2_L...

Page 1149: ...ical channel 0 LC0_FIFO_OVF_IRQ LC0_FIFO_OVF_IRQ This interrupt is triggered on the detection of a FIFO overflow error CCP2_LC01_IRQSTATUS 4 CCP2_LC01_IRQENABLE 4 LC0_CRC_IRQ CRC error LC0_CRC_IRQ This interrupt is triggered on the detection of a CRC error into the CCP2 data stream CCP2_LC01_IRQSTATUS 3 CCP2_LC01_IRQENABLE 3 LC0_FSP_IRQ False synchronization code protection error for LC0_FSP_IRQ l...

Page 1150: ...ATUS 19 CCP2_LC23_IRQENABLE 19 False synchronization code protection error for LC3_FSP_IRQ LC3_FSP_IRQ logical channel 3 This interrupt is triggered by the FSP decoder if an illegal combination is detected but 0xA5 is not present in the bit stream CCP2_LC23_IRQSTATUS 18 CCP2_LC23_IRQENABLE 18 LC3_FW_IRQ Frame width error for logical channel 3 LC3_FW_IRQ This interrupt is generated if the frame wid...

Page 1151: ... 1 LC2_FSC_IRQ False synchronization code error error for logical LC2_FSC_IRQ channel 2 This interrupt is triggered on the detection of a false synchronization code error into the CCP2 data stream CCP2_LC23_IRQSTATUS 0 CCP2_LC23_IRQENABLE 0 LC2_SSC_IRQ Shifted synchronization code error for logical LC2_SSC_IRQ channel 2 This interrupt is triggered if LEC or FEC are not aligned on a 32 bit boundary...

Page 1152: ...art line end frame start and frame end only data types between 0x8 and 0xF are considered CSI2_IRQSTATUS 14 CSI2_IRQENABLE 14 OCP_ERR_IRQ OCP error OCP_ERR_IRQ Table 6 19 shows CSI2A and CSI2C receiver event generation interrupt status and interrupt enable registers receiving signals from the associated PHY Table 6 19 Camera ISP CSI2A and CSI2C Receiver Event Generation from PHY Event Mask Descrip...

Page 1153: ...nchronization code into the CSI2 data stream CSI2_CTx_IRQSTATUS 1 FE_IRQ CSI2_CTx_IRQENABLE 1 FE_IRQ Frame end This interrupt is triggered on the detection of a frame end synchronization code into the CSI2 data stream CSI2_CTx_IRQSTATUS 2 LS_IRQ CSI2_CTx_IRQENABLE 2 LS_IRQ Line start This interrupt is triggered on the detection of a line start synchronization code into the CSI2 data stream CSI2_CT...

Page 1154: ...urations and limitations details The camera ISP master port is connected to the L3 interconnect and the slave port is connected to the L4 interconnect from the camera ISP point of view commands are output from the camera ISP to the L3 and data are input output From the camera ISP point of view commands are input from the L4 to the camera ISP and data are input output Figure 6 53 shows the camera I...

Page 1155: ...cessing front end CSI2C VP_HS VP_VS P_DATA 11 0 VP_PCLK EOF CSIPHY2 Primary camera CSI2 up to 2 data lanes Secondary camera CCP2 or CSI1 1 data lane DATA 32 RST DATA 32 RST W External sensor CSI2 or CCP2 up to 2 data lanes External sensor CSI2 or CCP2 1 data lane DATA 32 DATA 32 CAM_IRQ0 CAM_ICLK CAM_FCLK CAM_IRQ1 CSI2_96M_FCLK camisp 025 camera ISP Public Version www ti com Camera ISP Functional ...

Page 1156: ...ugh the resizer Statistics collection modules SCM H3A and histogram modules that provide statistics on the incoming images to help designers of camera systems The hardware 3A module supports the control loops for AF AWB and AE by collecting metrics about RAW image data from the CCDC The histogram module bins input color pixels depending on the amplitude and provide statistics required to implement...

Page 1157: ...a Figure 6 54 shows the data path of images in RAW format Figure 6 54 Camera ISP Data Path RAW RGB Images RAW data are processed through the CCDC module and are directly pipelined to the preview engine 1 Another way is to output directly from the CCDC to memory C In the preview block the format is converted from RAW data to YUV4 2 2 The data can be output to memory 4 or pipelined to the resizer 2 ...

Page 1158: ...o memory C or pixel dynamic must be reduced to RAW8 or RAW10 by the bridge lane shifter module before the CCDC 6 4 1 1 2 Camera ISP YUV4 2 2 Data Figure 6 55 shows the data path of images in YUV4 2 2 format Figure 6 55 Camera ISP Data Path YUV4 2 2 Images When the sensor output format is YUV4 2 2 the CCDC block is directly pipelined to the resizer 1 or output directly to the memory C The rescaled ...

Page 1159: ...D and 2D addressing mode False synchronization code protection Ping pong mechanism for double buffering Support of RGB RAW YUV and JPEG formats Support of DPCM compression and decompression Image read from memory RAW formats supported 6 4 2 2 Camera ISP CSI1 CCP2B Receiver Functional Description 6 4 2 2 1 Camera ISP CSI1 CCP2B Overview Figure 6 57 is the CSI1 CCP2B receiver top level block diagram...

Page 1160: ... is controlled by a SCM registers SCM CONTROL_CAMERA_PHY_CTRL SCM CONTROL_CAMERA_PHY_CTRL 4 CSI1_RX_sel CSIPHY1 data is sent to ISP CSI1 CCP2B if set to 0 CSIPHY2 data is sent to ISP CSI1 CCP2B if set to 1 For information about initializing the CSIPHY associated with CSI1 CCP2B see Section 6 5 2 2 Camera ISP CSIPHY Initialization for Work With CSI1 CCP2B Receiver See Section 6 2 3 for further conn...

Page 1161: ...CP2B Protocol Layer The CSI1 CCP2B protocol layer defines how image sensor data are transported to the physical layer The CSI1 CCP2B protocol layer transports logical channels which are composed of frames A frame comprises embedded data and image sensor data Each frame is clearly identified by unique synchronization codes frame start frame end line start and line end Image sensor data can have mul...

Page 1162: ...he receiver either removes the additional bits or adds dummy bits The next LS synchronization code resynchronizes the state machine to normal behavior A shifted line end LE synchronization code triggers an LE_IRQ event Frame end shifted code The receiver either removes the additional bits or adds dummy bits The next FS synchronization code resynchronizes the state machine to normal behavior A shif...

Page 1163: ...SC and LEC synchronization codes are never used when the CSI1 CCP2B interface transports a JPEG bitstream only FSC and FEC synchronization codes are used Figure 6 60 Camera ISP CSI1 CCP2B Frame Structure JPEG8 Data Format Data A frame comprises embedded data and image sensor data Figure 6 61 shows the location of embedded data and image sensor data in the frame The following definitions apply 0 or...

Page 1164: ...chronization code protection is implemented the receiver ensures that the embedded data contains no synchronization codes Pixel data Pixel data can be compressed Pixel data comprises pixels of the same data format False synchronization code protection is implemented the receiver ensures that the pixel data contains no synchronization codes 6 4 2 2 4 1 2 Camera ISP CSI1 CCP2B Logical Channels Ident...

Page 1165: ...mming model allows these values to be overwritten Table 6 23 Camera ISP CSI1 CCP2B Logical Channel Values in Synchronization Codes Logical Channel Value Logical channel 0 0x0 Logical channel 1 0x1 Logical channel 2 0x2 Logical channel 3 0x3 Logical channel 4 0x4 Logical channel 5 0x5 Logical channel 6 0x6 Logical channel 7 0x7 Muxing The logical channels are interleaved at the line level or at the...

Page 1166: ...1 RAW1 RAW1 RAW1 RAW1 RAW1 6 PAC DPC PAC DPC PAC PAC DPC PAC DPC PAC DPC 0 0 PAC 2 2 PAC 4 6 K M K DP M_AD K DP K M K DP M_AD K DP M K K CM V CM_A CM V CM_A DV DV RAW6 RAW6 PACK RAW6 X X DPCM RAW6 X X PACK DPCM RAW6 X X DPCM _ ADV RAW6 X X PACK DPMC _ ADV RAW7 RAW7 PACK RAW7 X X DPCM RAW7 X X PACK DPCM 1166Camera Image Signal Processor SWPU177N December 2009 Revised November 2010 Copyright 2009 20...

Page 1167: ...RAW1 RAW1 RAW1 RAW1 RAW1 6 PAC DPC PAC DPC PAC PAC DPC PAC DPC PAC DPC 0 0 PAC 2 2 PAC 4 6 K M K DP M_AD K DP K M K DP M_AD K DP M K K CM V CM_A CM V CM_A DV DV RAW7 X X DPCM _ ADV RAW7 X X PACK DPMC _ ADV RAW8 RAW8 X X DPCM RAW8 x x DPCM 12 RAW8 x x ALAW 10 RAW1 X X X X X X X X X 0 RAW1 X X X X X X X X X 0 PACK 1167 SWPU177N December 2009 Revised November 2010 Camera Image Signal Processor Copyri...

Page 1168: ...RAW1 2 PACK RAW1 4 RAW1 6 NOTE Video processing hardware and memory destinations are mutually exclusive Table 6 25 summarizes supported modes for memory to video port operations Table 6 25 Camera ISP CSI1 CCP2B Memory to Video Processing Hardware Supported Formats Memory Input Video Port Output RAW6 RAW7 RAW8 RAW10 RAW12 RAW14 RAW16 RAW6 x RAW6 PACK x RAW6 DPCM x RAW6 PACK x DPCM RAW6 DPCM_ADV x R...

Page 1169: ...utput RAW6 RAW7 RAW8 RAW10 RAW12 RAW14 RAW16 RAW7 PACK X DPCM_ADV RAW8 x RAW8 DPCM X RAW8 DPCM12 x RAW8 ALAW10 X RAW10 X RAW10 PACK X RAW12 X RAW12 PACK X RAW14 x RAW16 x NOTE The RAW6 and RAW7 data formats do not apply to the MIPI CSI1 compatible mode 1169 SWPU177N December 2009 Revised November 2010 Camera Image Signal Processor Copyright 2009 2010 Texas Instruments Incorporated ...

Page 1170: ...bit field specifies the horizontal size of the image The pixels after the right boundary of the image are not read from memory When data are sent to the video port throughput is imposed by the selected video port clock Otherwise it is imposed by the selected interconnect read port clock The interconnect read rate can be throttled limiting the maximum data read speed for memory to memory operation ...

Page 1171: ...7 8 9 c 2 3 4 5 6 7 8 9 d 0 1 RAW10 packed a 0 1 2 3 4 5 6 7 8 9 b 0 1 2 3 4 5 6 7 8 9 0 s 0 s RAW10 unpacked addr 0 addr 1 addr 2 addr 3 RAW12 packed RAW12 unpacked a 0 1 2 3 4 5 6 7 8 9 10 11 0 s 0 s b 0 1 2 3 4 5 6 7 8 9 10 11 d 2 3 4 5 6 7 8 9 a 0 1 b 0 1 c 0 1 a 2 3 4 5 6 7 8 9 e 2 3 4 5 6 7 8 9 f 2 3 4 5 6 7 8 9 g 2 3 4 5 6 7 8 9 h 2 3 4 5 6 7 8 9 h 0 1 e 0 1 f 0 1 g 0 1 i 2 3 4 5 6 7 8 9 j ...

Page 1172: ...start on 128 bit boundaries 6 4 2 2 5 2 Camera ISP CSI1 CCP2B Memory Read Port Burst Generation The hardware always uses the largest possible burst size according to the setup The amount of data read from memory can be higher than what is actually used by the CCP2B receiver Only full 64 bit words are read Figure 6 65 shows the data organization in memory Figure 6 65 Camera ISP CSI1 CCP2B Data Orga...

Page 1173: ... width restrictions in Table 6 27 apply Table 6 27 Camera ISP CSI1 CCP2B Output Width Restrictions in Memory to Memory Operation Format Bits pix Width Multiple of 1 Note RAW6 8 1 Full 32 bit words are written at the end of the line This last word can eventually include 0s RAW6 PACK 6 1 RAW7 8 1 RAW7 PACK 7 1 RAW8 8 1 RAW10 16 1 RAW10 PACK 10 16 RAW12 16 1 Same constraints as RAW8 RAW12 PACK 12 8 1...

Page 1174: ... 0xB RAW10 RAW6 6 40 Yes DPCM compression DPCM 0xC RAW7 EXP8 8 14 Yes 0xD RAW7 DPCM10 16 128 Yes DPCM decompression EXP16 0xE RAW7 DPCM10 N A data are sent to N A Yes DPCM decompression VP VP 0xF RAW10 RAW6 8 25 Yes DPCM compression DPCM EXP8 0x10 RAW8 this mode can 8 0 Yes be used to output RAW6 and RAW7 0x11 RAW8 DPCM10 16 100 Yes DPCM decompression EXP16 0x12 RAW8 DPCM10 N A data are sent to N ...

Page 1175: ...nsion to 16 bits padding with alpha or zeros CCP2_LCx_CTRL 15 8 ALPHA can be used to set an alpha value For RGB444 EXP16 data_out 31 28 ALPHA 3 0 data_out 15 12 ALPHA 3 0 EXP32 Data expansion to 32 bits padding with alpha CCP2_LCx_CTRL 15 8 ALPHA can be used to set an alpha value For RGB888 EXP32 data_out 31 24 ALPHA 7 0 FSP False synchronization code protection decoding Applies only to JPEG8 data...

Page 1176: ...figuration Error detection and correction by the protocol engine DMA engine integrated with dedicated FIFO Streaming 1D and 2D addressing modes Up to eight contexts to support eight dedicated configurations of virtual channel ID and data types Ping pong mechanism for double buffering JPEG support for unknown length transfer no extraction of the thumbnail All primary and secondary MIPI defined form...

Page 1177: ...e CSI2_COMPLEXIO_CFG1 register also contain a bit field affecting PHY power management For information about initializing the CSIPHY associated with CSI2 see Section 6 5 2 2 Camera ISP CSIPHY Initialization for Work With CSI2 Receiver 6 4 3 4 Camera ISP CSI2 ECC and Checksum Generation The CSI2 receiver includes an ECC in the packet header and a checksum in the packet footer for long packet transm...

Page 1178: ...M and A law Compression The CSI2 receiver has a funtionality to have an image in raw format transcoded Transcoding is mainly used to reduce memory footprint and bandwith when The sensor does not support DPCM compression So by transcoding A law and DPCM compressed pixels only occupy 6 7 or 8 bits pixel of storage Digital zoom is used In fact Data that is not going to be used by further processing d...

Page 1179: ...l format provided by the sensor Formats not listed in the following table are not supported for transcoding Table 6 30 Camera ISP Pixel Format Modes CSI2_CTx_CTRL2 CSI2 Data Format Cropping Engine Input DPCM Decomp Enabled Video Port Enabled 9 0 Format 0x028 RAW6 RAW6 0x068 RAW6 EXP8 0x029 RAW7 RAW7 0x069 RAW7 EXP8 0x02A RAW8 RAW8 0x12A RAW8 VP Yes 0x02B RAW10 0x0AB RAW10 EXP16 0x0E8 RAW6 DPCM10 V...

Page 1180: ...RAW7 DPCM12 VP Yes Yes 0x02D RAW14 0x0AD RAW14 EXP16 RAW14 0x12D RAW14 VP Yes Image cropping parameters are controlled by software Figure 6 68 provides a graphical representation of the cropping operation Figure 6 68 Camera ISP CSI2 Frame Cropping NOTE Hardware does not check for validity of the settings The following rules must be respected CSI2_CTx_TRANSCODEH 12 0 HSKIP CSI2_CTx_TRANSCODEH 28 16...

Page 1181: ...utput RAW6 0 Disabled Yes RAW10 0 Disabled Yes 1 DPCM10 RAW8 1 DPCM10 RAW8 Yes 2 DPCM12 RAW8 2 DPCM12 RAW8 3 ALAW10 RAW8 3 ALAW10 RAW8 Yes 4 RAW8 4 RAW8 5 RAW10 EXP16 5 RAW10 EXP16 Yes 6 RAW10 6 RAW10 Yes 7 RAW12 EXP16 7 RAW12 EXP16 8 RAW12 8 RAW12 9 RAW14 9 RAW14 RAW7 0 Disabled Yes RAW12 0 Disabled Yes 1 DPCM10 RAW8 1 DPCM10 RAW8 2 DPCM12 RAW8 2 DPCM12 RAW8 Yes 3 ALAW10 RAW8 3 ALAW10 RAW8 4 RAW8...

Page 1182: ... a short packet is stored in the SHORT_PACKET_IRQ bit in the CSI2_IRQSTATUS 13 register Logging cannot be disabled but users can set the corresponding bit in the CSI2_IRQENABLE register to prevent event generation at a higher level The application reads the CSI2_SHORT_PACKET register before the next short packet with a code between 0x8 and 0xF There is a single register for capturing the generic s...

Page 1183: ...ER_IRQ event The CSI2_CTx_CTRL1 1 LINE_MODULO bit configures how the LINE_NUMBER event is generated 0 The event is generated one time by frame 1 The event is generated modulo LINE_NUMBER the event can be generated more than once in a frame During a frame capture the CSI2_CTx_CTRL2 31 16 FRAME_NUMBER bit field shows the number that identifies the frame received 6 4 3 8 Camera ISP CSI2 DMA Engine Th...

Page 1184: ...G_PONG buffer 6 4 3 8 1 Camera ISP CSI2 Progressive Frame to Progressive Storage After each line a new start line address is computed depending on the value of the CSI2_CTx_DAT_OFST 15 5 OFST bit field If OFST 0 the new line starts immediately after the last pixel data are written contiguously in memory Otherwise the OFST value sets the offset between the first pixel of the previous line and the f...

Page 1185: ...wo serial data lanes into a bit stream compatible with the CSI2 receiver and one clock lane The two CSIPHY1 and CSIPHY2 have identical functionality only difference is that CSIPHY1 is limited to one data line Figure 6 72 shows the CSIPHY overview diagram Figure 6 72 Camera ISP CSI2 PHY Overview The CSI2_COMPLEXIO1_IRQSTATUS register logs the CSIPHY event The events that occur are Line power state ...

Page 1186: ..._RX_MODE_IO1 bit field sets the CSIPHY in RxMode or in NoRxMode stopped mode The FORCE_RX_MODE_IO1 bit is automatically reset to 0 by hardware when the counter ends and the FSM returns to NoRxMode Three bit fields CSI2_TIMING 14 STOP_STATE_X16_IO1 CSI2_TIMING 13 STOP_STATE_X4_IO1 and CSI2_TIMING 12 0 STOP_STATE_COUNTER_IO1 configure the delay between line stop mode and CSIPHY stop mode The delay r...

Page 1187: ... This predictor uses four previous pixel values when the prediction value is evaluated This means that also the other color component values are used when the prediction value has been defined The preferable usage is that simple predictor is used with 10 bits to 8 bits conversion 10 8 10 and the advanced predictor is used with 10 bits to 7 bits and 10 bits to 6 bits conversions 10 7 10 and 10 6 10...

Page 1188: ...re 6 75 Camera ISP Timing Control block diagram 6 4 4 2 1 Camera ISP Timing Control Generator The timing coontrol generates the cam_xclka and cam_xclkb clocks based on the CAM_MCLK frequency which can be up to 216 MHz The cam_mclk is used only by the clock generator the cam_xclka and cam_xclkb clocks are not used internally by the camera ISP The clock divider is programmable The possible frequenci...

Page 1189: ...ntrol signal generator can be synchronized either on the vertical synchronization signal coming from the CSI2A VP_VS from CSI2A CSI2C VP_VS from CSI2C CSI1 CCP2B VP_VS from CSI1 CCP2B or PARALLEL interface cam_vs or on an externally generated cam_global_reset signal A multiplexer controls which of the CSI2A CSI1 CCP2B or CSI2C and PARALLEL interface drives control signal generation This multiplexe...

Page 1190: ...ted in the CSI2A CSI1 CCP2B CSI2C receivers on detection of a frame start code FSC followed by a frame end code FEC A new frame is detected in the CCDC module by using the falling edge of the vertical synchronization signal at the input of the CCDC module NOTE The rising edge of the vertical synchronization signal and the vertical synchronization polarity settings inside the CCDC cannot be used Th...

Page 1191: ... activation length is programmable The counter is decreased at every CNTCLK clock cycle When the counter reaches 0 the signal is deasserted and the global reset enable bit is disabled TCTRL_CTRL 29 GRESETEN bit If the activation length is set to 0 the control signal is not asserted and the control signal enable bit is disabled The polarity of the cam_global_reset signal can be selected TCTRL_CTRL ...

Page 1192: ...ster Table 6 35 describes the different configurations Table 6 35 Camera ISP Bridge Lane Shifter Sensor Connected to Data Lane Shifter 0 Data Lane Shifter 1 Data Lane Shifter 2 Data Lane Shifter 3 Note 8 bits 7 0 8 bits 6 bits 4 bits 2 bits 9 2 10 bits 8 bits 6 bits 4 bits 11 4 12 bits 10 bits 8 bits 6 bits 13 6 14 bits 12 bits 10 bits 8 bits CSI2 only 10 bits 9 0 10 bits 8 bits 6 bits 4 bits 11 2...

Page 1193: ...zation signals are provided by either the sensor or the camera ISP This mode works with 8 10 11 12 and 14 bit data It supports both progressive and interlaced image sensor modules NOTE Input from CSI1 CCP2B is limited to 12 bits and input from CSI2 is limited to 14 bits ITU mode In this mode the image sensor module provides an ITU R BT 656 compatible data stream Horizontal and vertical synchroniza...

Page 1194: ...tter submodules Output is transmitted to the computing statistics H3A histogram modules for further processing JPEG still image capture data is not processed by the internal CCDC modules The data flow is sent to memory through the SBL Circular buffer and MMU to be read by the external JPEG CODEC RAW still image capture data flow typically passes through the optical clamp black level compensation f...

Page 1195: ... input pixel as a first step The goal is to remove an offset caused by the sensor technology The averaging circuit takes an average of masked black pixel values from the image sensor averaging pixels at the start CCDC_CLAMP 24 10 OBST of each line CCDC_CLAMP 30 28 OBSLEN and for the number of indicated lines CCDC_CLAMP 27 25 OBSLN plus an optional gain adjustment CCDC_CLAMP 4 0 OBGAIN and subtract...

Page 1196: ... requires the camera driver to have information about the image sensor faulty pixel number and positions This method leads to the best image quality However if the position of the faulty pixels is unavailable to the camera driver it can apply another faulty pixel correction algorithm in the preview module This algorithm leads to lower quality images The CCDC module implements an optional CCDC_FPC ...

Page 1197: ... output formatter In addition the CCDC_SYN_MODE 17 WEN bit must be enabled to store the output to memory The data formatter and video port interfaces are only 10 bits wide therefore the input data must be adjusted as it enters these modules For flexibility the bits to be retained can be selected by CCDC_FMTCFG 14 12 VPIN The reformatter decomposes each input line into multiple output lines with ne...

Page 1198: ...le reformatted lines occurs as the next input line is being read from the sensor and reformatted to ensure that all output lines are fully constructed The reformatter is subject to the restrictions listed in Table 6 36 Table 6 36 Camera ISP CCDC Reformatter Output Limitations Number of Output Lines Input Line Max Pixels Output Line 1 4 1376 2 2 1376 3 1 1376 4 1 1376 The reformatter derives its fl...

Page 1199: ...ed gain map reduces memory requirements for storage and bandwidth requirements for access of the gain maps in external memory Features supported The memory stored gain map is MxN downsampled M being the horizontal sampling factor N being the vertical sampling factor M and N being 4 8 16 32 64 independently and N M 8 bit entries in the gain map in U8Q8 U8Q7 U8Q6 and U8Q5 format with optional base o...

Page 1200: ...ilter Two pixels on the left and two pixels on the right of each line are cropped if the filter is enabled Use of the LPF is intended for bandwidth reduction if culling is enabled NOTE For YUV data the LPF must be disabled CCDC_SYN_MODE 14 LPF 0x0 Culling An optional culling operation can be enabled CCDC_CULLING register This operation allows selected pixel data to be culled deleted from a line CC...

Page 1201: ...sing stage Using this causes data width to be reduced to 8 bits and allows packing to 8 bits pixel when saving to memory Because data resolution can be greater than 10 bits at this stage the 10 bits for input to the A Law operation must be selected CCDC_ALAW 2 0 GWDI The preview module has an inverse A Law table A Law decompression option so that this nonlinear operation can be reversed if this sa...

Page 1202: ...escription Register Description CCDC_SDOFST 14 FIINV Invert interpretation of the field ID signal CCDC_SDOFST 13 12 FOFST Offset in lines of field 1 CCDC_SDOFST 11 9 LOFTS0 Offset in lines between even lines on even fields field 0 CCDC_SDOFST 8 6 LOFTS1 Offset in lines between odd lines on even fields field 0 CCDC_SDOFST 5 3 LOFTS2 Offset in lines between even lines on odd fields field 1 CCDC_SDOF...

Page 1203: ... Input image LINE0 LINE3 LINE2 LINE1 Output image LINE2 LINE0 LINE1 Public Version www ti com Camera ISP Functional Description Figure 6 83 shows an example of sample formats of input and output images Figure 6 83 Camera ISP CCDC Line Output Control Sample Formats of Input and Output Images Output Format The data bits comprising each pixel are stored in the lower bits of a 16 bit memory word and t...

Page 1204: ... 0 13 bit 0 Pixel 1 0 Pixel 0 12 bit 0 Pixel 1 0 Pixel 0 11 bit 0 Pixel 1 0 Pixel 0 10 bit 0 Pixel 1 0 Pixel 0 9 bit 0 Pixel 1 0 Pixel 0 8 bit 0 Pixel 1 0 Pixel 0 8 bit packed Pixel 3 Pixel 2 Pixel 1 Pixel 0 NOTE YUV data is stored in memory in packed YUV422 mode using two pixels per 32 bits as shown in Table 6 39 1204Camera Image Signal Processor SWPU177N December 2009 Revised November 2010 Copyr...

Page 1205: ...CDC Memory Output Format for YUV Data Upper Word Lower Word Memory Address MSB 31 LSB 16 MSB 15 LSB 0 N Y1 Cr0 Y0 Cb0 N 1 Y3 Cr1 Y2 Cb1 N 2 Y5 Cr2 Y4 Cb2 1205 SWPU177N December 2009 Revised November 2010 Camera Image Signal Processor Copyright 2009 2010 Texas Instruments Incorporated ...

Page 1206: ...filter array complementary color filter array Super CCD Honeycom sensors Horizontal averaging by a factor of 1 2 4 or 8 in the horizontal direction The preview module can output a maximum of only 4096 pixels horizontally due to fixed memory line sizes A Law decompression Transforms nonlinear 8 bit data to 10 bit linear data The CCDC module can perform A Law compression Noise reduction and faulty p...

Page 1207: ... engine receives RAW image video data from the video port interface through the CCDC or from the read buffer interface through the memory PRV_PCR 2 SOURCE When the source of input data is the CCDC the input data is always 10 bits wide When the source of input data is memory read buffer interface the data can be 8 or 10 bits wide Use the PRV_PCR 4 WIDTH field to set the input data width The 8 bits ...

Page 1208: ...ntal distance of two pixels of the same color for both even and odd lines Valid output of the input formatter averager is either 8 or 10 bits wide Figure 6 85 shows the horizontal distances for different patterns Figure 6 85 Camera ISP VPBE Preview Horizontal Distances for Different Patterns 6 4 7 1 4 Camera ISP VPBE Preview Dark Frame Write The preview engine is capable of capturing and saving a ...

Page 1209: ...ntains a horizontal median filter that can help reduce temperature induced noise effects The input and output of the horizontal median filter are 10 bits wide U10Q0 NOTE Line width reduction If the horizontal median filter is enabled the preview engine reduces the length of the output line of this stage by 4 pixels 2 starting pixels left edge and 2 ending pixels right edge For example if the input...

Page 1210: ...nd bottom edges are truncated in the Bayer conventional and other modes If the CFA format is 2 downsampling in both horizontal and vertical directions only 2 lines at the top and bottom of the image are truncated The two left and right most pixels are processed 6 4 7 1 11 Camera ISP VPBE Preview Black Adjustment The CFA interpolation output is three pixels red blue and green values and this is fed...

Page 1211: ...on Luminance Enhancement Chrominance Suppression Contrast and Brightness and 4 2 2 Downsampling and Output Clipping 6 4 7 1 14 1 RGB to YCbCr Conversion The RGB to YCbCr conversion module has a 3x3 square matrix and converts the RGB color space of the image data into the YCbCr color space In this module the following calculation is performed using the contents of the PRV_CSC0 PRV_CSC1 PRV_CSC2 and...

Page 1212: ...ximum Y and C values and 0 for the minimum Y and C values 6 4 7 1 15 Camera ISP VPBE Preview Write Buffer Interface The output of the preview engine may be passed directly to the Resizer PRV_PCR 19 RSZPORT and or written to memory PRV_PCR 20 SDRPORT If the output is written to memory the write address PRV_WSDR_ADDR and line offset PRV_WADD_OFFSET must be on 32 byte boundaries The output format of ...

Page 1213: ...aps 0 25 to 0 5 7 taps OW 2048 OW 2048 Vertical Resizer ratio 0 5 to 4 4 taps OW 4096 OW 4096 The horizontal resizer output rate must not exceed half the functional clock Moreover the horizontal resizer output rate must not exceed 100M pixels s This limitation applies only for the on the fly processing input source Flexible resizing ratios Independent resizing factors for the horizontal and vertic...

Page 1214: ... that the input sizes specified by the RSZ_IN_START and RSZ_IN_SIZE registers are less than or equal to the output from the preview engine or CCDC otherwise incorrect hardware operation may occur RSZ_SDR_INADD and RSZ_SDR_INOFF must be programmed to be 0x0 in this mode Also the output ports of the CCDC CCDC_SYN_MODE 19 SDR2RSZ and preview engine PRV_PCR 19 RSZPORT to the resizer must be configured...

Page 1215: ...e output width RSZ_OUT_SIZE 11 0 HORZ must be at least 16 pixels and be even so that the same number of Cb and Cr components is outputted Due to the vertical memory size constraint the output width RSZ_OUT_SIZE 11 0 HORZ cannot be greater than 4096 pixels if the vertical resizing ratio is between 1 2 and 4 RSZ_CNT 19 10 VRSZ 1 512 1650 pixels wide if the vertical resizing ratio is between 1 2 and ...

Page 1216: ...here P is the number of phases Figure 6 89 shows the resizer functionality Figure 6 89 Camera ISP VPBE Resizer Functionality Figure 6 90 shows a model of the resolution of the noninteger downsampling ratio The interpolated output from the filter is upsampled and replicated 256 P times before it is downsampled by the RSZ factor Figure 6 90 Camera ISP VPBE Resizer Approximation Scheme This implement...

Page 1217: ...d 24 6 0 3 0 25 1 1 26 2 2 27 3 3 28 7 0 4 29 1 5 30 2 6 31 3 Not used The indexing scheme of coefficients is oriented for dot product or inner product rather than for impulse response In other words the first data point contributing to a particular output is multiplied by the coefficient associated with tap 0 and the last data point is multiplied by the coefficient associated with tap 3 or tap 6 ...

Page 1218: ...unding issues in the algorithm Table 6 43 lists the input size calculations derived from the algorithm description in Section 6 4 7 2 5 The input width and height parameters must be programmed strictly according to these equations otherwise incorrect hardware operation may occur Table 6 43 Camera ISP VPBE Resizer Input Size Calculations 8 Phase 4 Tap Mode 4 Phase 7 Tap Mode RSZ_IN_SIZE 12 0 HORZ 3...

Page 1219: ...e of the 8 phases is calculated by rounding the fine input pointer to the nearest 1 8 pixel The output pixel is calculated by the dot product of the coefficients of the phase filter selected by the coarse input pointer and the appropriate four input pixels Figure 6 93 shows a pseudo code description of the resizer algorithm in the 4 tap 8 phase mode Figure 6 93 Camera ISP VPBE Resizer Pseudo Code ...

Page 1220: ...input pixel location in whole pixels see Section 6 4 7 2 3 Camera ISP VPBE Resizer Input and Output Interfaces and the starting phase in 1 2 pixel RSZ_CNT 22 20 HSTPH are programmed through the resizer registers A fine input pointer is maintained in 1 256 pixel precision A coarse input pointer and a pixel input pointer are computed for each output based on the fine input pointer The coarse input p...

Page 1221: ...pendently of the RSZ_CNT 22 20 HSTPH parameters However filtering with luma is intended only for downsampling and bilinear interpolation is intended only for upsampling For horizontal resizing of Y Cb Cr in a combined filtering flow the algorithm is modified as shown in the following algorithm descriptions Filter Chroma With Luma 4 Tap 8 Phase Mode For i 0 i output_width i output width depends of ...

Page 1222: ...Z 1 NOTE The chroma input values are internally replicated to realize 1 2 upsampling to line up with luma input values Only required chroma outputs are computed they correspond to even luma outputs Bilinear Interpolation 4 Tap or 7 Tap For the bilinear interpolation flow of chroma horizontal resizing the algorithm is adapted as follows For the bilinear interpolation option it is not necessary to r...

Page 1223: ...rocessing Example for 1 2 56 Horizontal Resize Output Y0 Cb0 Cr0 Y1 Y2 Cb2 Cr2 Y3 Y4 Cb4 Cr4 Y5 fip hrsz 256 156 56 44 144 244 cip fip 16 5 8 5 2 1 5 8 pip cip 3 1 0 0 0 1 1 2 coef ph cip 7 0 3 6 1 5 0 Inputs needed chroma Y0 Cb0 Cr0 Y0 Y0 Cb0 Cr0 Y1 Y1 Cb0 Cr0 Y2 filtered like luma Y1 Cb2 Cr0 Y1 Y1 Cb0 Cr0 Y2 Y2 Cb2 Cr2 Y3 Y2 Cb2 Cr2 Y2 Y2 Cb2 Cr2 Y3 Y3 Cb2 Cr2 Y4 Y3 Cb2 Cr2 Y3 Y3 Cb2 Cr2 Y4 Y4 C...

Page 1224: ...axel a paxel is defined as a two dimensional block of pixels Accumulate the maximum focus value of each line in a paxel Accumulation of the maximum focus value of each line in a paxel Accumulation mode Accumulation sum mode instead of peak mode Accumulation of focus value in a paxel Up to 36 paxels windows in the horizontal direction and up to 128 paxels windows in the vertical direction Programma...

Page 1225: ...y the host processor to adjust various parameters for processing image data The following features are supported Flexible input Input data can come from the RAW image sensor through the CCDC module or from memory Color separate gain A digital gain per color component can be applied before histogram computation Histogram computation The module performs pixel binning of the incoming RAW image data E...

Page 1226: ... for every 16 bits the DATSIZ bit must be cleared Likewise if memory contains one pixel for every 16 bits the DATSIZ bit must be cleared The input memory address HIST_RADD and line offset HIST_RADD_OFF registers are used to specify the location of the input frame in memory Both of these registers should be aligned on 32 byte boundaries The frame input width and height are configured using the HIST...

Page 1227: ...era ISP Histogram Regions and Bins Number of Bins Number of Regions Allowed 256 1 128 2 64 4 32 4 As indicated by Table 6 46 up to four overlapping regions can be designated within the frame Each region is defined by the horizontal starting HIST_Rn_HORZ 29 16 HSTART and ending HIST_Rn_HORZ 13 0 HEND pixels and the vertical starting HIST_Rn_VERT 29 16 VSTART and ending HIST_Rn_VERT 13 0 VEND lines ...

Page 1228: ...e write buffer 1 port Transfer input data to the CSI1 CCP2B from the read buffer This port is shared with the PREVIEW module input data read port Interface to the preview module Collects output data from the preview engine in the write buffer 1 port Transfer input data to the PREVIEW engine from the read buffer 1 ports This port is shared with CSI1 CCP2B data read port Transfer dark frame subtract...

Page 1229: ... Diagram Figure 6 98 shows the central resource SBL It comprises WBL and RBL blocks read and write buffers and arbitration logic The VBUSM data width to the memory is 64 bits 1229 SWPU177N December 2009 Revised November 2010 Camera Image Signal Processor Copyright 2009 2010 Texas Instruments Incorporated ...

Page 1230: ...Command arbiter Write mem arbiter Read mem arbiter Central resource shared buffer logic WBL CSI2a Public Version Camera ISP Functional Description www ti com Figure 6 98 Camera ISP Shared Buffer Logic Block Diagram NOTE Red Reads Blue Writes 1230 Camera Image Signal Processor SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 1231: ...ut port CCDC lens shading compensation input port RESIZER WRITE P5 1024 4DUs RESIZER output line 1 port WRITE P6 1024 4DUs RESIZER output line 2 port WRITE P7 1024 4DUs RESIZER output line 3 port WRITE P8 1024 4DUs RESIZER output line 4 port READ P12 1024 4DUs RESIZER input port H3A WRITE P10 512 2DUs H3A output AF port WRITE P11 512 2DUs H3A output AE AWB port HIST READ P14 512 2DUs HIST input po...

Page 1232: ...e arbitrated independently A total of 8 commands can be active at a time When a new slot opens the highest priority transfer enters the command queue RBLs WBLs are ensured access to the read write buffer memories at least once every other cycle NOTE The hardware uses burst All bursts are precise the total number of transfers in the burst is known at the start of the burst All writes are posted 6 4...

Page 1233: ...s HIST input Each write request register provides the following information Current byte count Number of bytes in the block of data for this command up to 256 bytes Data ready Block of data confirmed by the module Data sent Data sent to the destination and waiting for status Upper 20 bits of the address Each read request register provides the following information Valid Read requested from the mod...

Page 1234: ...on when the camera ISP reads data through the CSIb receivers flexible input At a given time a certain number of physical buffers are available for the processor Depending if the circular buffer is configured in read or write mode the processor can respectively write or read those physical buffers When the number of physical buffers to be processed by the processor increases the number of physical ...

Page 1235: ...to W 3 Mapped to W 0 Virtual space END Mapped to W 1 Mapped to W 2 Mapped to W 3 camisp 165 Public Version www ti com Camera ISP Functional Description Figure 6 99 Camera ISP Circular Buffer Single Slice Buffer Write Mode Physically this circular buffer is typically in the SDRAM The virtual space is defined by a start and an end address The physical buffer is defined by a start address a window si...

Page 1236: ...tween the resizer and preview module goes though the SBL and data is internally buffered The SBL can buffer up to 4 DUs between the PREVIEW and RESIZER module In other words when the input of the PREVIEW module is stalled the RESIZER receives up to 2K bytes before it stalls The SBL can store up to four DUs for each of the RESIZERs write ports The count of ports used by the resizer depends on the v...

Page 1237: ...s as done In this example the stall command is released when the CODEC has completed processing W0 and W1 The camera ISP resumes writing into W3 NOTE Software can control the minimum full window count to issue the stall command using the CBUFFx_CTRL 7 4 BCF register Setting this value to 1 or 2 in this example may negatively affect the performance because only up to two or three windows can be use...

Page 1238: ...ust be triggered in advance Otherwise the camera ISP may prefetch invalid data The last moment when the CSI1 CCP2B interconnect read master port can be safely stalled is when the physical read buffer still contains 1K byte of valid data The camera ISP may or may not then read the remaining data into its internal SBL buffer The minimum amount of buffered data depends on the circular buffer configur...

Page 1239: ...rform address translation to group 4 contexts together This extends the maximum frame size than can be rotated to the following Table 6 51 Camera ISP Circular Buffer VRFB Extended Supported Frame Size Frame size Aspect ratio 12 5 Mega Pixel 4 3 11 1 Mega Pixel 3 2 9 4 Mega Pixel 16 9 NOTE VRFB context grouping is a standalone feature It cannot be combined with circular buffering or fragmentation T...

Page 1240: ... The current value can be read using the CBUFFx_STATUS 19 16 NW register CPUWx Window in the physical buffer that can be accessed by the CPU Possible values are 0 to allowed window count The current value can be read using the CBUFFx_STATUS 3 0 CPUW register FCOx Start address in the virtual space of the current window This is an internal quantity that cannot be accessed by software OFFSETy This i...

Page 1241: ...ue Lower IDs correspond to higher priorities in case multiple conditions are true For example when the current virtual window of the circular buffer 0 is accessed at least the tests for categories CW_CBUFF0 and ERR_CBUFF0 are true The final category is CW_CBUFF0 because it has a higher priority Further processing depends on the category TRANSPARENT Accesses flow through the module without changing...

Page 1242: ...ccess cancelled Category TRANSPARENT ADDROUT ADDRIN 6 4 10 3 2 4 Camera ISP Circular Buffer Window Fill Level Each time an access is performed into an active window CW_CBUFF0 NW_CBUFF0 CW_CBUFF1 or NW_CBUFF1 the window level is updated The corresponding LEVELy is incremented according to the BYTEEN input of the interconnect port All possible BYTEEN patterns are supported Table 6 56 shows some exam...

Page 1243: ... the first OFFSET 2 x 1 OFFSET 2 x 1 WCx CBUFFx_WINDOWSIZE NOTE WC is the window count defined by the CBUFFx_CTRL 9 8 WCOUNT register 6 4 10 3 3 Camera ISP Circular Buffer CPU Interaction The CBUFF module sets an IRQ_CBUFFx_READY event to inform the CPU that it can access the CPUx window in the physical buffer The CBUFF module cannot monitor CPU accesses to the physical buffer The CPU must indicat...

Page 1244: ...LKSEL_CAM 4 PRCM CM_CLKSEL_CAM CLKSEL_CAM x 2 Enable the cam_fclk clock PRCM CM_FLCKEN_CAM 0 EN_CAM 0x1 3 Enable the cam_iclk clock PRCM CM_ICLKEN_CAM 0 EN_CAM 0x1 Table 6 58 lists the registers to configure the camera subsystem clock configuration step Table 6 58 Camera ISP PRCM Registers Settings Register Name Address Value Description PRCM CM_CLKSEL_CAM 0x4800 4F40 DPLL4 divisor set to 0x4 PRCM...

Page 1245: ...ULLTYPESELECT1 0x0 CONTROL_PADCONF_CAM_D7 19 PULLUDENABLE1 0x1 cam_d9 CONTROL_PADCONF_CAM_D9 8 INPUTENABLE0 0x1 CONTROL_PADCONF_CAM_D9 4 PULLTYPESELECT0 0x0 CONTROL_PADCONF_CAM_D9 3 PULLUDENABLE0 0x1 For CSIPHY2 Pull down on signals through padconf registers cam_d0 CONTROL_PADCONF_CAM_FLD 24 INPUTENABLE1 0x1 CONTROL_PADCONF_CAM_FLD 20 PULLTYPESELECT1 0x0 CONTROL_PADCONF_CAM_FLD 19 PULLUDENABLE1 0x...

Page 1246: ...p on signals through padconf registers cam_d0 CONTROL_PADCONF_CAM_FLD 20 PULLTYPESELECT1 0x1 cam_d1 CONTROL_PADCONF_CAM_D1 4 PULLTYPESELECT0 0x1 csi2_dx0 CONTROL_PADCONF_CSI2_DX0 4 PULLTYPESELECT0 0x1 csi2_dy0 CONTROL_PADCONF_CSI2_DX0 20 PULLTYPESELECT1 0x1 csi2_dx1 CONTROL_PADCONF_CSI2_DX1 4 PULLTYPESELECT0 0x1 csi2_dy1 CONTROL_PADCONF_CSI2_DX1 20 PULLTYPESELECT1 0x1 i The CSIPHY is initialized a...

Page 1247: ...to 0x1 b Assert the ForceRxMode signal i Set CSI2_TIMING 15 FORCE_RX_MODE_IO1 to 0x1 c Power up the CSIPHY i Set CSI2_COMPLEXIO_CFG1 28 27 PWR_CMD to 0x1 d Check that the state status reaches the ON state CSI2_COMPLEXIO_CFG1 26 25 PWR_STATUS 0x1 e Release the ForceRxMode signal i Set CSI2_TIMING 15 FORCE_RX_MODE_IO1 to 0x0 f CSIPHY is initialized and ready active in CSI1 CCP2B mode 6 5 3 Programmi...

Page 1248: ...P2_LCx_CODE CCP2_LCx_STAT_START CCP2_LCx_STAT_SIZE CCP2_LCx_SOF_ADDR CCP2_LCx_EOF_ADDR CCP2_LCx_DAT_SIZE CCP2_LCx_DAT_PING_ADDR CCP2_LCx_DAT_PONG_ADDR CCP2_LCx_DAT_OFST Busy locked registers These registers fields must not be written if the module is busy All register fields not listed as shadowed are busy writable registers 6 5 3 4 Camera ISP CSI1 CCP2B Enable Disable the Hardware The CSI1 CCP2B ...

Page 1249: ...ield forces the burst behavior of the CSI1 CCP2B receiver The module can be forced to perform single 64 bit requests or bursts of 2x 4x and 8x 64 bits The burst size must never exceed the output FIFO size The output FIFO size can be read by reading the CCP2_GNQ 4 2 FIFODEPTH bit field 6 5 3 9 Camera ISP CSI1 CCP2B Debug Mode Use the CCP2_CTRL 7 DBG_EN bit to enable the debug mode During debug mode...

Page 1250: ...d to the CCDC module on 8 bits DATA 7 0 The pixel data are not decompressed The pixel data are transmitted to the CCDC module on 8 bits DATA 7 0 RAW12 VP The incoming data are 12 bits The pixel data are not compressed The embedded data are transmitted to the CCDC module on 12 bits DATA 11 0 The pixel data are reconstructed in the receiver The pixel data are transmitted to the CCDC module on 12 bit...

Page 1251: ...ntrols destination data format EXP8 Data expansion to 8 bits padding with zeros EXP16 Data expansion to 16 bits padding with alpha or zeros CCP2_CTRL 15 8 ALPHA can be used to set an alpha value For RGB444 EXP16 data_out 31 28 ALPHA 3 0 and data_out 27 16 RGB444 data_out 15 12 ALPHA 3 0 and data_out 11 0 RGB444 EXP32 Data expansion to 32 bits padding with alpha CCP2_CTRL 15 8 ALPHA can be used to ...

Page 1252: ...the default values CCP2_LCx_CODE 11 8 FSC CCP2_LCx_CODE 15 12 FEC CCP2_LCx_CODE 3 0 LSC and CCP2_LCx_CODE 7 4 LEC overwrite the 4 LSBs of the 32 bit synchronization codes The default values should not be modified 6 5 3 18 Camera ISP CSI1 CCP2B Status Data The SOF and EOF status lines can be output to memory The SOF and EOF status lines always cover full lines No register settings enable the settin...

Page 1253: ... LSBs are ignored The EOF lines are packed together at the destination address NOTE The CSI1 CCP2B receiver does not modify the data in the SOF and EOF status lines The data are received and written with no modifications 6 5 3 19 Camera ISP CSI1 CCP2B Pixel Data Region Pixel data can be output to memory or to the Video processing hardware The pixel data region covers full lines The CCP2_LCx_DAT_SI...

Page 1254: ...P2_LCx_DAT_OFST register It applies for CCP2_LCx_DAT_PING_ADDR and CCP2_LCx_DAT_PONG_ADDR NOTE The destination pitch must be a multiple of 32 bytes the address 5 LSBs are ignored The use of CCP2_LCx_DAT_OFST is limited to the following destination data formats YUV422 little endian YUV422 big endian RGB444 EXP16 RGB565 RGB888 EXP32 For all other data formats the CCP2_LCx_DAT_OFST register is ignore...

Page 1255: ...by the PREVIEW and CSI1 CCP2B receiver modules The read port must be affected to the CSI1 CCP2B receiver module by writing 1 to the ISP_CTRL 27 SBL_SHARED_RPORTA bit The programmer must ensure that the PREVIEW module does not use this port before switching to the CSI1 CCP2B module The burst size must be configured to 32 x 64 bit bursts using the CCP2_LCM_CTRL 7 5 BURST_SIZE register Firmware must ...

Page 1256: ...and or RSZ At that time the CCDC RSZ FIFO overflow interrupt is raised To prevent the processor from stalling the VP clock must be lowered from CCP2_CTRL 31 15 FRACDIV The CCP2_LCM_CTRL 4 3 READ_THROTTLE register can be used to reduce the bandwidth in memory to memory operation to prevent system overload It has no effect when data are sent to the video port If the memory write port is used the des...

Page 1257: ...gister 32 configuration bus clock pulses to complete the PHY reset sequence 6 5 4 3 Camera ISP CSI2 Enable Video Picture Acquisition To start a video picture acquisition perform the following steps 1 Reset the CSI2 receiver module see Section 6 5 4 2 Reset Management 2 Configure the module power management Set the CSI2_SYSCONFIG 13 12 MSTANDBY_MODE bit field to 0x2 so the module tries to enter sma...

Page 1258: ... frame address in memory If not using a double buffer mechanism the ping and pong addresses must be equal so that all frames are stored at the same memory address Set the CSI2_CTx_DAT_OFST 15 5 OFST bit field to 0x0 so consecutive lines are stored consecutively in memory image width and frame buffer width are equal NOTE Addresses given for PING and PONG frames are virtual addresses Address transla...

Page 1259: ...The CSI2 receiver supports eight contexts and the CSI2 protocol defines four virtual channels Therefore a CSI2 receiver context can be associated with a virtual channel and a data type Virtual channels are defined by a 2 bit field Valid data types for the CSI2 receiver with their associated values are described in Table 6 60 Table 6 60 Camera ISP CSI2 Receiver Supported Data Types Value Data Type ...

Page 1260: ...PE_2 DPCM10 EXP16 0x2C2 USER_DEFINED_8_BIT_DATA_TYPE_3 DPCM10 EXP16 0x2C3 USER_DEFINED_8_BIT_DATA_TYPE_4 DPCM10 EXP16 0x2C4 USER_DEFINED_8_BIT_DATA_TYPE_5 DPCM10 EXP16 0x2C5 USER_DEFINED_8_BIT_DATA_TYPE_6 DPCM10 EXP16 0x2C6 USER_DEFINED_8_BIT_DATA_TYPE_7 DPCM10 EXP16 0x2C7 USER_DEFINED_8_BIT_DATA_TYPE_8 DPCM10 EXP16 0x329 RAW7 DPCM10 VP 0x32A RAW8 DPCM10 VP 0x340 USER_DEFINED_8_BIT_DATA_TYPE_1 DPC...

Page 1261: ... buffer is switched ping to pong or pong to ping after the FEC_NUMBER FEC is received for the context The image in the memory buffer consists of the FEC_NUMBER transmitted frame For more information about how data is stored in memory through the DMA see Section 6 4 3 8 DMA Engine NOTE If FEC_NUMBER 1 the camera sensor must send the line number information with the current line Otherwise the CSI2 r...

Page 1262: ... generates the CNTCLK clock TCTRL_CTRL 18 10 DIVC The clock is set by CNTCLK cam_mclk TCTRL_CTRL 18 10 DIVC The possible values are 0 to 511 Setting DIVC 0 disables the CNTCLK clock generation The frame counters are set with possible values are 0 to 63 frames TCTRL_FRAME 5 0 SHUT TCTRL_FRAME 11 6 PSTRB TCTRL_FRAME 17 12 STRB NOTE If the value is 0 the timing control module does not delay any frame...

Page 1263: ...on The frame counters bit fields are ignored TCTRL_FRAME 5 0 SHUT TCTRL_FRAME 11 6 PSTRB TCTRL_FRAME 17 12 STRB The delay counters are set with TCTRL_SHUT_DELAY TCTRL_PSTRB_DELAY TCTRL_STRB_DELAY The possible values are 0 to 225 1 cycle The cycles are at the CNTCLK clock frequency The maximum signal duration is 225 1 x 2 366 s 79 s TCTRL_CTRL 18 10 DIVC 511 The signal durations are set with TCTRL_...

Page 1264: ...ter t4 Set by the TCTRL_STRB_LENGTH register 6 5 6 Programming the CCDC This section discusses issues related to the software control of the CCDC It lists which registers are required to be programmed in different modes and describes how to enable and disable the CCDC how to check the status of the CCDC the different register access types and programming constraints 6 5 6 1 Camera ISP CCDC Hardwar...

Page 1265: ...rresponding condition is met Table 6 62 can be read as if Condition is TRUE then Configuration Required parameters must be programmed Table 6 62 Camera ISP CCDC Conditional Configuration Parameters Function Condition Configuration Required VD HD set as outputs CCDC_SYN_MODE 0 VDHDOUT 0x1 CCDC_HD_VD_WID CCDC_PIX_LINES Interlaced fields CCDC_SYN_MODE 7 FLDMODE 0x1 CCDC_CFG 7 6 FIDMD External WEN CCD...

Page 1266: ...7 WEN 0x1 CCDC_SDR_ADDR CCDC_HSIZE_OFF CCDC_SDOFST A Law CCDC_ALAW 3 CCDTBL 0x1 CCDC_ALAW 2 0 GWDI Interrupt usage VDINT 1 0 Interrupts are enabled CCDC_VDINT Lens shading compensation CCDC_LSC_CONFIG 0 ENABLE CCDC_LSC_CONFIG CCSC_LSC_INITIAL CCDC_LSC_TABLE_BASE CCDC_LSC_TABLE_OFFSET 6 5 6 1 3 Camera ISP CCDC Pixel Selection Framing Register Dependencies There are three locations in the data flow ...

Page 1267: ...d area HS Horizontal sync VS Vertical sync HORZ_ST Start pixel horizontal HORZ_NUM Size horiz of valid area VERT_NUM Size vertical of valid area CCDC input frame Reformatter VP output frame FMTLNV FMTSLV HORZ_NUM HD VD HDW PPLN HLPFR VDW HS VS HS VS VDW Global frame from AFE HLPFR SLVx NLV SDRAM output area SPH NPH SDRAM output frame Public Version www ti com Camera ISP Basic Programming Model Fig...

Page 1268: ...Q and one error event CCDC_ERR_IRQ Event generation is described in Section 6 5 6 3 2 CCDC_VD0_IRQ and CCDC_VD1_IRQ Interrupts and Section 6 5 6 3 3 CCDC_VD2_IRQ Interrupt CCDC module events can be mapped to the ARM or the DSP The CCDC_VD0_IRQ CCDC_VD1_IRQ CCDC_VD2_IRQ and CCDC_ERR_IRQ bits in the ISP_IRQ0ENABLE register control whether the CCDC module events trigger an interrupt to the ARM The IS...

Page 1269: ...CDC Status Checking The CCDC_PCR 1 BUSY status bit is set when the start of frame occurs if the CCDC_PCR 0 ENABLE bit is 1 at that time It is automatically reset to 0 at the end of a frame The CCDC_PCR 1 BUSY status bit may be polled to determine end of frame status The CCDC_FPC 16 FPERR status bit is set when faulty pixel data fetched from memory arrives late This bit can be reset by writing a 1 ...

Page 1270: ... CCDC_CFG 15 VDLC remains set to 0 default indeterminate results may occur for ANY register access in the CCDC not just those listed in the following Optionally shadowed or busy writable registers CCDC_SYN_MODE 19 SDR2RSZ CCDC_SYN_MODE 18 VP2SDR CCDC_SYN_MODE 16 VDHDEN CCDC_SYN_MODE 17 WEN CCDC_SYN_MODE 14 LPF CCDC_HD_VD_WID CCDC_PIX_LINES CCDC_HORZ_INFO CCDC_VERT_START CCDC_VERT_LINES CCDC_CULLIN...

Page 1271: ...Cr and cam_d 9 0 are used for 10 bit YCbCr FVH error correction is enabled by setting CCDC_REC656IF 1 ECCFVH 1 The internal timing generator must be enabled with CCDC_SYN_MODE 16 VDHDEN 1 6 5 6 6 1 2 Camera ISP CCDC Timing Generator and Frame Settings The polarities of the cam_hs cam_vs and cam_fld signals are controlled by the CCDC_SYN_MODE 3 HDPOL CCDC_SYN_MODE 2 VDPOL and CCDC_SYN_MODE 4 FLDPOL...

Page 1272: ...e Cy Mg and G complementary color mosaic filters The mosaic filter layout pattern is controlled by the CCDC_COLPTN register Each bit field in this register controls the color associated to one pixel in a 4x4 region area The 4x4 area repeats horizontally and vertically Figure 6 116 shows configuration examples of the CCDC_COLPTN register It is assumed that CP0LPC0 is the first pixel output and CP3L...

Page 1273: ...ght of the window is 2N the average value multiplied by a programmable gain factor is subtracted from the raw image data for the following 2N lines Every 2N lines a new average value is computed For the first 2N lines 0 is subtracted The size of the window and horizontal position are controlled by the CCDC_CLAMP register The vertical position of the window is set to line 0 and cannot be modified C...

Page 1274: ...e input line is transformed into 2 output lines is 2x1376 The maximum number of pixels that can be supported in an output line if the input line is transformed into 3 output lines is 1376 The maximum number of pixels that can be supported in an output line if the input line is transformed into 4 output lines is 1376 The data reformatter gets its flexibility from up to 8 different addresses and a p...

Page 1275: ... can be as large as 4x1376 pixels Table 6 64 Camera ISP CCDC Dual Readout Pattern 1 to 1 Input Pixels order in input line Line i 0 1 2 3 4092 4093 4094 4095 Output Pixels order in output line Line i 0 2 4 6 7 5 3 1 To obtain this mapping between the input and output pixels the following settings apply CCDC_FMTCFG 3 2 LNUM 0 Converts to 1 line CCDC_FMTCFG 11 8 PLEN_EVEN 1 2 program entry CCDC_FMTCF...

Page 1276: ...R_i 12 0 INIT i 2 1 Init ADDR2 index to first pixel CCDC_FMT_ADDR_i 25 24 LINE i 3 1 Init ADDR3 pointer to first line CCDC_FMT_ADDR_i 12 0 INIT i 3 856 Init ADDR3 index to 856th pixel CCDC_FMT_ADDR_i 25 24 LINE i 4 2 Init ADDR4 pointer to second line CCDC_FMT_ADDR_i 12 0 INIT i 4 0 Init ADDR4 index to 0th pixel CCDC_FMT_ADDR_i 25 24 LINE i 5 0 Init ADDR5 pointer to 0th line CCDC_FMT_ADDR_i 12 0 IN...

Page 1277: ...pixels each in the left and right edges of each line are cropped from the output 6 5 6 6 2 6 2 Camera ISP CCDC A Law Compression A Law compression is enabled by setting CCDC_ALAW 3 CCDTBL to 1 The A Law table is fixed so no setup is required When the input is wider than 10 bits the CCDC_ALAW 2 0 GWDI bit is used to select which 10 bits of the 12 possible bits are selected for compression See Table...

Page 1278: ...a Packing Pixel Ordering 6 5 6 6 2 6 5 Camera ISP CCDC Clipping Window Before data is stored in memory a clipping window can be set only a selected sensor area is stored to memory Figure 6 118 shows the settings only the white area is stored to memory The valid data horizontal start position is controlled with the CCDC_HORZ_INFO 30 16 SPH bit field The valid data vertical start position is control...

Page 1279: ... LSBs as 0 A destination pitch can be set with the CCDC_HSIZE_OFF register The offset must be a multiple of 32 bytes The 5 LSBs are ignored Reading the register always shows the 5 LSBs as 0 It is required for the pixel line length to be a multiple of 32 bytes to be stored in memory without holes The CCDC_SDOFST register controls how the pixels are stored to memory Data to be written to memory can ...

Page 1280: ...amming the Preview Engine This section discusses issues related to software control of the preview engine It lists which registers are required to be programmed in different modes how to enable and disable the preview engine and how to check the status of the preview engine discusses the different register access types and enumerates programming constraints 6 5 7 1 Camera ISP Preview Setup Initial...

Page 1281: ..._BRT YCC output format PRV_SETUP_YC PRV_PCR 18 17 YCPOS The PRV_PCR register contains control bits that enable or disable optional functions and module IO ports If an optional function or port is enabled there may be more registers or configuration information required for the preview engine to operate correctly Table 6 68 can be read as If Condition is TRUE then Configuration required parameters ...

Page 1282: ...d the CFA coefficient memory must be filled in before the operation of the preview engine if their respective functions are enabled Two registers allow memory contents to be read and written The address register is used to select the specific table entry PRV_SET_TBL_ADDR The data register contains the data to be written to the specified location PRV_SET_TBL_DATA While the data register is 20 bits ...

Page 1283: ...tatus Checking The preview engine generates an interrupt at the end of each frame The status of this interrupt can be checked by reading the ISP_IRQ0STATUS register or ISP_IRQ1STATUS When the read of the register ISP_IRQ0STATUS occurs or ISP_IRQ1STATUS the register is not automatically reset To reset the interrupt a 1 must be written to the PRV_DONE_IRQ bit Each event that generates an interrupt c...

Page 1284: ... and memory pointer registers are shadowed these modifications can occur any time before the end of the frame and the data is latched in for the next frame The MPU subsystem can perform these changes on receiving an interrupt 6 5 7 6 Camera ISP Preview Summary of Constraints The following is a list of register configuration constraints to adhere to when programming the preview engine It can be use...

Page 1285: ... the hardware must be correctly configured through register writes Table 6 69 identifies the register parameters that must be programmed before enabling the resizer Table 6 69 Camera ISP Resizer Required Configuration Parameters Function Configuration Required Resizer control parameters RSZ_CNT IO sizes RSZ_OUT_SIZE RSZ_IN_START RSZ_IN_SIZE Memory addresses RSZ_SDR_INADD RSZ_SDR_INOFF RSZ_SDR_OUTA...

Page 1286: ...vents and Status Checking The resizer generates an interrupt event at the end of each frame The status of this interrupt can be checked by reading the ISP_IRQ0STATUS register or ISP_IRQ1STATUS When the read of the register ISP_IRQ0STATUS occurs or ISP_IRQ1STATUS the register is not automatically reset To reset the interrupt a 1 must be written to the RSZ_DONE_IRQ bit Each event that generates an i...

Page 1287: ...the filter coefficients If polyphase resampling is used a different set is required when changing between 4 tap and 7 tap modes and with different downsampling factors all upsampling factors can share the same set of coefficients Do not change any busy lock registers while the resizer is operating Specifically when back to back resizes require changes in any busy lock registers such as the coeffic...

Page 1288: ...o determine the processing time of the resizer when the input is from memory and therefore how much time it takes before it can switch back to preview input mode Time W bytes_per_pixel H L3 2 4 Where If the input is YUV422 and horizontal downsampling is performed if RSZ_CNT 27 INPTYP 0 RSZ_CNT 9 0 HRSZ 1 256 W average input_width output width output width includes extra 4 pixels if edge enhancemen...

Page 1289: ... 16 VERT hrsz Horizontal resize value RSZ_CNT 9 0 HRSZ 1 vrsz Vertical resize value RSZ_CNT 19 10 VRSZ 1 extra 0 when RSZ_YENH 17 16 ALGO 0 edge enhancement disabled extra 4 when RSZ_YENH 17 16 ALGO 0 edge enhancement enabled NOTE Normally for example for a QVGA display or encoded PAL video the output size not the input size matters The image provided by preview CCDC memory must have an adequate o...

Page 1290: ...T H3A_AFIIRSH Memory address H3A_AFBUFST Filter coefficients H3A_AFCOEF010 to H3A_AFCOEF1010 The horizontal median filter function is optional If it is disabled the H3A_PCR 10 3 MED_TH does not need to be programmed However if it is enabled the H3A_PCR 10 3 MED_TH parameter must be programmed so that the horizontal median filter function operates correctly Table 6 73 can be read as If Condition is...

Page 1291: ...hen the read of the register ISP_IRQ0STATUS occurs or ISP_IRQ1STATUS the register is not automatically reset To reset the interrupt a 1 must be written to the corresponding bit Each event that generates an interrupt can be individually mapped to ARM or DSP using the ISP_IRQ0ENABLE register or ISP_IRQ1ENABLE When a particular event is not enabled for example ISP_IRQ0ENABLE x 0 the correspondent sta...

Page 1292: ...he minimum width of the AE AWB windows is 6 pixels 6 5 10 Programming the Histogram This section discusses issues related to software control of the histogram module It lists which registers are required to be programmed in different modes how to enable and disable the histogram and how to check the status of the histogram discusses the different register access types and enumerates programming co...

Page 1293: ...e This must be done after all required registers are programmed and the output memory has been cleared When the input source is the memory the histogram module always operates in one shot mode In other words after enabling the histogram the ENABLE bit is automatically turned off set to 0 and only a single frame is processed from memory In this mode fetching and processing of the frame begin immedi...

Page 1294: ...ed to memories internally Such reads return indeterminate data Byte enables are not implemented for reading the histogram memory The ideal procedure for changing the histogram registers is IF HIST_PCR 1 BUSY 0 OR IF EOF interrupt occurs DISABLE HISTOGRAM CHANGE REGISTERS ENABLE HISTOGRAM 6 5 10 5 Camera ISP Histogram Interframe Operations Between frames read from memory it may be necessary to modi...

Page 1295: ...esource SBLReset Behavior On hardware reset of the camera ISP all registers in the SBL are reset to their reset values 6 5 11 1 2 Camera ISP Central Resource SBLRegister Setup Before enabling any of the camera ISP modules the hardware must be correctly configured through register writes to the camera ISP registers If the preview engine resizer or the histogram is reading from memory the SBL_SDR_RE...

Page 1296: ...Q0STATUS register or ISP_IRQ1STATUS Each event that generates an interrupt can be individually mapped to ARM or DSP using the ISP_IRQ0ENABLE register or ISP_IRQ1ENABLE When a particular event is not enabled for example ISP_IRQ0ENABLE x 0 the correspondent status ISP_IRQ0STATUS x 1 bit is flagged if the correspondent event occurs This has no effect on the interrupt line but can be used by software ...

Page 1297: ...sults long before real time deadlines the performance of other peripherals in the system may be negatively affected The camera ISP offers two kinds of adjustments that can slow down data processing in this situation One can be made when the sensor input to the CCDC is the input source and the other can be made when the memory is the source of the input image 6 5 11 5 1 Camera ISP Central Resource ...

Page 1298: ... read requests frame In the previous equation DMA cycles frame is based on a real time requirement For example if the real time requirement is a frame rate of 1 30 sec and the L3 clock equals the ISP clock this can be calculated as DMA cycles frame L3 clock frame rate ISP clock 1 30 5 53M cycles The DMA read requests frame is based on the frame size and the alignment in memory Assuming a VGA 640 x...

Page 1299: ...ffer organization For example when each window corresponds to 8 lines by 4096 pixel but the camera ISP only send lines of 2560 pixels the CBUFFx_WINDOWSIZE 8 4096 and CBUFFx_THRESHOLD 8 2560 When the register setup is completed the module is enabled using the CBUFFx_CTRL 0 EN bit It can be disabled by clearing the CBUFFx_CTRL 0 EN bit This must only be done when there are no more outstanding reque...

Page 1300: ..._IRQ event is generated each time processor can read data from the circular buffer Processor can clear the event when it starts processing the data to avoid masking of other events Processor can keep trace of the location on the data internally or use the circular buffer registers to compute it The formula used for CBUFF1 is ADDR CBUFFx_STATUS 3 0 CPUW x CBUFFx_WINDOWSIZE CBUFFx_START 5 Because of...

Page 1301: ...o configure for the camera subsystem software reset step Table 6 79 Camera ISP Software Register Settings Register Name Address Value Description ISP_SYSCONFIG 0x480B C004 Initiate a software reset The ISP_SYSCONFIG 1 SOFTRESET is automatically reset by hardware ISP_SYSSTATUS 0x480B C008 The ISP_SYSSTATUS 0 RESETDONE is set to 1 when the reset sequence is done 1301 SWPU177N December 2009 Revised N...

Page 1302: ...ement Units 6 6 1 1 Camera ISP Registers Summary Table 6 81 ISP Register Mapping Summary Register Width Register Name Type Address Offset ISP L3 Base Address Bits ISP_REVISION R 32 0x0000 0000 0x480B C000 ISP_SYSCONFIG RW 32 0x0000 0004 0x480B C004 ISP_SYSSTATUS R 32 0x0000 0008 0x480B C008 ISP_IRQ0ENABLE RW 32 0x0000 000C 0x480B C00C ISP_IRQ0STATUS RW 32 0x0000 0010 0x480B C010 ISP_IRQ1ENABLE RW ...

Page 1303: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED REV Bits Field Name Description Type Reset 31 8 RESERVED Write 0s for future compatibility Read returns 0 R 0x000000 7 0 REV IP revision R TI internal data 7 4 major revision 3 0 minor revision Table 6 83 Register Call Summary for Register ISP_REVISION Camera ISP Register Manual Camera ISP Registers Summary 0 Table 6 84 ISP_SYSCONFIG Address Offset ...

Page 1304: ...ategy RW 1 0x0 Interconnect functional clocks are free running 0x1 Automatic clock gating strategy is applied based on the Interconnect interface activity for interface clock and on the functional activity for functional Clocks Table 6 85 Register Call Summary for Register ISP_SYSCONFIG Camera ISP Integration Camera ISP Local Power Management 0 Camera ISP System Power Management 1 Camera ISP Softw...

Page 1305: ...31 HS_VS_IRQ HS or VS synchro event RW 0 This event is triggered if a rising or falling edge is detected on the HS or VS signal The rising or falling edge and the HS or VS signal selection is chosen with the ISP_CTRL SYNC_DTECT bit field 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 30 RESERVED Write 0s for future compatibility Read returns 0 RW 0 29 OCP_ERR_IRQ ISP interconn...

Page 1306: ...rupt when it occurs 17 CCDC_LSC_DONE The event is triggered when the internal state of LSC RW 0 toggles from BUSY to IDLE 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 16 HIST_DONE_IRQ HIST module processing done event RW 0 This event is triggered at the end of the frame when the processing is completed for the current frame 0x0 Event is masked 0x1 Event generates an interrup...

Page 1307: ...n interrupt when it occurs 2 RESERVED Write 0s for future compatibility Read returns 0 RW 0 1 CSI2C_IRQ CSI2C module event RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 0 CSI2A_IRQ CSI2A module event RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs Table 6 89 Register Call Summary for Register ISP_IRQ0ENABLE Camera ISP Integration Camera ISP Inter...

Page 1308: ...1 Status bit reset 30 RESERVED Write 0s for future compatibility Read returns 0 RW 0 29 OCP_ERR_IRQ ISP interconnect error R W 1to 0 READS Clr 0 Event is false 1 Event is true WRITES 0 Status bit unchanged 1 Status bit reset 28 MMU_ERR_IRQ MMU error R W 1to 0 If event is true one needs to read the MMU_IRQSTATUS register Clr to know the event source Write in MMU_IRQSTATUS to clear the bit READS 0 E...

Page 1309: ... Event is false 1 Event is true WRITES 0 Status bit unchanged 1 Status bit reset 18 CCDC_LSC_PREFETCH_COMP Indicates current state of the prefetch buffer R W 1to 0 LETED READS Clr 0 Event is false 1 Event is true WRITES 0 Status bit unchanged 1 Status bit reset 17 CCDC_LSC_DONE The event is triggered when the internal state of LSC toggles from R W 1to 0 BUSY to IDLE Clr READS 0 Event is false 1 Ev...

Page 1310: ...nchanged 1 Status bit reset 8 CCDC_VD0_IRQ CCDC module programmable event 0 R W 1to 0 READS Clr 0 Event is false 1 Event is true WRITES 0 Status bit unchanged 1 Status bit reset 7 CSIB_LC3_IRQ CSI1 CCP2B receiver module event on logical channel 3 R W 1to 0 READS Clr 0 Event is false 1 Event is true WRITES 0 Status bit unchanged 1 Status bit reset 6 CSIB_LC2_IRQ CSI1 CCP2B receiver module event on ...

Page 1311: ...upt Requests 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Camera ISP Basic Programming Model Camera ISP CCDC Interrupts 23 24 25 Camera ISP Preview Events and Status Checking 26 27 28 Camera ISP Resizer Events and Status Checking 29 30 31 Camera ISP H3A Event and Status Checking 32 33 34 Camera ISP Histogram Event and Status Checking 35 36 37 Camera ISP Central Resource SBL Event and...

Page 1312: ... when it occurs 28 MMU_ERR_IRQ MMU error RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 27 26 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 25 OVF_IRQ Central Resource SBL overflow RW 0 This event is triggered when one of the buffer in the central resource SBL overflows 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 24 RSZ_DONE_IRQ R...

Page 1313: ...e 0s for future compatibility Read returns 0 R 0 14 RESERVED Write 0s for future compatibility Read returns 0 RW 0 13 H3A_AWB_DONE_IRQ H3A module auto exposure and auto white balance processing RW 0 done event This event is triggered at the end of the frame when the processing is completed for the current frame 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 12 H3A_AF_DONE_IRQ ...

Page 1314: ...mera ISP CCDC Interrupts 1 Camera ISP Preview Events and Status Checking 2 Camera ISP Resizer Events and Status Checking 3 Camera ISP Resizer Multiple Passes for Large Resizing Operations 4 Camera ISP H3A Event and Status Checking 5 6 Camera ISP Histogram Event and Status Checking 7 Camera ISP Central Resource SBL Event and Status Checking 8 9 Camera ISP Register Manual Camera ISP Registers Summar...

Page 1315: ...PCR Clr register to know the source One needs to clear the SBL_PCR register first before clearing this bit READS 0 event is false 1 event is true WRITES 0 status bit unchanged 1 status bit reset 24 RSZ_DONE_IRQ RESIZER module resizer processing done event R W 1to 0 READS Clr 0 event is false 1 event is true WRITES 0 status bit unchanged 1 status bit reset 23 22 RESERVED Write 0s for future compati...

Page 1316: ... unchanged 1 status bit reset 15 14 RESERVED Write 0s for future compatibility Read returns 0 R W 1to 0 Clr 13 H3A_AWB_DONE_IRQ H3A module auto exposure and auto white balance R W 1to 0 processing done event Clr READS 0 event is false 1 event is true WRITES 0 status bit unchanged 1 status bit reset 12 H3A_AF_DONE_IRQ H3A module autofocus processing done event R W 1to 0 READS Clr 0 event is false 1...

Page 1317: ...S 0 status bit unchanged 1 status bit reset 5 CSIB_LC1_IRQ CSI1 CCP2B receiver module event on logical channel R W 1to 0 1 Clr READS 0 event is false 1 event is true WRITES 0 status bit unchanged 1 status bit reset 4 CSIB_LC0_IRQ CSI1 CCP2B receiver module event on logical channel R W 1to 0 0 Clr READS 0 event is false 1 event is true WRITES 0 status bit unchanged 1 status bit reset 3 CSIB_LCM_IRQ...

Page 1318: ... is used by the TIMING CTRL module to generate the CAM GRESET signal Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LENGTH Bits Field Name Description Type Reset 31 24 RESERVED Write 0s for future compatibility Read returns 0 R 0x00 23 0 LENGTH Sets the length of the CAM GLOBAL_RESET signal RW 0x000000 assertion in cycles of the CNTCLK clock ...

Page 1319: ...values are 0 to 2 25 1 cycles If TCTRL_PSTRB_LENGTH 0 there is no replay This bit field shall not be set to 0 if the COUNTER is set to a value different of 0 This bit is useful when one wants to enable red eye removal Table 6 99 Register Call Summary for Register TCTRL_PSTRB_REPLAY Camera ISP Basic Programming Model Camera ISP Timing CTRL STROBE and PRESTROBE Signal Generation for Red Eye Removal ...

Page 1320: ... 0x0 0x0 Disabled 0x1 The BCF signal of CBUFF1 stalls the response phase of the CSI1 CCP2B Interconnect read master port 0x2 The BCF signal of CBUFF1 stalls the request phase of the CSI1 CCP2B Interconnect read master port 0x3 The BCF signal of CBUFF1 stalls the request and response phase of the CSI1 CCP2B Interconnect read master port 23 22 CBUFF0_BCF_CTRL Bandwidth control feedback loop configur...

Page 1321: ...owever accesses on the module slave port to configure it are still possible 0x1 Enable clock The module is fully functional 12 PRV_CLK_EN PRV module clock enable RW 0 This bit controls the clock distribution to the PRV module 0x0 Disable clock The module is not active However accesses on the module slave port to configure it are still possible 0x1 Enable clock The module is fully functional 11 HIS...

Page 1322: ... 13 0 CAM 13 0 0x1 Shift by 2 CAMEXT 13 2 CAM 11 0 0x2 Shift by 4 CAMEXT 13 4 CAM 9 0 0x3 Shift by 6 CAMEXT 13 6 CAM 7 0 5 RESERVED Write 0s for future compatibility Read returns 0 R 0 4 PAR_CLK_POL This bit sets the pixel clock polarity on the parallel RW 0 interface The pixel clock is used for latching the pixel data into the CCDC module 0x0 Clock not inverted The data are sampled on the rising ...

Page 1323: ...r Manual Camera ISP Registers Summary 33 Camera ISP Register Description 34 35 36 Camera ISP CCDC Register Description 37 38 Table 6 102 TCTRL_CTRL Address Offset 0x0000 0050 Physical Address Instance ISP See Table 6 81 Description TIMING CONTROL CONTROL REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INSEL DIVC DIVB DIVA STRBEN SHUTEN SHUTPOL...

Page 1324: ..._CTRL GRESETPOL 26 STRBPSTRBPOL Sets the polarity of the strobe and prestrobe signals RW 0 0x0 Active high 0x1 Active low 25 RESERVED Write 0s for future compatibility Read returns 0 R 0 24 SHUTPOL Sets the polarity of the mechanical shutter signal RW 0 CAM SHUTTER 0x0 Active high 0x1 Active low 23 STRBEN Flash strobe signal enable If enabled the STROBE RW 0 signal will be asserted after TCTRL_FRA...

Page 1325: ...stable low level Divider disabled 0x1 CAM XCLKA stable high level Divider disabled 0x1F CAM XCLKA CAM XCLK Bypass Table 6 103 Register Call Summary for Register TCTRL_CTRL Camera ISP Integration Camera ISP Clock Configuration 0 1 Camera ISP Functional Description Camera ISP Timing Control Control Signal Generator 2 3 4 5 6 7 8 9 10 11 12 Camera ISP Basic Programming Model Camera ISP Timing CTRL Ti...

Page 1326: ...SET Table 6 105 Register Call Summary for Register TCTRL_FRAME Camera ISP Basic Programming Model Camera ISP Timing CTRL Vertical Synchro Based Control Signal Generation or Externally Generated cam_global_reset 0 1 2 Camera ISP Timing CTRL Internally Generated cam_global_reset Based Control Signal Generation 3 4 5 Camera ISP Register Manual Camera ISP Registers Summary 6 Camera ISP Register Descri...

Page 1327: ...TRL DIVC bit field The possible values are 0 to 2 25 1 cycles Table 6 109 Register Call Summary for Register TCTRL_STRB_DELAY Camera ISP Basic Programming Model Camera ISP Timing CTRL Vertical Synchro Based Control Signal Generation or Externally Generated cam_global_reset 0 Camera ISP Timing CTRL Internally Generated cam_global_reset Based Control Signal Generation 1 Camera ISP Timing CTRL STROBE...

Page 1328: ...tion in cycles of the CNTCLK clock The CNTCLK frequency is generated with the TCTRL_CTRL DIVC bit field After signal assertion the TCTRL_CTRL PSTRBEN bit is automatically cleared The possible values are 0 to 2 24 1 cycles Table 6 113 Register Call Summary for Register TCTRL_PSTRB_LENGTH Camera ISP Basic Programming Model Camera ISP Timing CTRL Vertical Synchro Based Control Signal Generation or Ex...

Page 1329: ...enerate the SHUTTER signal Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LENGTH Bits Field Name Description Type Reset 31 24 RESERVED Write 0s for future compatibility Read returns 0 R 0x00 23 0 LENGTH Sets the length of the CAM SHUTTER signal assertion in RW 0x000000 cycles of the CNTCLK clock The CNTCLK frequency is generated with the TCTR...

Page 1330: ...ister Description Table 6 119 CBUFF_REVISION Address Offset 0x0000 0000 Physical Address 0x480B C100 Instance ISP_CBUFF Description This register contains the IP revision code Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED REV Bits Field Name Description Type Reset 31 8 RESERVED Write 0s for future compatibility Read returns 0 R 0x000000 7 0 R...

Page 1331: ...ual Camera ISP CBUFF Register Summary 0 Table 6 125 CBUFF_IRQSTATUS Address Offset 0x0000 0018 Physical Address 0x480B C118 Instance ISP_CBUFF Description The interrupt status register regroups all the status of the module internal events that can generate an interrupt Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IRQ_CBUFF1_OVR IRQ_CBUFF0_O...

Page 1332: ...tegration Camera ISP Interrupt Requests 0 1 2 3 4 5 6 Camera ISP Functional Description Camera ISP Circular Buffer Window Management 7 8 9 Camera ISP Basic Programming Model Camera ISP CBUFF Interrupts 10 11 Camera ISP CBUFF Status Checking 12 Camera ISP Register Manual Camera ISP CBUFF Register Summary 13 Table 6 127 CBUFF_IRQENABLE Address Offset 0x0000 001C Physical Address 0x480B C11C Instance...

Page 1333: ...ble 6 128 Register Call Summary for Register CBUFF_IRQENABLE Camera ISP Integration Camera ISP Interrupt Requests 0 1 2 3 4 5 Camera ISP Register Manual Camera ISP CBUFF Register Summary 6 Table 6 129 CBUFFx_CTRL Address Offset 0x0000 0020 x 0x4 Index x 0 to 1 Physical Address 0x480B C120 x 0x4 Instance ISP_CBUFF Description Circular buffer x control register Type RW 31 30 29 28 27 26 25 24 23 22 ...

Page 1334: ...s finished W 0x0 processing its physical buffer This bit is automatically cleared by hardware reads always return 0 0x0 No effect 0x1 The CPU has completely processed the CPUW physical buffer 1 RWMODE Selects read or write mode RW 0x0 0x0 Write mode HW writes and CPU reads the physical space CPU accesses are out of CBUFF module s scope therefore only writes are permitted between CBUFF0_START and C...

Page 1335: ...e 0s for future compatibility Read returns 0 R 0x00 23 20 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 19 16 NW Next window number R 0x1 Valid values depend on the CBUFF_CTRL WCOUNT register 15 12 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 11 8 CW Current window number R 0x0 Valid values depend on the CBUFF_CTRL WCOUNT register 7 4 RESERVED Write 0s for futu...

Page 1336: ...F Register Setup 6 Camera ISP CBUFF Operations 7 Camera ISP Register Manual Camera ISP CBUFF Register Summary 8 Table 6 135 CBUFFx_END Address Offset 0x0000 0050 x 0x4 Index x 0 to 1 Physical Address 0x480B C150 x 0x4 Instance ISP_CBUFF Description End address of the virtual space managed by circular buffer x Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 1337: ... 10 11 Camera ISP CBUFF Operations 12 Camera ISP Register Manual Camera ISP CBUFF Register Summary 13 Table 6 139 CBUFFx_THRESHOLD Address Offset 0x0000 0070 x 0x4 Index x 0 to 1 Physical Address 0x480B C170 x 0x4 Instance ISP_CBUFF Description Threshold value used to check if a write window is full Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESER...

Page 1338: ...Circular Buffer Bandwidth Control Feedback Loop 0 1 Camera ISP Basic Programming Model Camera ISP CBUFF Operations 2 Camera ISP Register Manual Camera ISP CBUFF Register Summary 3 Table 6 143 CBUFF_VRFB_CTRL Address Offset 0x0000 00C0 Physical Address Instance ISP_CBUFF 0x480B C1C0 Description VRFB context grouping control register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1...

Page 1339: ...all not change this register when there s active traffic to the translated region 0x0 Disabled 0x1 Enabled 9 RESERVED Write 0s for future compatibility Read returns 0 R 0 8 7 ORIENTATION0 Orientation RW 0x0 0x0 0 degrees 0x1 90 degrees 0x2 180 degrees 0x3 270 degrees 6 5 WIDTH0 RW 0x0 0x0 8 bits 0x1 16 bits 0x2 32 bits 0x3 Reserved 4 1 BASE0 Region being translated when translation is enabled RW 0...

Page 1340: ...0x480B C454 x 0x30 CCP2_LCx_STAT_START RW 32 0x0000 0058 x 0x30 0x480B C458 x 0x30 CCP2_LCx_STAT_SIZE RW 32 0x0000 005C x 0x30 0x480B C45C x 0x30 CCP2_LCx_SOF_ADDR RW 32 0x0000 0060 x 0x30 0x480B C460 x 0x30 CCP2_LCx_EOF_ADDR RW 32 0x0000 0064 x 0x30 0x480B C464 x 0x30 CCP2_LCx_DAT_START RW 32 0x0000 0068 x 0x30 0x480B C468 x 0x30 CCP2_LCx_DAT_SIZE RW 32 0x0000 006C x 0x30 0x480B C46C x 0x30 CCP2_...

Page 1341: ...STER This register is the Interconnect socket system configuration register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED AUTO_IDLE SOFT_RESET MSTANDBY_MODE Bits Field Name Description Type Reset 31 14 RESERVED Write 0s for future compatibility Read returns 0 RW 0x00000 13 12 MSTANDBY_MODE Sets the behavior of the master port power ...

Page 1342: ...Address 0x480B C408 Instance ISP_CCP2 Description SYSTEM STATUS REGISTER This register provides status information about the module excluding interrupt status information Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESET_DONE Bits Field Name Description Type Reset 31 1 RESERVED Write 0s for future compatibility Read returns 0 R 0x00000000 0...

Page 1343: ...1 Event generates an interrupt when it occurs 26 LC1_LE_IRQ Logical channel 1 Line end synchronization code RW 0x0 detection 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 25 LC1_LS_IRQ Logical channel 1 Line start synchronization code RW 0x0 detection 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 24 LC1_FE_IRQ Logical channel 1 Frame end synchronization ...

Page 1344: ...n 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 7 LC0_COUNT_IRQ Logical channel 0 Frame counter reached RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 6 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 5 LC0_FIFO_OVF_IRQ Logical channel 0 FIFO overflow error RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs ...

Page 1345: ...RQ LC1_FW_IRQ LC0_FW_IRQ LC1_FSP_IRQ LC0_FSP_IRQ LC1_FSC_IRQ LC0_FSC_IRQ LC1_SSC_IRQ LC0_SSC_IRQ LC1_CRC_IRQ LC0_CRC_IRQ LC1_COUNT_IRQ LC0_COUNT_IRQ LC1_FIFO_OVF_IRQ LC0_FIFO_OVF_IRQ Bits Field Name Description Type Reset 31 28 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 27 LC1_FS_IRQ Logical channel 1 Frame start synchronization code RW 0x0 detection status 1toClr 0x0 READS E...

Page 1346: ...g WRITES Status bit is reset 17 LC1_FSC_IRQ Logical channel 1 False synchronization code error RW 0x0 status 1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 16 LC1_SSC_IRQ Logical channel 1 Shifted synchronization code error RW 0x0 status 1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pendin...

Page 1347: ... 0x0 1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 2 LC0_FW_IRQ Logical channel 0 Frame width error status RW 0x0 1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 1 LC0_FSC_IRQ Logical channel 0 False synchronization code error RW 0x0 status 1toClr 0x0 READ...

Page 1348: ...1 Event generates an interrupt when it occurs 26 LC3_LE_IRQ Logical channel 3 Line end synchronization code RW 0x0 detection 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 25 LC3_LS_IRQ Logical channel 3 Line start synchronization code RW 0x0 detection 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 24 LC3_FE_IRQ Logical channel 3 Frame end synchronization ...

Page 1349: ...n 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 7 LC2_COUNT_IRQ Logical channel 2 Frame counter reached RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 6 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 5 LC2_FIFO_OVF_IRQ Logical channel 2 FIFO overflow error RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs ...

Page 1350: ...RQ LC3_FW_IRQ LC2_FW_IRQ LC3_FSP_IRQ LC2_FSP_IRQ LC3_FSC_IRQ LC2_FSC_IRQ LC3_SSC_IRQ LC2_SSC_IRQ LC3_CRC_IRQ LC2_CRC_IRQ LC3_COUNT_IRQ LC2_COUNT_IRQ LC3_FIFO_OVF_IRQ LC2_FIFO_OVF_IRQ Bits Field Name Description Type Reset 31 28 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 27 LC3_FS_IRQ Logical channel 3 Frame start synchronization code RW 0x0 detection status 1toClr 0x0 READS E...

Page 1351: ...g WRITES Status bit is reset 17 LC3_FSC_IRQ Logical channel 3 False synchronization code error RW 0x0 status 1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 16 LC3_SSC_IRQ Logical channel 3 Shifted synchronization code error RW 0x0 status 1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pendin...

Page 1352: ... 0x0 1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 2 LC2_FW_IRQ Logical channel 2 Frame width error status RW 0x0 1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 1 LC2_FSC_IRQ Logical channel 2 False synchronization code error RW 0x0 status 1toClr 0x0 READ...

Page 1353: ... generates an interrupt when it occurs 0 LCM_EOF Memory read channel End of frame RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs Table 6 161 Register Call Summary for Register CCP2_LCM_IRQENABLE Camera ISP Integration Camera ISP Interrupt Requests 0 1 Camera ISP Register Manual Camera ISP CCP2 Register Summary 2 Table 6 162 CCP2_LCM_IRQSTATUS Address Offset 0x0000 0030 ...

Page 1354: ...le This register is not modified dynamically except IF_EN bit field Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRACDIV BURST INV IF_EN MODE FRAME POSTED DBG_EN PHY_SEL RESERVED IO_OUT_SEL VP_CLK_POL VP_ONLY_EN VP_CLK_FORCE_ON Bits Field Name Description Type Reset 31 15 FRACDIV Fractional clock divider control for the video port RW 0x10000 The mea...

Page 1355: ...ectly to MIPI CSI1 values the behavior of the receiver is unpredictable 0x1 CCP2B compatible mode 3 FRAME Set the modality in which IF_EN works RW 0x0 0x0 When SW writes IF_EN 0 the interface is disabled immediately 0x1 When SW writes IF_EN 0 the interface is disabled after the next FEC synchronization code 2 IO_OUT_SEL IO cell output mode selection RW 0x0 0x0 RESERVED 0x1 MUST BE SET TO 1 IO outp...

Page 1356: ...rom Memory 41 42 43 44 45 46 Camera ISP Register Manual Camera ISP CCP2 Register Summary 47 Camera ISP CCP2 Register Description 48 49 50 51 52 Table 6 166 CCP2_DBG Address Offset 0x0000 0044 Physical Address 0x480B C444 Instance ISP_CCP2 Description DEBUG REGISTER This register provides a way to debug the CCP2B RECEIVER module with no image sensor connected to the module The debug mode is enabled...

Page 1357: ...ts R 0x2 Read 0x0 2x 64 bits Read 0x1 4x 64 bits Read 0x2 8x 64 bits Read 0x3 16x 64 bits Read 0x4 32x 64 bits Read 0x5 64x 64 bits 1 0 NBCHANNELS Number of logical channels supported by the module R 0x2 Read 0x0 1 logical channel Read 0x1 2 logical channels Read 0x2 4 logical channels Read 0x3 8 logical channels Table 6 169 Register Call Summary for Register CCP2_GNQ Camera ISP Basic Programming ...

Page 1358: ... period provided by the camera is lower than the value set here the blanking period is shortened by the CCP2_RECEIVER to prevent internal FIFO overflow Software must increase the sensor blanking period in that case 0x0 4 video port clock cycles 0x1 16 video port clock cycles 0x2 64 video port clock cycles 0x3 Free running Table 6 171 Register Call Summary for Register CCP2_CTRL1 Camera ISP Registe...

Page 1359: ...sed 0x1 The simple predictor is used 17 PING_PONG Indicates whether the PING or PONG destination R 1 address CCP2_LC0_DAT_PING_ADDR or CCP2_LC0_DAT_PONG_ADDR was used to write the last frame This bit field toggles after every FEC sync code Read 0x0 PING buffer Read 0x1 PONG buffer 16 COUNT_UNLOCK Unlock writes to the COUNT bit field W 0 Write 0x0 COUNT bit field is locked Writes have no effect Wri...

Page 1360: ...W8 DPCM RAW10 data from sensor is DPCM compressed into RAW8 before it is send to memory 0x1C JPEG8 FSP 0x1D JPEG8 0x1E RAW10 RAW8 RAW10 data from sensor is right shifted to produce RAW8 before it is send to memory 0x1F RAW8 DPCM12 RAW12 VP Used predictor is selected by the DPCM_PRED bit 0x20 RAW10 RAW8 ALAW 0x21 RAW8 DPCM10 ALAW 1 REGION_EN Enables the setting of regions of interest in the frame R...

Page 1361: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CHAN_ID FEC FSC LEC LSC Bits Field Name Description Type Reset 31 20 RESERVED Write 0s for future compatibility Read returns 0 RW 0x000 19 16 CHAN_ID Logical channel x identifier RW 0x0 for LC0 The channel identifier is located between bits 4 to 7 in the 0x1 for LC1 32 bit synchronization codes 0x2 for LC2 0x3 for LC3 15 12 FEC Logical c...

Page 1362: ...g Frame Processing 0 Camera ISP CSI1 CCP2B Video Port 1 Camera ISP CSI1 CCP2B Status Data 2 3 Camera ISP Register Manual Camera ISP CCP2 Register Summary 4 Table 6 178 CCP2_LCx_STAT_SIZE Address Offset 0x0000 005C x 0x30 Index x 0 to 3 Physical Address 0x480B C45C x 0x30 Instance ISP_CCP2 Description STATUS LINE SIZE REGISTER LOGICAL CHANNEL x This register is shadowed modifications are taken into...

Page 1363: ...bility During Frame Processing 0 Camera ISP CSI1 CCP2B Status Data 1 Camera ISP Register Manual Camera ISP CCP2 Register Summary 2 Table 6 182 CCP2_LCx_EOF_ADDR Address Offset 0x0000 0064 x 0x30 Index x 0 to 3 Physical Address 0x480B C464 x 0x30 Instance ISP_CCP2 Description EOF STATUS LINE MEMORY ADDRESS REGISTER LOGICAL CHANNEL x This register sets the 32 bit memory address where the EOF data ar...

Page 1364: ...Camera ISP CCP2 Register Summary 2 Table 6 186 CCP2_LCx_DAT_SIZE Address Offset 0x0000 006C x 0x30 Index x 0 to 3 Physical Address 0x480B C46C x 0x30 Instance ISP_CCP2 Description DATA SIZE REGISTER LOGICAL CHANNEL x This register is shadowed modifications are taken into account after the next FSC synchronization code Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 ...

Page 1365: ...ion 2 3 4 5 Camera ISP Register Manual Camera ISP CCP2 Register Summary 6 Camera ISP CCP2 Register Description 7 Table 6 190 CCP2_LCx_DAT_PONG_ADDR Address Offset 0x0000 0074 x 0x30 Index x 0 to 3 Physical Address 0x480B C474 x 0x30 Instance ISP_CCP2 Description DATA MEMORY PONG ADDRESS REGISTER LOGICAL CHANNEL x This register sets the 32 bit memory address where the pixel data are stored The dest...

Page 1366: ...2 1 0 OFST RESERVED Bits Field Name Description Type Reset 31 5 OFST Line offset programmed in bytes RW 0x0000000 If OFST 0 the data are written contiguously in memory Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line 1 4 0 RESERVED Write 0s for future compatibility Read returns 0 RW 0x00 1 An Interconnect access read wr...

Page 1367: ...s packed and must be unpacked RW 0x0 0x0 Disabled 0x1 Enabled 22 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 21 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 19 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 18 16 SRC_FORMAT Data format of the data stored in memory RW 0x0 Because there is no header embedded in the data sent to memory the us...

Page 1368: ...red correctly before the bit is set This bit is cleared by hardware at the end of the frame 0x0 Disabled 0x1 Enabled Table 6 195 Register Call Summary for Register CCP2_LCM_CTRL Camera ISP Functional Description Camera ISP CSI1 CCP2B Memory Read Channel 4 5 6 7 8 9 10 11 12 Camera ISP Basic Programming Model Camera ISP CSI1 CCP2B Read Data from Memory 13 14 15 16 17 18 19 20 Camera ISP Register Ma...

Page 1369: ...ns 0 RW 0x0 12 0 SKIP Horizontal count of pixels to skip after the start of the line RW 0x000 Valid values 0 8191 0 disables pixel skipping Table 6 199 Register Call Summary for Register CCP2_LCM_HSIZE Camera ISP Functional Description Camera ISP CSI1 CCP2B Memory Read Channel 0 1 Camera ISP Basic Programming Model Camera ISP CSI1 CCP2B Read Data from Memory 2 3 4 5 Camera ISP Register Manual Came...

Page 1370: ...4 3 2 1 0 ADDR RESERVED Bits Field Name Description Type Reset 31 5 ADDR 27 MSBs of the 32 bit address RW 0x0000000 4 0 RESERVED 5 LSBs of the 32 bit address RW 0x00 Write 0s for future compatibility Read returns 0 Table 6 203 Register Call Summary for Register CCP2_LCM_SRC_ADDR Camera ISP Functional Description Camera ISP CSI1 CCP2B Memory Read Channel 0 1 Camera ISP Basic Programming Model Camer...

Page 1371: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR RESERVED Bits Field Name Description Type Reset 31 5 ADDR 27 MSBs of the 32 bit address RW 0x0000000 4 0 RESERVED 5 least significant bits of the 32 bit address RW 0x00 Write 0s for future compatibility Read returns 0 Table 6 207 Register Call Summary for Register CCP2_LCM_DST_ADDR Camera ISP Functional Description Camera ISP CSI1 CCP2B Memory Read Chan...

Page 1372: ...8 0x480B C608 CCDC_HD_VD_WID RW 32 0x0000 000C 0x480B C60C CCDC_PIX_LINES RW 32 0x0000 0010 0x480B C610 CCDC_HORZ_INFO RW 32 0x0000 0014 0x480B C614 CCDC_VERT_START RW 32 0x0000 0018 0x480B C618 CCDC_VERT_LINES RW 32 0x0000 001C 0x480B C61C CCDC_CULLING RW 32 0x0000 0020 0x480B C620 CCDC_HSIZE_OFF RW 32 0x0000 0024 0x480B C624 CCDC_SDOFST RW 32 0x0000 0028 0x480B C628 CCDC_SDR_ADDR RW 32 0x0000 00...

Page 1373: ...CID PREV Bits Field Name Description Type Reset 31 24 RESERVED Write 0s for future compatibility Reads returns 0 R 0x00 23 16 TID Peripheral identification CCDC module R 0x01 15 8 CID Class identification Camera ISP R 0xFE 7 0 PREV Peripheral revision number R TI internal data Table 6 212 Register Call Summary for Register CCDC_PID Camera ISP Register Manual Camera ISP CCDC Register Summary 0 Tabl...

Page 1374: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATSIZ LPF WEN PACK8 VDPOL HDPOL EXWEN FLDPOL VP2SDR INPMOD FLDOUT VDHDEN FLDSTAT SDR2RSZ DATAPOL FLDMODE VDHDOUT Bits Field Name Description Type Reset 31 20 RESERVED Write 0s for future compatibility RW 0x000 Reads returns 0 19 SDR2RSZ Memory port output into the RESIZER input RW 0x0 Controls whether or not the memory port output data are forwarded to the ...

Page 1375: ...VS signals are used 0x0 Disable 0x1 Enable 15 FLDSTAT cam_fld signal status R 0x0 This bit field applies only if the CCDC module is configured to work in interlaced mode CCDC_SYN_MODE FLDMODE interlaced It indicates the status of the current field 0x0 Odd field 0x1 Even field 14 LPF Three tap low pass antialiasing filter enable RW 0x0 This bit field is latched by the VS sync pulse 0x0 Filter is di...

Page 1376: ... Environment Camera ISP ITU R BT 656 Protocol and Data Formats 8 10 Bits 0 Camera ISP Functional Description Camera ISP CCDC Block Diagram 1 2 Camera ISP CCDC Functional Operations 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Camera ISP VPBE Resizer Input and Output Interfaces 20 Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ...

Page 1377: ...DC_SYN_MODE VDHDOUT 0 This bit field is latched by the VS sync pulse Table 6 218 Register Call Summary for Register CCDC_HD_VD_WID Camera ISP Functional Description Camera ISP CCDC Functional Operations 0 1 Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 2 Camera ISP CCDC Register Accessibility During Frame Processing 3 Camera ISP CCDC Image Sensor Configuration 4 5 Camera ISP Re...

Page 1378: ...C Register Setup 2 Camera ISP CCDC Register Accessibility During Frame Processing 3 Camera ISP CCDC Image Sensor Configuration 4 5 6 Camera ISP Register Manual Camera ISP CCDC Register Summary 7 Table 6 221 CCDC_HORZ_INFO Address Offset 0x0000 0014 Physical Address 0x480B C614 Instance ISP_CCDC Description HORIZONTAL PIXEL INFO REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 1379: ...art line vertical field0 RW 0x0000 Sets the line at which data output to memory begins It is measured from the start of the VS sync pulse This bit field is latched by the VS sync pulse 15 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 14 0 SLV1 Start line vertical field1 RW 0x0000 Sets the line at which data output to memory begins It is measured from the start of the VS sync pu...

Page 1380: ...ster Summary 6 Table 6 227 CCDC_CULLING Address Offset 0x0000 0020 Physical Address 0x480B C620 Instance ISP_CCDC Description CULL CONTROL REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CULHEVN CULHODD RESERVED CULV Bits Field Name Description Type Reset 31 24 CULHEVN Horizontal culling patterns for even lines RW 0xFF Sets an 8 bit mask 0 cul...

Page 1381: ...he 5 least significant bits are ignored Usually the line offset is equal to the line length in bytes that is the line length must be a multiple of 32 bytes If LNOFST 0 the data is written again and again over the same line For optimal performance in the system the address offset must be on a 256 byte boundary This bit field is latched by the VS sync pulse Table 6 230 Register Call Summary for Regi...

Page 1382: ...This bit field is latched by the VS sync pulse 0x0 1 line 0x1 2 lines 0x2 3 lines 0x3 4 lines 0x4 1 line 0x5 2 lines 0x6 3 lines 0x7 4 lines 8 6 LOFST1 Line offset values of odd lines and even fields RW 0x0 field id 0 This bit field is latched by the VS sync pulse 0x0 1 line 0x1 2 lines 0x2 3 lines 0x3 4 lines 0x4 1 line 0x5 2 lines 0x6 3 lines 0x7 4 lines 5 3 LOFST2 Line offset values of even lin...

Page 1383: ...e ISP_CCDC Description MEMORY ADDRESS REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Bits Field Name Description Type Reset 31 0 ADDR Memory address RW 0x00000000 Sets the CCDC module output address The address should be aligned on a 32 byte boundary the 5 least significant bits are ignored For optimal performance in the system the addre...

Page 1384: ...to include in the average calculation 0x0 1 line 0x1 2 lines 0x2 4 lines 0x3 8 lines 0x4 16 lines 24 10 OBST Start pixel of optical black samples RW 0x0000 Start pixel position of optical black samples specified from the start of HS in pixel clocks 9 5 RESERVED Write 0s for future compatibility RW 0x00 Reads returns 0 4 0 OBGAIN Gain to apply to the optical black average RW 0x10 The gain value is ...

Page 1385: ...egister CCDC_DCSUB Camera ISP Functional Description Camera ISP CCDC Functional Operations 0 1 Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 2 3 Camera ISP CCDC Image Signal Processing 4 Camera ISP Register Manual Camera ISP CCDC Register Summary 5 Table 6 239 CCDC_COLPTN Address Offset 0x0000 0038 Physical Address 0x480B C638 Instance ISP_CCDC Description COLOR PATTERN REGISTE...

Page 1386: ...R Ye 0x1 Gr Cy 0x2 Gb G 0x3 B Mg 19 18 CP2PLC1 Color pattern 2nd line pixel counter 1 RW 0x0 0x0 R Ye 0x1 Gr Cy 0x2 Gb G 0x3 B Mg 17 16 CP2PLC0 Color pattern 2nd line pixel counter 0 RW 0x0 0x0 R Ye 0x1 Gr Cy 0x2 Gb G 0x3 B Mg 15 14 CP1PLC3 Color pattern 1st line pixel counter 3 RW 0x0 0x0 R Ye 0x1 Gr Cy 0x2 Gb G 0x3 B Mg 13 12 CP1PLC2 Color pattern 1st line pixel counter 2 RW 0x0 0x0 R Ye 0x1 Gr ...

Page 1387: ...x2 Gb G 0x3 B Mg Table 6 240 Register Call Summary for Register CCDC_COLPTN Camera ISP Functional Description Camera ISP CCDC Functional Operations 0 Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 1 Camera ISP CCDC Image Sensor Configuration 2 3 Camera ISP CCDC Summary of Constraints 4 Camera ISP Register Manual Camera ISP CCDC Register Summary 5 Table 6 241 CCDC_BLKCMP Address ...

Page 1388: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FPNUM FPERR FPCEN Bits Field Name Description Type Reset 31 17 RESERVED Write 0s for future compatibility RW 0x0000 Reads returns 0 16 FPERR Fault pixel correction error RW 0x0 This bit is set when the CCDC module is unable to fetch the required fault pixel table entry in time Write 1 to clear the error or end_of_frame clears it automatically for the ...

Page 1389: ...ime Table 6 244 Register Call Summary for Register CCDC_FPC Camera ISP Functional Description Camera ISP CCDC Functional Operations 0 3 Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 4 5 6 Camera ISP CCDC Enable Disable Hardware 7 8 9 Camera ISP CCDC Interrupts 10 11 Camera ISP CCDC Status Checking 12 Camera ISP CCDC Image Signal Processing 13 14 15 Camera ISP Central Resource S...

Page 1390: ...horizontal lines from the start of the VS sync pulse The resulting value is VDINT0 1 Note that if the rising edge or falling edge if programmed of the HS sync pulse lines up with the rising edge or falling edge if programmed of VS sync pulse the first HS sync pulse is not counted 15 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 14 0 VDINT1 VD1 interrupt timing RW 0x0000 Specifi...

Page 1391: ...er CCDC_ALAW Camera ISP Functional Description Camera ISP CCDC Functional Operations 0 1 2 Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 3 4 5 Camera ISP CCDC Image Signal Processing 6 7 Camera ISP Register Manual Camera ISP CCDC Register Summary 8 Table 6 251 CCDC_REC656IF Address Offset 0x0000 0050 Physical Address 0x480B C650 Instance ISP_CCDC Description ITU R BT 656 CONFIG...

Page 1392: ...4 3 2 1 0 RESERVED FIDMD VDLC BSWD BW656 Y8POS MSBINVI WENLOG RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Bits Field Name Description Type Reset 31 16 RESERVED Write 0s for future compatibility RW 0x0000 Reads returns 0 15 VDLC Enable latching function registers on the internal VS sync RW 0x0 pulse If this bit is set all the register fields that are VS pulse latched take on new values im...

Page 1393: ...d when the VD signal is active and the HD signal is inactive opposite phase 5 BW656 The data width in ITU R BT656 input mode RW 0x0 This bit field takes precedence over the CCDC_SYN_MODE INPMOD and CCDC_DATSIZ bit fields if the ITU mode is enabled with CCDC_REC656IF R656ON 1 0x0 8 bits 0x1 10 bits 4 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 3 RESERVED Write 0s for future co...

Page 1394: ...s Interconnect VPIF_FRQ 2 The valid range for VPIF_FRQ is 0 62 15 VPEN Video port enable This bit shall be enabled to send data RW 0 to the PREVIEW H3A and HIST modules 0x0 Disable 0x1 Enable 14 12 VPIN 10 bit input select for video port RW 0x4 0x3 bits 12 3 0x4 bits 11 2 0x5 bits 10 1 0x6 bits 9 0 11 8 PLEN_EVEN Number of program entries in even line minus 1 RW 0x0 If the desired number of progra...

Page 1395: ...sical Address 0x480B C65C Instance ISP_CCDC Description DATA REFORMATTER HORIZ INFO REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMTSPH FMTLNH RESERVED RESERVED Bits Field Name Description Type Reset 31 29 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 28 16 FMTSPH Start pixel horizontal from start of the HS sync pulse RW...

Page 1396: ...ions 0 Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 1 Camera ISP CCDC Pixel Selection Framing Register Dependencies 2 Camera ISP CCDC Image Signal Processing 7 Camera ISP CCDC Summary of Constraints 8 Camera ISP Register Manual Camera ISP CCDC Register Summary 9 Camera ISP CCDC Register Description 10 Table 6 261 CCDC_FMT_ADDR_i Address Offset 0x0000 0064 i 0x4 Index i 0 to 7 ...

Page 1397: ...NES REGISTER Each bit field in this register is programmed in the same way The following definition applies where n ranges from 0 to 8 Bits 4 n 3 4 n 1 000 ADDR0 001 ADDR1 010 ADDR2 011 ADDR3 100 ADDR4 101 ADDR5 110 ADDR6 111 ADDR7 Bit 4 n 0 Auto increment 1 Auto decrement Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVEN7 EVEN6 EVEN5 EVEN4 EVEN3 EV...

Page 1398: ...CDC_PRGEVEN1 Camera ISP Functional Description Camera ISP CCDC Functional Operations 0 Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 1 Camera ISP CCDC Image Signal Processing 2 Camera ISP Register Manual Camera ISP CCDC Register Summary 3 Table 6 267 CCDC_PRGODD0 Address Offset 0x0000 008C Physical Address 0x480B C68C Instance ISP_CCDC Description PROGRAM ENTRIES 0 7 FOR ODD LI...

Page 1399: ...ement Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODD15 ODD14 ODD13 ODD12 ODD11 ODD10 ODD9 ODD8 Bits Field Name Description Type Reset 31 28 ODD15 Address update See register description RW 0x0 27 24 ODD14 Address update See register description RW 0x0 23 20 ODD13 Address update See register description RW 0x0 19 16 ODD12 Address update See registe...

Page 1400: ...lowed is 1376 if original input is broken down to 4 lines The maximum offset allowed is 1376 if original input is broken down to 3 lines The maximum offset allowed is 2 1376 if original input is broken down to 2 lines The maximum offset allowed is 4 1376 if original input is broken down to 1 line 3 0 HORZ_ST Horizontal start pixel in each output line RW 0x0 The maximum value allowed is 15 The vide...

Page 1401: ... M 32 0x6 Paxel is 64 pixels tall M 64 11 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 10 8 GAIN_MODE_N Define the vertical dimension of a paxel Possible values RW 0x6 are listed below 0x2 Paxel is 4 pixels tall N 4 0x3 Paxel is 8 pixels tall N 8 0x4 Paxel is 16 pixels tall N 16 0x5 Paxel is 32 pixels tall N 32 0x6 Paxel is 64 pixels tall N 64 7 BUSY Module busy or idle R 0x0 0x...

Page 1402: ...ting the module Data processing is only effective at the start of the next frame Note that preview module dark frame subtract must be disabled because there is only one shared read port Table 6 274 Register Call Summary for Register CCDC_LSC_CONFIG Camera ISP Functional Description Camera ISP CCDC Functional Operations Camera ISP Basic Programming Model Camera ISP CCDC Register Setup 2 3 4 Camera ...

Page 1403: ...5 4 3 2 1 0 BASE Bits Field Name Description Type Reset 31 0 BASE Table address in bytes Table is 32 bit aligned so this RW 0x00000000 register must be a multiple of 4 This bit field sets the address of the gain table in memory Table 6 278 Register Call Summary for Register CCDC_LSC_TABLE_BASE Camera ISP Functional Description Camera ISP CCDC Functional Operations Camera ISP Basic Programming Mode...

Page 1404: ...mary Table 6 281 ISP_HIST Register Summary Register Name Type Register Width Bits Address Offset Physical Address HIST_PID R 32 0x0000 0000 0x480B CA00 HIST_PCR RW 32 0x0000 0004 0x480B CA04 HIST_CNT RW 32 0x0000 0008 0x480B CA08 HIST_WB_GAIN RW 32 0x0000 000C 0x480B CA0C HIST_Rn_HORZ 1 RW 32 0x0000 0010 n 0x8 0x480B CA10 n 0x8 HIST_Rn_VERT 1 RW 32 0x0000 0014 n 0x8 0x480B CA14 n 0x8 HIST_ADDR RW ...

Page 1405: ...ED BUSY ENABLE Bits Field Name Description Type Reset 31 2 RESERVED Write 0s for future compatibility RW 0x00000000 Reads returns 0 1 BUSY HIST module busy RW 0x0 0x0 Module is not busy 0x1 Module is busy 0 ENABLE HIST module enable RW 0x0 0x0 Disable module 0x1 Enable module Table 6 285 Register Call Summary for Register HIST_PCR Camera ISP Functional Description Camera ISP Basic Programming Mode...

Page 1406: ...Number of bins RW 0x0 0x0 32 bins REGIONS 0 1 2 and 3 are active 0x1 64 bins REGIONS 0 1 2 and 3 are active 0x2 128 bins REGIONS 0 and 1 are active 0x3 256 bins REGION 0 is active 3 SOURCE Input source RW 0x0 0x0 The input data comes from the CCDC module 0x1 The input data comes from memory 2 0 SHIFT Shift value RW 0x0 The pixel data is right shifted before the binning operation The shift value ca...

Page 1407: ... 7 96875 Table 6 289 Register Call Summary for Register HIST_WB_GAIN Camera ISP Functional Description Camera ISP Histogram White Balance 0 2 Camera ISP Basic Programming Model Camera ISP Histogram Register Setup 3 Camera ISP Register Manual Camera ISP HIST Register Summary 4 Table 6 290 HIST_Rn_HORZ Address Offset 0x0000 0010 n 0x8 Index n 0 to 3 Physical Address 0x480B CA10 n 0x8 Instance ISP_HI...

Page 1408: ...ibility RW 0x0 Reads returns 0 29 16 VSTART Vertical start position for REGION n RW 0x0000 From 0 to 16383 15 14 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 13 0 VEND Vertical end position for REGION n RW 0x0000 From 0 to 16383 Table 6 293 Register Call Summary for Register HIST_Rn_VERT Camera ISP Functional Description Camera ISP Histogram Binning 0 1 Camera ISP Basic Progra...

Page 1409: ...DATA Histogram data RW 0x The histogram memory has 1024 entries Each entry is coded on 20 bits Table 6 297 Register Call Summary for Register HIST_DATA Camera ISP Functional Description Camera ISP Basic Programming Model Camera ISP Histogram Register Accessibility During Frame Processing 3 Camera ISP Register Manual Camera ISP HIST Register Summary 4 Table 6 298 HIST_RADD Address Offset 0x0000 003...

Page 1410: ...Offset value RW 0x0000 The 5 LSBs are ignored the offset must be a multiple of 32 bytes Table 6 301 Register Call Summary for Register HIST_RADD_OFF Camera ISP Functional Description Camera ISP Histogram Input Interface 0 Camera ISP Basic Programming Model Camera ISP Histogram Register Setup 1 Camera ISP Histogram Register Accessibility During Frame Processing 2 Camera ISP Register Manual Camera I...

Page 1411: ...0x0000 0010 0x480B CC10 H3A_AFIIRSH RW 32 0x0000 0014 0x480B CC14 H3A_AFBUFST RW 32 0x0000 0018 0x480B CC18 H3A_AFCOEF010 RW 32 0x0000 001C 0x480B CC1C H3A_AFCOEF032 RW 32 0x0000 0020 0x480B CC20 H3A_AFCOEF054 RW 32 0x0000 0024 0x480B CC24 H3A_AFCOEF076 RW 32 0x0000 0028 0x480B CC28 H3A_AFCOEF098 RW 32 0x0000 002C 0x480B CC2C H3A_AFCOEF0010 RW 32 0x0000 0030 0x480B CC30 H3A_AFCOEF110 RW 32 0x0000 ...

Page 1412: ... CC04 Instance ISP_H3A Description PERIPHERAL CONTROL REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AVE2LMT RGBPOS MED_TH AF_EN BUSYAF AEW_EN FVMODE RESERVED AF_MED_EN BUSYAEAWB AF_ALAW_EN AEW_ALAW_EN Bits Field Name Description Type Reset 31 22 AVE2LMT AE AWB saturation limit RW 0x3FF All pixels in a block are compared to this limit If one ...

Page 1413: ... Camera ISP H3A AE AWB Engine Camera ISP Basic Programming Model Camera ISP H3A Register Setup 7 8 9 10 11 12 13 14 15 16 Camera ISP H3A Enable Disable Hardware 17 18 19 20 Camera ISP H3A Register Accessibility During Frame Processing 21 22 23 24 25 Camera ISP H3A Interframe Operations 26 Camera ISP Histogram Interframe Operations 27 Camera ISP Register Manual Camera ISP H3A Register Summary 28 Ta...

Page 1414: ...cription Type Reset 31 17 RESERVED Write 0s for future compatibility RW 0x0000 Reads returns 0 16 13 AFINCV AF line increments RW 0x0 The number of lines to skip in a paxel is set by 2 x AFINCV 1 12 6 PAXVC Paxel count in the vertical direction RW 0x00 The number of paxels in the vertical direction is set by PAXVC 1 It is illegal to have more than 128 paxels in the vertical direction We have 0 PAX...

Page 1415: ...RT Camera ISP Functional Description Camera ISP H3A Autofocus Engine Camera ISP Basic Programming Model Camera ISP H3A Register Setup 2 Camera ISP Register Manual Camera ISP H3A Register Summary 3 Table 6 315 H3A_AFIIRSH Address Offset 0x0000 0014 Physical Address 0x480B CC14 Instance ISP_H3A Description AF IIR HORIZONTAL START POSITION REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 1416: ... Camera ISP H3A Register Accessibility During Frame Processing 2 Camera ISP Register Manual Camera ISP H3A Register Summary 3 Table 6 319 H3A_AFCOEF010 Address Offset 0x0000 001C Physical Address 0x480B CC1C Instance ISP_H3A Description IIR FILTER COEF DATA REGISTER SET 0 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEFF1 RESERVED COEFF0 B...

Page 1417: ...AF IIR filter coefficient 2 set0 RW 0x000 The coefficient value is signed in S12Q6 representation The range is 32 coeff 31 96875 Table 6 322 Register Call Summary for Register H3A_AFCOEF032 Camera ISP Register Manual Camera ISP H3A Register Summary 0 Table 6 323 H3A_AFCOEF054 Address Offset 0x0000 0024 Physical Address 0x480B CC24 Instance ISP_H3A Description IIR FILTER COEF DATA REGISTER SET 0 Ty...

Page 1418: ...signed in S12Q6 representation The range is 32 coeff 31 96875 Table 6 326 Register Call Summary for Register H3A_AFCOEF076 Camera ISP Register Manual Camera ISP H3A Register Summary 0 Table 6 327 H3A_AFCOEF098 Address Offset 0x0000 002C Physical Address 0x480B CC2C Instance ISP_H3A Description IIR FILTER COEF DATA REGISTER SET 0 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 1419: ...er Summary 1 Table 6 331 H3A_AFCOEF110 Address Offset 0x0000 0034 Physical Address 0x480B CC34 Instance ISP_H3A Description IIR FILTER COEF DATA REGISTER SET 1 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEFF1 RESERVED COEFF0 Bits Field Name Description Type Reset 31 28 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 27 ...

Page 1420: ...2 Camera ISP Register Manual Camera ISP H3A Register Summary 0 Table 6 335 H3A_AFCOEF154 Address Offset 0x0000 003C Physical Address 0x480B CC3C Instance ISP_H3A Description IIR FILTER COEF DATA REGISTER SET 1 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEFF5 RESERVED COEFF4 Bits Field Name Description Type Reset 31 28 RESERVED Write 0s f...

Page 1421: ... Camera ISP Register Manual Camera ISP H3A Register Summary 0 Table 6 339 H3A_AFCOEF198 Address Offset 0x0000 0044 Physical Address 0x480B CC44 Instance ISP_H3A Description IIR FILTER COEF DATA REGISTER SET 1 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEFF9 RESERVED COEFF8 Bits Field Name Description Type Reset 31 28 RESERVED Write 0s fo...

Page 1422: ...e 6 343 H3A_AEWWIN1 Address Offset 0x0000 004C Physical Address 0x480B CC4C Instance ISP_H3A Description AE AWB CONTROL REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WINH RESERVED WINW WINVC WINHC RESERVED Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 30 24 WINH AE AWB window heig...

Page 1423: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED WINSV RESERVED WINSH Bits Field Name Description Type Reset 31 28 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 27 16 WINSV AE AWB vertical window start position RW 0x000 Sets the first line for the first window The range is 0 to 4095 15 12 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 11 0 WINSH AE AWB hor...

Page 1424: ...for Register H3A_AEWINBLK Camera ISP Functional Description Camera ISP H3A AE AWB Engine Camera ISP Basic Programming Model Camera ISP H3A Register Setup 2 Camera ISP Register Manual Camera ISP H3A Register Summary 3 Table 6 349 H3A_AEWSUBWIN Address Offset 0x0000 0058 Physical Address 0x480B CC58 Instance ISP_H3A Description AE AWB REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 1425: ...D Write 0s for future compatibility RW 0x00 Reads returns 0 Table 6 352 Register Call Summary for Register H3A_AEWBUFST Camera ISP Functional Description Camera ISP H3A AE AWB Engine Camera ISP Basic Programming Model Camera ISP H3A Register Setup 1 Camera ISP H3A Register Accessibility During Frame Processing 2 Camera ISP Register Manual Camera ISP H3A Register Summary 3 6 6 7 Camera ISP PREVIEW ...

Page 1426: ...W 32 0x0000 0068 0x480B CE68 PRV_CSC2 RW 32 0x0000 006C 0x480B CE6C PRV_CSC_OFFSET RW 32 0x0000 0070 0x480B CE70 PRV_CNT_BRT RW 32 0x0000 0074 0x480B CE74 PRV_CSUP RW 32 0x0000 0078 0x480B CE78 PRV_SETUP_YC RW 32 0x0000 007C 0x480B CE7C PRV_SET_TBL_ADDR RW 32 0x0000 0080 0x480B CE80 PRV_SET_TBL_DATA RW 32 0x0000 0084 0x480B CE84 PRV_CDC_THRx 1 RW 32 0x0000 0090 x 0x4 0x480B CE90 x 0x4 1 x 0 to 3 6...

Page 1427: ...or 0x1 Error 30 29 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 28 DCOR_METHOD Defect correction method RW 0x0 0x0 MinMax 0x1 MinMax2 Couplet defect correction 27 DCOREN Defect correction enable RW 0x0 This bit enables or disables the defect correction The PRV_PCR DCOR_METHOD and PRV_CDC_THRx registers must be configured for correct operation 0x0 Disable defect correction 0x1 ...

Page 1428: ... Cr0 31 24 Y1 23 16 Cb0 15 8 Y0 7 0 RW 0x0 0x0 YCRYCB Y1 31 24 Cr0 23 16 Y0 15 8 Cb0 7 0 0x1 YCBYCR Y1 31 24 Cb0 23 16 Y0 15 8 Cr0 7 0 0x2 CBYCRY Cb0 31 24 Y1 23 16 Cr 15 8 Y0 7 0 0x3 CRYCBY Cr0 31 24 Y1 23 16 Cb0 15 8 Y0 7 0 16 SUPEN Color suppression RW 0x0 0x0 Disable 0x1 Enable 15 YNENHEN Non linear enhancer RW 0x0 0x0 Disable 0x1 Enable 14 11 CFAFMT CFA format RW 0x0 0x0 Mode 0 conventional B...

Page 1429: ...ding Compensation 6 7 8 9 10 Camera ISP VPBE Preview Horizontal Median Filter Camera ISP VPBE Preview Noise Filter and Faulty Pixel Correction 18 19 Camera ISP VPBE Preview White Balance Camera ISP VPBE Preview CFA Interpolation 22 23 Camera ISP VPBE Preview Gamma Correction 25 Camera ISP VPBE Preview RGB to YCbCr Conversion Luminance Enhancement Chrominance Suppression Contrast and Brightness and...

Page 1430: ... AVE register settings If PRV_PCR SOURCE 0 CCDC input EPH must be 2 pixels before the last pixel sent from the CCDC PRV_HORZ_INFO EPH PRV_HORZ_INFO SPH 1 MOD 1 PRV_AVE COUNT LeastCommonMultiple PRV_AVE ODDDIST 1 PRV_AVE EVENDIST 1 0 Table 6 359 Register Call Summary for Register PRV_HORZ_INFO Camera ISP Functional Description Camera ISP VPBE Preview Input Interface 0 Camera ISP Basic Programming M...

Page 1431: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RADR Bits Field Name Description Type Reset 31 0 RADR 32 bit read address RW 0x00000000 Specifies the 32 bit address in memory of the input frame The lower 5 bits of this register are always treated as 0s The offset should be aligned on a 32 byte boundary This field can be altered even when the PREVIEW module is busy The change takes place only f...

Page 1432: ...ET Camera ISP Functional Description Camera ISP VPBE Preview Input Interface 0 Camera ISP Basic Programming Model Camera ISP Preview Register Setup 1 Camera ISP Preview Register Accessibility During Frame Processing 2 Camera ISP Register Manual Camera ISP PREVIEW Register Summary 3 Table 6 366 PRV_DSDR_ADDR Address Offset 0x0000 0018 Physical Address 0x480B CE18 Instance ISP_PREVIEW Description DA...

Page 1433: ...elatively to the previous line The lower 5 bits of this register are always treated as 0s The offset should be aligned on a 32 byte boundary This field can be altered even when the PREVIEW module is busy The change takes place only for the next frame next VS pulse However note that reading this register always gives the latest value Table 6 369 Register Call Summary for Register PRV_DRKF_OFFSET Ca...

Page 1434: ...0x480B CE24 Instance ISP_PREVIEW Description MEMORY WRITE OFFSET REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OFFSET Bits Field Name Description Type Reset 31 16 RESERVED Write 0s for future compatibility RW 0x0000 Reads returns 0 15 0 OFFSET Line offset RW 0x0000 The lower 5 bits of this register are always treated as 0s The offse...

Page 1435: ... of horizontal pixels to average RW 0x0 This field should not be changed when the PRV_PCR DRKFEN bit is set to 1 The input width must be divisible by the number of horizontal pixels to average indicated by this field if 4 pixel average is selected then the input width must be a multiple of 4 0x0 No averaging 0x1 2 pixel average 0x2 4 pixel average 0x3 8 pixel average Table 6 375 Register Call Summ...

Page 1436: ...y for Register PRV_HMED Camera ISP Functional Description Camera ISP VPBE Preview Horizontal Median Filter Camera ISP Basic Programming Model Camera ISP Preview Register Setup 3 Camera ISP Register Manual Camera ISP PREVIEW Register Summary 4 Table 6 378 PRV_NF Address Offset 0x0000 0030 Physical Address 0x480B CE30 Instance ISP_PREVIEW Description NOISE FILTER REGISTER Type RW 31 30 29 28 27 26 2...

Page 1437: ...SP Basic Programming Model Camera ISP Preview Register Setup 1 Camera ISP Preview Register Accessibility During Frame Processing 2 Camera ISP Register Manual Camera ISP PREVIEW Register Summary 3 Table 6 382 PRV_WBGAIN Address Offset 0x0000 0038 Physical Address 0x480B CE38 Instance ISP_PREVIEW Description WHITE BALANCE COEF REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 1438: ...ANCE COEF SELECTION REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N3_3 N3_2 N3_1 N3_0 N2_3 N2_2 N2_1 N2_0 N1_3 N1_2 N1_1 N1_0 N0_3 N0_2 N0_1 N0_0 Bits Field Name Description Type Reset 31 30 N3_3 Coefficient selection for 3rd line 3rd pixel RW 0x3 0x0 COEF0 0x1 COEF1 0x2 COEF2 0x3 COEF3 29 28 N3_2 Coefficient selection for 3rd line 2rd pixel...

Page 1439: ...F0 0x1 COEF1 0x2 COEF2 0x3 COEF3 13 12 N1_2 Coefficient selection for 1st line 2nd pixel RW 0x2 0x0 COEF0 0x1 COEF1 0x2 COEF2 0x3 COEF3 11 10 N1_1 Coefficient selection for 1st line 1st pixel RW 0x3 0x0 COEF0 0x1 COEF1 0x2 COEF2 0x3 COEF3 9 8 N1_0 Coefficient selection for 1st line 0th pixel RW 0x2 0x0 COEF0 0x1 COEF1 0x2 COEF2 0x3 COEF3 7 6 N0_3 Coefficient selection for 0th line 3rd pixel RW 0x1...

Page 1440: ...ress 0x480B CE40 Instance ISP_PREVIEW Description COLOR FILTER ARRAY REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED GRADTH_VER GRADTH_HOR Bits Field Name Description Type Reset 31 16 RESERVED Write 0s for future compatibility RW 0x0000 Reads returns 0 15 8 GRADTH_VER Gradient threshold vertical RW 0x00 7 0 GRADTH_HOR Gradient thresho...

Page 1441: ...amera ISP Preview Register Setup 1 Camera ISP Register Manual Camera ISP PREVIEW Register Summary 2 Table 6 390 PRV_RGB_MAT1 Address Offset 0x0000 0048 Physical Address 0x480B CE48 Instance ISP_PREVIEW Description RGB TO RGB MATRIX COEF REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MTX_GR RESERVED MTX_RR Bits Field Name Description ...

Page 1442: ...mat is in S12Q8 representation Table 6 393 Register Call Summary for Register PRV_RGB_MAT2 Camera ISP Functional Description Camera ISP VPBE Preview RGB Blending 0 Camera ISP Register Manual Camera ISP PREVIEW Register Summary 1 Table 6 394 PRV_RGB_MAT3 Address Offset 0x0000 0050 Physical Address 0x480B CE50 Instance ISP_PREVIEW Description RGB TO RGB MATRIX COEF REGISTER Type RW 31 30 29 28 27 26...

Page 1443: ... RW 0x100 The format is in S12Q8 representation Table 6 397 Register Call Summary for Register PRV_RGB_MAT4 Camera ISP Functional Description Camera ISP VPBE Preview RGB Blending 0 Camera ISP Register Manual Camera ISP PREVIEW Register Summary 1 Table 6 398 PRV_RGB_MAT5 Address Offset 0x0000 0058 Physical Address 0x480B CE58 Instance ISP_PREVIEW Description RGB TO RGB MATRIX COEF REGISTER Type RW ...

Page 1444: ...ster Call Summary for Register PRV_RGB_OFF1 Camera ISP Functional Description Camera ISP VPBE Preview RGB Blending 0 Camera ISP Basic Programming Model Camera ISP Preview Register Setup 1 Camera ISP Register Manual Camera ISP PREVIEW Register Summary 2 Table 6 402 PRV_RGB_OFF2 Address Offset 0x0000 0060 Physical Address 0x480B CE60 Instance ISP_PREVIEW Description RGB TO RGB MATRIX OFFSET REGISTER...

Page 1445: ...computing Y The format is in S10Q8 representation 9 0 CSCRY Color space conversion coefficient of RED for computing RW 0x04C Y The format is in S10Q8 representation Table 6 405 Register Call Summary for Register PRV_CSC0 Camera ISP Functional Description Camera ISP VPBE Preview RGB to YCbCr Conversion Luminance Enhancement Chrominance Suppression Contrast and Brightness and 4 2 2 Downsampling and ...

Page 1446: ...OLOR SPACE CONVERSION COEF REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSCBCR CSCGCR CSCRCR RESERVED Bits Field Name Description Type Reset 31 30 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 29 20 CSCBCR Color space conversion coefficient of BLUE for RW 0x3EC computing Cr The format is in S10Q8 representation 19 10 CSC...

Page 1447: ... for Register PRV_CSC_OFFSET Camera ISP Functional Description Camera ISP VPBE Preview RGB to YCbCr Conversion Luminance Enhancement Chrominance Suppression Contrast and Brightness and 4 2 2 Downsampling and Output Clipping 0 Camera ISP Register Manual Camera ISP PREVIEW Register Summary 1 Table 6 412 PRV_CNT_BRT Address Offset 0x0000 0074 Physical Address 0x480B CE74 Instance ISP_PREVIEW Descript...

Page 1448: ... high pass filter of luminance for chroma suppression RW 0x0 0x0 Disable Use luminance without high pass filter 0x1 Enable 15 8 CSUPTH Chroma suppression threshold RW 0x00 7 0 CSUPG Gain value for chroma suppression function RW 0x00 The data format is in U8Q8 representation Table 6 415 Register Call Summary for Register PRV_CSUP Camera ISP Functional Description Camera ISP VPBE Preview RGB to YCbC...

Page 1449: ...PREVIEW Register Summary 2 Table 6 418 PRV_SET_TBL_ADDR Address Offset 0x0000 0080 Physical Address 0x480B CE80 Instance ISP_PREVIEW Description SET TABLE ADDRESS REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ADDR Bits Field Name Description Type Reset 31 13 RESERVED Write 0s for future compatibility RW 0x00000 Reads returns 0 12 0 ...

Page 1450: ...e Description Type Reset 31 26 RESERVED Write 0s for future compatibility RW 0x00 Reads returns 0 25 16 CORRECT Correction threshold when couplet defect correction is RW 0x000 selected It must be set to 1023 for single defect correction 15 10 RESERVED Write 0s for future compatibility RW 0x00 Reads returns 0 9 0 DETECT Detection threshold when couplet defect correction is RW 0x000 selected It must...

Page 1451: ... 0x480B D050 RSZ_HFILT2322 RW 32 0x0000 0054 0x480B D054 RSZ_HFILT2524 RW 32 0x0000 0058 0x480B D058 RSZ_HFILT2726 RW 32 0x0000 005C 0x480B D05C RSZ_HFILT2928 RW 32 0x0000 0060 0x480B D060 RSZ_HFILT3130 RW 32 0x0000 0064 0x480B D064 RSZ_VFILT10 RW 32 0x0000 0068 0x480B D068 RSZ_VFILT32 RW 32 0x0000 006C 0x480B D06C RSZ_VFILT54 RW 32 0x0000 0070 0x480B D070 RSZ_VFILT76 RW 32 0x0000 0074 0x480B D074...

Page 1452: ... Address Offset 0x0000 0004 Physical Address 0x480B D004 Instance ISP_RESIZER Description PERIPHERAL CONTROL REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED BUSY ENABLE ONESHOT Bits Field Name Description Type Reset 31 3 RESERVED Write 0s for future compatibility RW 0x00000000 Reads returns 0 2 ONESHOT One shot or continuous mode sele...

Page 1453: ..._CNT Address Offset 0x0000 0008 Physical Address 0x480B D008 Instance ISP_RESIZER Description RESIZER CONTROL REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VSTPH HSTPH VRSZ HRSZ CBILIN YCPOS INPTYP INPSRC RESERVED Bits Field Name Description Type Reset 31 30 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 29 CBILIN Chromina...

Page 1454: ...ra ISP Functional Description Camera ISP VPBE Resizer Input and Output Interfaces 0 1 2 Camera ISP VPBE Resizer Horizontal and Vertical Resizing 3 4 5 6 7 8 9 10 11 Camera ISP VPBE Resizer Resampling Algorithm 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Camera ISP Basic Programming Model Camera ISP Resizer Register Setup 28 Camera ISP Resizer Processing Time Calculation 29 30 Camera ISP Resize...

Page 1455: ...l data comes from the PREVIEW module must be set to 0 is the input pixel data comes from memory Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VERT_ST HORZ_ST RESERVED RESERVED Bits Field Name Description Type Reset 31 29 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 28 16 VERT_ST Vertical start line RW 0x0000 This field makes sens...

Page 1456: ...13 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 12 0 HORZ Input width RW 0x0000 The range is 0 to 4095 pixels Table 6 436 Register Call Summary for Register RSZ_IN_SIZE Camera ISP Functional Description Camera ISP VPBE Resizer Input and Output Interfaces 0 1 2 3 Camera ISP VPBE Resizer Horizontal and Vertical Resizing 4 5 Camera ISP Basic Programming Model Camera ISP Resizer R...

Page 1457: ...This register must be set only if the input pixel data comes from memory Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OFFSET Bits Field Name Description Type Reset 31 16 RESERVED Write 0s for future compatibility RW 0x0000 Reads returns 0 15 0 OFFSET Memory offset for the input lines RW 0x0000 The 5 LSBs are forced to be zeros by the hardwa...

Page 1458: ... Basic Programming Model Camera ISP Resizer Register Setup 2 Camera ISP Resizer Register Accessibility During Frame Processing 3 Camera ISP Register Manual Camera ISP RESIZER Register Summary 4 Table 6 443 RSZ_SDR_OUTOFF Address Offset 0x0000 0024 Physical Address 0x480B D024 Instance ISP_RESIZER Description OUTPUT OFFSET REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12...

Page 1459: ... future compatibility RW 0x00 Reads returns 0 9 0 COEF0 10 bit coefficient S10Q8 format range of 2 to RW 0x000 1 255 256 1 is 0x100 Phase 0 tap 0 Table 6 446 Register Call Summary for Register RSZ_HFILT10 Camera ISP Functional Description Camera ISP VPBE Resizer Horizontal and Vertical Resizing 0 Camera ISP Basic Programming Model Camera ISP Resizer Register Setup 1 Camera ISP Register Manual Came...

Page 1460: ...ity RW 0x00 Reads returns 0 9 0 COEF4 10 bit coefficient S10Q8 format range of 2 to RW 0x000 1 255 256 1 is 0x100 Phase 0 1 tap 4 0 Table 6 450 Register Call Summary for Register RSZ_HFILT54 Camera ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 451 RSZ_HFILT76 Address Offset 0x0000 0034 Physical Address 0x480B D034 Instance ISP_RESIZER Description HORIZONTAL FILTER COEFFICIENTS ...

Page 1461: ... 6 454 Register Call Summary for Register RSZ_HFILT98 Camera ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 455 RSZ_HFILT1110 Address Offset 0x0000 003C Physical Address 0x480B D03C Instance ISP_RESIZER Description HORIZONTAL FILTER COEFFICIENTS 10 AND 11 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF11 RESERV...

Page 1462: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 459 RSZ_HFILT1514 Address Offset 0x0000 0044 Physical Address 0x480B D044 Instance ISP_RESIZER Description HORIZONTAL FILTER COEFFICIENTS 14 AND 15 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF15 RESERVED COEF14 Bits Field Name Description Type Reset 31 26 RE...

Page 1463: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 463 RSZ_HFILT1918 Address Offset 0x0000 004C Physical Address 0x480B D04C Instance ISP_RESIZER Description HORIZONTAL FILTER COEFFICIENTS 18 AND 19 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF19 RESERVED COEF18 Bits Field Name Description Type Reset 31 26 RE...

Page 1464: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 467 RSZ_HFILT2322 Address Offset 0x0000 0054 Physical Address 0x480B D054 Instance ISP_RESIZER Description HORIZONTAL FILTER COEFFICIENTS 22 AND 23 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF23 RESERVED COEF22 Bits Field Name Description Type Reset 31 26 RE...

Page 1465: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 471 RSZ_HFILT2726 Address Offset 0x0000 005C Physical Address 0x480B D05C Instance ISP_RESIZER Description HORIZONTAL FILTER COEFFICIENTS 26 AND 27 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF27 RESERVED COEF26 Bits Field Name Description Type Reset 31 26 RE...

Page 1466: ...LT3130 Address Offset 0x0000 0064 Physical Address 0x480B D064 Instance ISP_RESIZER Description HORIZONTAL FILTER COEFFICIENTS 30 AND 31 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF31 RESERVED COEF30 Bits Field Name Description Type Reset 31 26 RESERVED Write 0s for future compatibility RW 0x00 Reads returns 0 25 16 COEF31 10 ...

Page 1467: ...izing 0 Camera ISP Basic Programming Model Camera ISP Resizer Register Setup 1 Camera ISP Register Manual Camera ISP RESIZER Register Summary 2 Table 6 479 RSZ_VFILT32 Address Offset 0x0000 006C Physical Address 0x480B D06C Instance ISP_RESIZER Description VERTICAL FILTER COEFFICIENTS 2 AND 3 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES...

Page 1468: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 483 RSZ_VFILT76 Address Offset 0x0000 0074 Physical Address 0x480B D074 Instance ISP_RESIZER Description VERTICAL FILTER COEFFICIENTS 6 AND 7 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF7 RESERVED COEF6 Bits Field Name Description Type Reset 31 26 RESERVED W...

Page 1469: ...SP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 487 RSZ_VFILT1110 Address Offset 0x0000 007C Physical Address 0x480B D07C Instance ISP_RESIZER Description VERTICAL FILTER COEFFICIENTS 10 AND 11 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF11 RESERVED COEF10 Bits Field Name Description Type Reset 31 26 RESERVED ...

Page 1470: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 491 RSZ_VFILT1514 Address Offset 0x0000 0084 Physical Address 0x480B D084 Instance ISP_RESIZER Description VERTICAL FILTER COEFFICIENTS 14 AND 15 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF15 RESERVED COEF14 Bits Field Name Description Type Reset 31 26 RESE...

Page 1471: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 495 RSZ_VFILT1918 Address Offset 0x0000 008C Physical Address 0x480B D08C Instance ISP_RESIZER Description VERTICAL FILTER COEFFICIENTS 18 AND 19 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF19 RESERVED COEF18 Bits Field Name Description Type Reset 31 26 RESE...

Page 1472: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 499 RSZ_VFILT2322 Address Offset 0x0000 0094 Physical Address 0x480B D094 Instance ISP_RESIZER Description VERTICAL FILTER COEFFICIENTS 22 AND 23 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF23 RESERVED COEF22 Bits Field Name Description Type Reset 31 26 RESE...

Page 1473: ...era ISP Register Manual Camera ISP RESIZER Register Summary 0 Table 6 503 RSZ_VFILT2726 Address Offset 0x0000 009C Physical Address 0x480B D09C Instance ISP_RESIZER Description VERTICAL FILTER COEFFICIENTS 26 AND 27 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF27 RESERVED COEF26 Bits Field Name Description Type Reset 31 26 RESE...

Page 1474: ...LT3130 Address Offset 0x0000 00A4 Physical Address 0x480B D0A4 Instance ISP_RESIZER Description VERTICAL FILTER COEFFICIENTS 30 AND 31 REGISTER Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED COEF31 RESERVED COEF30 Bits Field Name Description Type Reset 31 26 RESERVED Write 0s for future compatibility RW 0x00 Reads returns 0 25 16 COEF31 10 bi...

Page 1475: ...mera ISP Functional Description Camera ISP VPBE Resizer Horizontal and Vertical Resizing 0 1 Camera ISP VPBE Resizer Luma Edge Enhancement 2 3 4 5 Camera ISP Basic Programming Model Camera ISP Resizer Register Setup 6 7 8 9 10 11 Camera ISP Resizer Summary of Constraints 12 13 Camera ISP Register Manual Camera ISP RESIZER Register Summary 14 6 6 9 Camera ISP SBL Registers 6 6 9 1 Camera ISP SBL Re...

Page 1476: ...78 0x480B D278 SBL_RSZ_RD_3 R 32 0x0000 007C 0x480B D27C SBL_RSZ1_WR_0 R 32 0x0000 0080 0x480B D280 SBL_RSZ1_WR_1 R 32 0x0000 0084 0x480B D284 SBL_RSZ1_WR_2 R 32 0x0000 0088 0x480B D288 SBL_RSZ1_WR_3 R 32 0x0000 008C 0x480B D28C SBL_RSZ2_WR_0 R 32 0x0000 0090 0x480B D290 SBL_RSZ2_WR_1 R 32 0x0000 0094 0x480B D294 SBL_RSZ2_WR_2 R 32 0x0000 0098 0x480B D298 SBL_RSZ2_WR_3 R 32 0x0000 009C 0x480B D29C...

Page 1477: ... RESERVED Write 0s for future compatibility Reads returns 0 R 0x00 23 16 TID Peripheral identification SBL module R 0x01 15 8 CID Class identification Camera ISP R 0xFB 7 0 PREV Peripheral revision number R TI internal data Table 6 513 Register Call Summary for Register SBL_PID Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 514 SBL_PCR Address Offset 0x0000 0004 Physical Addr...

Page 1478: ...showed up at the resizer interface In such a case resizing for this frame cannot take place and the bit is set This scenario can happen when a resize of 4x is required per frame Therefore the REISZER needs to operate in two passes In the first pass the input data from CCDC PREVIEW is directly resized and written to memory In the second pass the resized data from the first pass is resized again The...

Page 1479: ...up overflow Software has to write 1 to clear the bit Read 0x0 No overflow Read 0x1 Overflow 16 H3A_AEAWB_WBL_OVF H3A AE AWB Write buffer memory overflow RW 0 All DUs have been filled up overflow Software has to write 1 to clear the bit Read 0x0 No overflow Read 0x1 Overflow 15 3 RESERVED Write 0 s for future compatibility RW 0x0000 Reads returns 0 2 0 RESERVED Write 0 s for future compatibility RW...

Page 1480: ...RESIZER module input Read 0x6 RESIZER module output line 1 Read 0x7 RESIZER module output line 2 Read 0x8 RESIZER module output line 3 Read 0x9 RESIZER module output line 4 Read 0xA HISTOGRAM module input Read 0xB H3A module output auto focus Read 0xC H3A module output auto exposure and auto white balance Read 0xD CSI2A module output Read 0xE CSI1 CCP2B or CSI2C module output 1 DIRECTION Direction...

Page 1481: ...RESIZER module input Read 0x6 RESIZER module output line 1 Read 0x7 RESIZER module output line 2 Read 0x8 RESIZER module output line 3 Read 0x9 RESIZER module output line 4 Read 0xA HISTOGRAM module input Read 0xB H3A module output auto focus Read 0xC H3A module output auto exposure and auto white balance Read 0xD CSI2A module output Read 0xE CSI1 CCP2B or CSI2C module output 1 DIRECTION Direction...

Page 1482: ...RESIZER module input Read 0x6 RESIZER module output line 1 Read 0x7 RESIZER module output line 2 Read 0x8 RESIZER module output line 3 Read 0x9 RESIZER module output line 4 Read 0xA HISTOGRAM module input Read 0xB H3A module output auto focus Read 0xC H3A module output auto exposure and auto white balance Read 0xD CSI2A module output Read 0xE CSI1 CCP2B or CSI2C module output 1 DIRECTION Direction...

Page 1483: ...RESIZER module input Read 0x6 RESIZER module output line 1 Read 0x7 RESIZER module output line 2 Read 0x8 RESIZER module output line 3 Read 0x9 RESIZER module output line 4 Read 0xA HISTOGRAM module input Read 0xB H3A module output auto focus Read 0xC H3A module output auto exposure and auto white balance Read 0xD CSI2A module output Read 0xE CSI1 CCP2B or CSI2C module output 1 DIRECTION Direction...

Page 1484: ...RESIZER module input Read 0x6 RESIZER module output line 1 Read 0x7 RESIZER module output line 2 Read 0x8 RESIZER module output line 3 Read 0x9 RESIZER module output line 4 Read 0xA HISTOGRAM module input Read 0xB H3A module output auto focus Read 0xC H3A module output auto exposure and auto white balance Read 0xD CSI2A module output Read 0xE CSI1 CCP2B or CSI2C module output 1 DIRECTION Direction...

Page 1485: ...RESIZER module input Read 0x6 RESIZER module output line 1 Read 0x7 RESIZER module output line 2 Read 0x8 RESIZER module output line 3 Read 0x9 RESIZER module output line 4 Read 0xA HISTOGRAM module input Read 0xB H3A module output auto focus Read 0xC H3A module output auto exposure and auto white balance Read 0xD CSI2A module output Read 0xE CSI1 CCP2B or CSI2C module output 1 DIRECTION Direction...

Page 1486: ...RESIZER module input Read 0x6 RESIZER module output line 1 Read 0x7 RESIZER module output line 2 Read 0x8 RESIZER module output line 3 Read 0x9 RESIZER module output line 4 Read 0xA HISTOGRAM module input Read 0xB H3A module output auto focus Read 0xC H3A module output auto exposure and auto white balance Read 0xD CSI2A module output Read 0xE CSI1 CCP2B or CSI2C module output 1 DIRECTION Direction...

Page 1487: ...ER module input Read 0x6 RESIZER module output line 1 Read 0x7 RESIZER module output line 2 Read 0x8 RESIZER module output line 3 Read 0x9 RESIZER module output line 4 Read 0xA HISTOGRAM module input Read 0xB H3A module output auto focus Read 0xC H3A module output auto exposure and auto white balance Read 0xD CSI2A module output Read 0xE CSI1 CCP2B or CSI2C module output 1 DIRECTION Direction R 0 ...

Page 1488: ...ISP_SBL See Table 6 511 Description CCDC WRITE REQUEST 2 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read...

Page 1489: ...x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 537 Register Call Summary for Register SBL_CCDC_WR_2 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 538 SBL_CCDC_WR_3 Address Offset 0x0000 0034 Physical Address Instance ISP_SBL See Table 6 511 Description CCDC WRITE REQUEST 4 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 1490: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR VALID DATA_AVL RESERVED DATA_WAIT Bits Field Name Description Type Reset 31 RESERVED Write 0 s for future compatibility R 0 Reads returns 0 30 VALID Valid bit R 0 Read 0x0 No Read 0x1 Yes 29 DATA_WAIT Waiting for data R 0 Read 0x0 No Read 0x1 Yes 28 DATA_AVL Data available Received from source and can be read by R 0 the module Read ...

Page 1491: ...ad by R 0 the module Read 0x0 No Read 0x1 Yes 27 20 BYTE_CNT Byte count requested R 0x00 19 0 ADDR Upper 20 bits of the read address R 0x00000 Table 6 543 Register Call Summary for Register SBL_CCDC_FP_RD_1 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 544 SBL_PRV_RD_0 Address Offset 0x0000 0040 Physical Address Instance ISP_SBL See Table 6 511 Description PREVIEW READ REQUE...

Page 1492: ...GISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR VALID DATA_AVL RESERVED DATA_WAIT Bits Field Name Description Type Reset 31 RESERVED Write 0 s for future compatibility R 0 Reads returns 0 30 VALID Valid bit R 0 Read 0x0 No Read 0x1 Yes 29 DATA_WAIT Waiting for data R 0 Read 0x0 No Read 0x1 Yes 28 DATA_AVL Data available Received fro...

Page 1493: ...the module Read 0x0 No Read 0x1 Yes 27 20 BYTE_CNT Byte count requested R 0x00 19 0 ADDR Upper 20 bits of the read address R 0x00000 Table 6 549 Register Call Summary for Register SBL_PRV_RD_2 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 550 SBL_PRV_RD_3 Address Offset 0x0000 004C Physical Address Instance ISP_SBL See Table 6 511 Description PREVIEW READ REQUEST 4 REGISTER ...

Page 1494: ...scription PREVIEW WRITE REQUEST 1 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT D...

Page 1495: ...x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 555 Register Call Summary for Register SBL_PRV_WR_1 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 556 SBL_PRV_WR_2 Address Offset 0x0000 0058 Physical Address Instance ISP_SBL See Table 6 511 Description PREVIEW WRITE REQUEST 3 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ...

Page 1496: ...pe Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiting for status R 0 Read 0x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 559 Register Call Summary for Register SBL_PRV_WR_3 Camera ISP Register...

Page 1497: ...1 Address Offset 0x0000 0064 Physical Address Instance ISP_SBL See Table 6 511 Description PREVIEW DARK FRAME READ REQUEST 2 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR VALID DATA_AVL RESERVED DATA_WAIT Bits Field Name Description Type Reset 31 RESERVED Write 0 s for future compatibility R 0 Reads returns 0 30 VALID Valid bit ...

Page 1498: ...0x1 Yes 29 DATA_WAIT Waiting for data R 0 Read 0x0 No Read 0x1 Yes 28 DATA_AVL Data available Received from source and can be read by R 0 the module Read 0x0 No Read 0x1 Yes 27 20 BYTE_CNT Byte count requested R 0x00 19 0 ADDR Upper 20 bits of the read address R 0x00000 Table 6 565 Register Call Summary for Register SBL_PRV_DK_RD_2 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table...

Page 1499: ..._RD_0 Address Offset 0x0000 0070 Physical Address Instance ISP_SBL See Table 6 511 Description RESIZER READ REQUEST 1 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR VALID DATA_AVL RESERVED DATA_WAIT Bits Field Name Description Type Reset 31 RESERVED Write 0 s for future compatibility R 0 Reads returns 0 30 VALID Valid bit R 0 Rea...

Page 1500: ...0x1 Yes 29 DATA_WAIT Waiting for data R 0 Read 0x0 No Read 0x1 Yes 28 DATA_AVL Data available Received from source and can be read by R 0 the module Read 0x0 No Read 0x1 Yes 27 20 BYTE_CNT Byte count requested R 0x00 19 0 ADDR Upper 20 bits of the read address R 0x00000 Table 6 571 Register Call Summary for Register SBL_RSZ_RD_1 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 ...

Page 1501: ...D_3 Address Offset 0x0000 007C Physical Address Instance ISP_SBL See Table 6 511 Description RESIZER READ REQUEST 4 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR VALID DATA_AVL RESERVED DATA_WAIT Bits Field Name Description Type Reset 31 RESERVED Write 0 s for future compatibility R 0 Reads returns 0 30 VALID Valid bit R 0 Read ...

Page 1502: ...No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiting for status R 0 Read 0x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 577 Register Call Summary for Register SBL_RSZ1_WR_0 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 578 SBL_RSZ1_WR_1 Address Offset 0x0000 0084 Physical Address Instance ISP_SBL See Table 6 511 Description RE...

Page 1503: ...EST 3 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT Data sent to the destination ...

Page 1504: ...x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 583 Register Call Summary for Register SBL_RSZ1_WR_3 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 584 SBL_RSZ2_WR_0 Address Offset 0x0000 0090 Physical Address Instance ISP_SBL See Table 6 511 Description RESIZER LINE 2 WRITE REQUEST 1 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 1505: ...BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiting for status R 0 Read 0x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table...

Page 1506: ... Manual Camera ISP SBL Register Summary 0 Table 6 590 SBL_RSZ2_WR_3 Address Offset 0x0000 009C Physical Address Instance ISP_SBL See Table 6 511 Description RESIZER LINE 2 WRITE REQUEST 4 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s fo...

Page 1507: ... No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiting for status R 0 Read 0x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 593 Register Call Summary for Register SBL_RSZ3_WR_0 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 594 SBL_RSZ3_WR_1 Address Offset 0x0000 00A4 Physical Address Instance ISP_SBL See Table 6 511 Description R...

Page 1508: ...EST 3 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT Data sent to the destination ...

Page 1509: ...x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 599 Register Call Summary for Register SBL_RSZ3_WR_3 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 600 SBL_RSZ4_WR_0 Address Offset 0x0000 00B0 Physical Address Instance ISP_SBL See Table 6 511 Description RESIZER LINE 4 WRITE REQUEST 1 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 1510: ...BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiting for status R 0 Read 0x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table...

Page 1511: ... Manual Camera ISP SBL Register Summary 0 Table 6 606 SBL_RSZ4_WR_3 Address Offset 0x0000 00BC Physical Address Instance ISP_SBL See Table 6 511 Description RESIZER LINE 4 WRITE REQUEST 4 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s fo...

Page 1512: ...0x1 Yes 29 DATA_WAIT Waiting for data R 0 Read 0x0 No Read 0x1 Yes 28 DATA_AVL Data available Received from source and can be read by R 0 the module Read 0x0 No Read 0x1 Yes 27 20 BYTE_CNT Byte count requested R 0x00 19 0 ADDR Upper 20 bits of the read address R 0x00000 Table 6 609 Register Call Summary for Register SBL_HIST_RD_0 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6...

Page 1513: ... 00C8 Physical Address Instance ISP_SBL See Table 6 511 Description H3A AF WRITE REQUEST 1 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_REA...

Page 1514: ... Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 615 Register Call Summary for Register SBL_H3A_AF_WR_1 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 616 SBL_H3A_AEAWB_WR_0 Address Offset 0x0000 00D0 Physical Address Instance ISP_SBL See Table 6 511 Description H3A AE AWB WRITE REQUEST 1 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 1515: ... 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiting for status R 0 Read 0x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 ...

Page 1516: ...ister Manual Camera ISP SBL Register Summary 0 Table 6 622 SBL_CSIA_WR_1 Address Offset 0x0000 00DC Physical Address Instance ISP_SBL See Table 6 511 Description CSIA WRITE REQUEST 2 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for fut...

Page 1517: ... No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiting for status R 0 Read 0x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 625 Register Call Summary for Register SBL_CSIA_WR_2 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 626 SBL_CSIA_WR_3 Address Offset 0x0000 00E4 Physical Address Instance ISP_SBL See Table 6 511 Description C...

Page 1518: ... REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE_CNT ADDR RESERVED DATA_SENT DATA_READY Bits Field Name Description Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiti...

Page 1519: ...x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 631 Register Call Summary for Register SBL_CSIB_WR_1 Camera ISP Register Manual Camera ISP SBL Register Summary 0 Table 6 632 SBL_CSIB_WR_2 Address Offset 0x0000 00F0 Physical Address Instance ISP_SBL See Table 6 511 Description CSIB WRITE REQUEST 3 REGISTER Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 1520: ...tion Type Reset 31 30 RESERVED Write 0 s for future compatibility R 0x0 Reads returns 0 29 22 BYTE_CNT Current byte count R 0x00 21 DATA_READY Data ready R 0 Read 0x0 No Read 0x1 Yes 20 DATA_SENT Data sent to the destination waiting for status R 0 Read 0x0 No Read 0x1 Yes 19 0 ADDR Upper 20 bits of the write address R 0x00000 Table 6 635 Register Call Summary for Register SBL_CSIB_WR_3 Camera ISP ...

Page 1521: ...ister SBL_SDR_REQ_EXP Camera ISP Basic Programming Model Camera ISP Resizer Events and Status Checking 0 Camera ISP Central Resource SBLRegister Setup 1 Camera ISP Central Resource SBL Input From Memory 2 3 4 5 Camera ISP Register Manual Camera ISP SBL Register Summary 6 6 6 10 Camera ISP CSI2 Registers 6 6 10 1 Camera ISP CSI2 REGS1 Register Summary Table 6 638 CAMERA_ISP_CSI2_REGS1 Register Summ...

Page 1522: ...0x480B D874 x 0x480B DC00 x CSI2_CTx_CTRL2 RW 32 0x20 0x20 0x20 0x0000 0078 x 0x480B D878 x 0x480B DC00 x CSI2_CTx_DAT_OFST RW 32 0x20 0x20 0x20 0x0000 007C x 0x480B D87C x 0x480B DC00 x CSI2_CTx_DAT_PING_ADDR RW 32 0x20 0x20 0x20 0x0000 0080 x 0x480B D880 x 0x480B DC00 x CSI2_CTx_DAT_PONG_ADDR RW 32 0x20 0x20 0x20 0x0000 0084 x 0x480B D884 x 0x480B DC00 x CSI2_CTx_IRQENABLE RW 32 0x20 0x20 0x20 0...

Page 1523: ...NFIG Address Offset 0x0000 0010 Physical Address Instance See Table 6 80 See Table 6 638 Description SYSTEM CONFIGURATION REGISTER This register is the Interconnect socket system configuration register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED AUTO_IDLE SOFT_RESET MSTANDBY_MODE Bits Field Name Description Type Reset 31 14 RESERV...

Page 1524: ...on 4 5 Camera ISP Register Manual Camera ISP CSI2 REGS1 Register Summary 6 Table 6 643 CSI2_SYSSTATUS Address Offset 0x0000 0014 Physical Address Instance See Table 6 80 See Table 6 638 Description SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

Page 1525: ...RT_PACKET_IRQ Short packet reception status other than synch events RW 0 Line Start Line End Frame Start and Frame End data W1toClr type between 0x8 and x0F only shall be considered 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 12 ECC_CORRECTION_IRQ ECC has been used to do the correction of the only 1 bit RW 0 error status short pac...

Page 1526: ...DS Event is false Read 0x1 READS Event is true pending 2 CONTEXT2 Context 2 R 0 Read 0x0 READS Event is false Read 0x1 READS Event is true pending 1 CONTEXT1 Context 1 R 0 Read 0x0 READS Event is false Read 0x1 READS Event is true pending 0 CONTEXT0 Context 0 R 0 Read 0x0 READS Event is false Read 0x1 READS Event is true pending Table 6 646 Register Call Summary for Register CSI2_IRQSTATUS Camera ...

Page 1527: ...dered 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 12 ECC_CORRECTION_IRQ ECC has been used to correct the only 1 bit error short RW 0 packet only 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 11 ECC_NO_CORRECTION_IRQ ECC error short and long packets No correction of the RW 0 header because of more than 1 bit error 0x0 Event is masked 0x1 Event generates...

Page 1528: ...escription Camera ISP CSI2 ECC 14 Camera ISP CSI2 Short Packet 15 Camera ISP Basic Programming Model Camera ISP CSI2 Enable Video Picture Acquisition 16 17 Camera ISP Register Manual Camera ISP CSI2 REGS1 Register Summary 18 Table 6 649 CSI2_CTRL Address Offset 0x0000 0040 Physical Address Instance See Table 6 80 See Table 6 638 Description GLOBAL CONTROL REGISTER This register controls the CSI2 R...

Page 1529: ... in which IF_EN works RW 0 0x0 If IF_EN 0 the interface is disabled immediately 0x1 If IF_EN 1 the interface is disabled after all FEC sync code have been received for the active contexts 2 ECC_EN Enables the Error Correction Code check for the received RW 0 header short and long packets for all virtual channel ids 0x0 Disabled 0x1 Enabled 1 RESERVED Write 0s for future compatibility Read returns ...

Page 1530: ...full 32 bit values shall be written The register is used to write short packets and header of long packets Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBG Bits Field Name Description Type Reset 31 0 DBG 32 bit input value W 0x0000 0000 Table 6 652 Register Call Summary for Register CSI2_DBG_H Camera ISP Register Manual Camera ISP CSI2 REGS1 Register...

Page 1531: ...der and position of the lanes clock and data and the polarity order for the control of the PHY differential signals in addition to the control bit for the power FSM Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PWR_CMD RESERVED PWR_AUTO DATA2_POL DATA1_POL CLOCK_POL RESET_CTRL RESET_DONE PWR_STATUS DATA2_POSITION DATA1_POSITION CLOCK_POSITIO...

Page 1532: ...one pair is used as GPI for CPI mode The corresponding DATAx_POSITION bit must be set to 0x0 for the lane in GPI mode 7 DATA1_POL differential pin order of DATA lane 1 RW 0 0x0 pin order 0x1 pin order 6 4 DATA1_POSITION Position and order of the DATA lane 1 RW 0x0 The data lane 1 is always present 0x0 Not used connected 0x1 Data lane 1 is at position 1 0x2 Data lane 1 is at position 2 0x3 Data lan...

Page 1533: ...EGS1 Register Summary 19 Table 6 657 CSI2_COMPLEXIO1_IRQSTATUS Address Offset 0x0000 0054 Physical Address Instance See Table 6 80 See Table 6 638 Description INTERRUPT STATUS REGISTER All errors from the associated PHY Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ERRESC5 ERRESC4 ERRESC3 ERRESC2 ERRESC1 ERRSOTHS5 ERRSOTHS4 ERRSOTHS3 ERRSOTH...

Page 1534: ...t is reset 19 ERRCONTROL5 Control error for lane 5 RW 0 W1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 18 ERRCONTROL4 Control error for lane 4 RW 0 W1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 17 ERRCONTROL3 Control error for lane 3 RW 0 W1toClr 0x0 RE...

Page 1535: ...nc error for lane 4 RW 0 W1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 7 ERRSOTSYNCHS3 Start of transmission sync error for lane 3 RW 0 W1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 6 ERRSOTSYNCHS2 Start of transmission sync error for lane 2 RW 0 W1toC...

Page 1536: ...Camera ISP CSI2 PHYs 18 Camera ISP Register Manual Camera ISP CSI2 REGS1 Register Summary 19 Camera ISP CSI2 REGS1 Register Description 20 21 Table 6 659 CSI2_SHORT_PACKET Address Offset 0x0000 005C Physical Address Instance See Table 6 80 See Table 6 638 Description SHORT PACKET INFORMATION This register sets the 24 bit DATA_ID Short Packet Data Field when the data type is between 0x8 and x0F Typ...

Page 1537: ...re entering in ULPM RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 24 STATEULPM5 Lane 5 in Ultra Low Power Mode RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 23 STATEULPM4 Lane 4 in Ultra Low Power Mode RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 22 STATEULPM3 Lane 3 in Ultra Low Power Mode RW 0 0x0 Event is masked 0...

Page 1538: ...tes an interrupt when it occurs 8 ERRSOTSYNCHS4 Start of transmission sync error for lane 4 RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 7 ERRSOTSYNCHS3 Start of transmission sync error for lane 3 RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 6 ERRSOTSYNCHS2 Start of transmission sync error for lane 2 RW 0 0x0 Event is masked 0x1 Event generat...

Page 1539: ...ly full 32 bit values shall be written The register is used to write payload of long packets Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBG Bits Field Name Description Type Reset 31 0 DBG 32 bit input value W 0x0000 0000 Table 6 664 Register Call Summary for Register CSI2_DBG_P Camera ISP Register Manual Camera ISP CSI2 REGS1 Register Summary 0 Tab...

Page 1540: ...d by 4x 12 0 STOP_STATE_COUNTER_IO1 Stop State counter for monitoring It indicates the number RW 0x1FFF of L3 to monitor for Stop State before de asserting ForceRxMode Complex I O 1 The value is from 0 to 8191 Table 6 666 Register Call Summary for Register CSI2_TIMING Camera ISP Functional Description Camera ISP CSI2 PHYs 0 1 2 3 4 5 6 7 Camera ISP Basic Programming Model Camera ISP CSIPHY Initial...

Page 1541: ...s DPCM compressed RAW10 data After compression pixels are coded on 8 bits Data in memory is organized as regular RAW8 data 0x2 Outputs DPCM compressed RAW12 data After compression pixels are coded on 8 bits Data in memory is organized as regular RAW8 data 0x3 Outputs ALAW compressed RAW10 data After compression pixels are coded on 8 bits Data in memory is organized as regular RAW8 data 0x4 Outputs...

Page 1542: ...f each frame 5 CS_EN Enables the checksum check for the received payload RW 0 long packet only 0x0 Disabled 0x1 Enabled 4 COUNT_UNLOCK Unlock writes to the COUNT bit field W 0 Write 0x0 COUNT bit field is locked Writes have no effect Write 0x1 COUNT bit field is unlocked Writes are possible 3 PING_PONG Indicates whether the PING or PONG destination R 1 address CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DA...

Page 1543: ...ame Configuration 30 Camera ISP Register Manual Camera ISP CSI2 REGS1 Register Summary 31 Table 6 669 CSI2_CTx_CTRL2 Address Offset 0x0000 0074 x 0x20 Index x 0 to 7 Physical Address Instance See Table 6 80 See Table 6 638 Description CONTROL REGISTER Context This register controls the Context This register is shadowed modifications are taken into account after the next FSC sync code except for VI...

Page 1544: ...0x28 RAW6 0x29 RAW7 0x2A RAW8 0x2B RAW10 0x2C RAW12 0x2D RAW14 0x33 RGB666 EXP32_24 0x40 USER_DEFINED_8_BIT_DATA_TYPE_1 0x41 USER_DEFINED_8_BIT_DATA_TYPE_2 0x42 USER_DEFINED_8_BIT_DATA_TYPE_3 0x43 USER_DEFINED_8_BIT_DATA_TYPE_4 0x44 USER_DEFINED_8_BIT_DATA_TYPE_5 0x45 USER_DEFINED_8_BIT_DATA_TYPE_6 0x46 USER_DEFINED_8_BIT_DATA_TYPE_7 0x47 USER_DEFINED_8_BIT_DATA_TYPE_8 0x68 RAW6 EXP8 0x69 RAW7 EXP...

Page 1545: ...4 USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP 0x145 USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP 0x146 USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP 0x147 USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP 0x1C0 USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP 16 0x1C1 USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP 16 0x1C2 USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP 16 0x1C3 USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP 16 0x1C4 USER_D...

Page 1546: ...ATA_TYPE_5 DPCM10 VP 0x345 USER_DEFINED_8_BIT_DATA_TYPE_6 DPCM10 VP 0x346 USER_DEFINED_8_BIT_DATA_TYPE_7 DPCM10 VP 0x347 USER_DEFINED_8_BIT_DATA_TYPE_8 DPCM10 VP 0x368 RAW6 DPCM12 VP 0x369 RAW7 DPCM12 EXP16 0x36A RAW8 DPCM12 EXP16 0x3A8 RAW6 DPCM12 EXP16 0x3A9 RAW7 DPCM12 VP 0x3AA RAW8 DPCM12 VP Table 6 670 Register Call Summary for Register CSI2_CTx_CTRL2 Camera ISP Environment Camera ISP CSI2 Pi...

Page 1547: ...of the current line 4 0 RESERVED Write 0s for future compatibility Read returns 0 R 0x00 Table 6 672 Register Call Summary for Register CSI2_CTx_DAT_OFST Camera ISP Functional Description Camera ISP CSI2 Progressive Frame to Progressive Storage 0 Camera ISP Basic Programming Model Camera ISP CSI2 Enable Video Picture Acquisition 1 Camera ISP Register Manual Camera ISP CSI2 REGS1 Register Summary 2...

Page 1548: ... register is shadowed modifications are taken into account after the next FSC sync code Only full 32 bit values shall be written Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR RESERVED Bits Field Name Description Type Reset 31 5 ADDR 27 most significant bits of the 32 bit address RW 0x0000000 4 0 RESERVED Write 0s for future compatibility Read re...

Page 1549: ...0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 4 RESERVED Write 0s for future compatibility Read returns 0 R 0 3 LE_IRQ Context Line end sync code detection RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 2 LS_IRQ Context Line start sync code detection RW 0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 1 FE_IRQ Context Frame end...

Page 1550: ...Q Contexc Line number reached status RW 0 W1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 6 FRAME_NUMBER_IRQ Context Frame counter reached status RW 0 W1toClr 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 5 CS_IRQ Context Check Sum mismatch status RW 0 W1toClr 0...

Page 1551: ...ndex x 0 to 7 Physical Address Instance See Table 6 80 See Table 6 638 Description CONTROL REGISTER Context This register controls the Context This register is shadowed modifications are taken into account after the next FSC sync code Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALPHA LINE_NUMBER RESERVED Bits Field Name Description Type Reset 31 30...

Page 1552: ...ation register defines horizontal frame cropping Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HCOUNT HSKIP RESERVED RESERVED Bits Field Name Description Type Reset 31 29 RESERVED Write 0s for future compatibility Read returns 0 R 0x0 28 16 HCOUNT Pixels to output per line when the values is between 1 RW 0x0000 and 8191 Pixels HSKIP WIDTH pixels are ...

Page 1553: ... returns 0 R 0x0 12 0 VSKIP Pixel to skip vertically RW 0x0000 Valid values 0 8191 Table 6 687 Register Call Summary for Register CSI2_CTx_TRANSCODEV Camera ISP Functional Description Camera ISP CSI2 RAW Image Transcoding with DPCM and A law Compression 0 1 2 3 Camera ISP Register Manual Camera ISP CSI2 REGS2 Register Summary 4 6 6 11 Camera ISP CSIPHY Registers 6 6 11 1 Camera ISP CSIPHY Register...

Page 1554: ...term 1 15 ns Programmed value ceil 12 5 ns DDRClk period 1 Default value 4 for 400 MHz Note 20 percent clock frequency tolerance 7 0 THS_SETTLE Ths settle timing parameter in multiples of DDR clock RW 0x27 period Derived requirement from DSI_PHY spec 90 ns 6 UI 145 ns 10 UI Effective Ths settle seen on the line starting to look for sync pattern synchonizer delay timer delay LPRx delay combinatoria...

Page 1555: ...leted 27 26 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 25 CLOCK_MISS_DETECTOR_ST 1 Error in clock missing detector 0 Clock missing R 0 ATUS detector successful 24 18 TCLK_TERM Tclk term timing parameter in multiples of RW 0x00 CSI2_96M_FCLK period Requirement from DSI_PHY spec Dn Voltage 450 mV 55 ns Effective time for enabling termination synchonizer delay timer delay LPRx d...

Page 1556: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCP2_SYNC_PATTERN TRIGGER_CMD_RXTRIGESC0 TRIGGER_CMD_RXTRIGESC1 TRIGGER_CMD_RXTRIGESC2 TRIGGER_CMD_RXTRIGESC3 Bits Field Name Description Type Reset 31 30 TRIGGER_CMD_RXTRIGESC0 Mapping of Trigger escape entry command to PPI output RW 0x0 RXTRIGGERESC0 29 28 TRIGGER_CMD_RXTRIGESC1 Mapping of Trigger escape entry command t...

Page 1557: ...Public Version www ti com Camera ISP Register Manual 1557 SWPU177N December 2009 Revised November 2010 Camera Image Signal Processor Copyright 2009 2010 Texas Instruments Incorporated ...

Page 1559: ...se of the products of TI See OMAP36xx MIPI Disclaimer for details NOTE This document is strictly for wireless cellular software developers using OMAP36xx application processors which are not available for the broad market through authorized distributors Topic Page 7 1 Display Subsystem Overview 1560 7 2 Display Subsystem Environment 1565 7 3 Display Subsystem Integration 1617 7 4 Display Subsystem...

Page 1560: ...DSI protocol engine DSI PLL controller that drives a DSI PLL and high speed HS divider NTSC PAL video encoder The display controller and the DSI protocol engine are connected to the L3 and L4 interconnect the RFBI and the TV out encoder modules are connected to the L4 interconnect NOTE The DSI complex I O module and the DSI PLL controller are not connected to an L3 or L4 interconnect Specific disp...

Page 1561: ...otocol engine HS divider Data Controls Status PLL control DSS_DMA_REQ 3 0 DSI1_PLL_FCLK DSI2_PLL_FCLK vdds_dsi vdd_dsi DSI PLL vss_dsi cvideo1_out Composite Luma Chroma TV syncs camdss 001 DSI PLL controller Syncs DSS_PCLK DSS_VSYNC DSS_HSYNC DSS_ACBIAS dss_pclk dss_vsync dss_hsync dss_acbias dss_data 17 6 dss_data 23 18 L4 clock DSS_DATA 17 6 DSS_DATA 23 18 cvideo1_vfb cvideo1_rset COMP_EN Public...

Page 1562: ...e output format on 8 9 12 16 bit interface time division multiplexing TDM HDMI through external bridge Signal processing Overlay support for graphics ARGB RGBA RGB or Color Look Up Table CLUT and video1 YCbCr 4 2 2 RGB video2 YCbCr 4 2 2 or ARGB RGBA RGB Programmable video resizer independent horizontal and vertical resampling Upsampling up to x8 and downsampling down to 1 4 maximum input width of...

Page 1563: ...air Data splitter for 2 data lane configuration Error correction code ECC and check sum generation Burst support for the video mode RGB16 RGB18 packed and nonpacked and RGB24 formats supported for video mode Serial configuration port SCP for the DSI_PHY complex I O and DSI PLL Connection to the DSI_PHY complex I O through PPI Data interleaving support for one synchronous stream video mode from the...

Page 1564: ...s Programmable subcarrier frequency and SCH Internal test pattern generation color bar flat field color burst 2x 4x oversampling Supports square pixel sampling NTSC 12 27 MHz 24 54 MHz 49 09 MHz PAL 14 75 MHz 29 5 MHz 59 MHz CAUTION In square pixel mode an external clock generator is required to provide sampling frequencies TV detection gating pulse generation 1564 Display Subsystem SWPU177N Decem...

Page 1565: ...V display support 7 2 1 LCD Support LCD panels can be connected to the display subsystem of the device using parallel and or serial interfaces Table 7 1 provides more details on the supported interfaces to LCD panels and the respective pad and signal configurations 1565 SWPU177N December 2009 Revised November 2010 Display Subsystem Copyright 2009 2010 Texas Instruments Incorporated ...

Page 1566: ...bit dss_hsync Display DISPC_HSYNC RFBI_CS0 DISPC RFBI CS0 RFBI CS0 subsystem dss_vsync DISPC_VSYNC RFBI_WR RFBI RFBI dss_pclk DISPC_PCLK RFBI_RD dss_acbias DISPC_ACBIAS RFBI_A0 dss_data0 DISPC_DATA_L RFBI_DA0 DSI_DX0 DSI DSI RFBI_DA 0 5 CD0 dss_data1 DISPC_DATA_L RFBI_DA1 DSI_DY0 CD1 dss_data2 DISPC_DATA_L RFBI_DA2 DSI_DX1 CD2 dss_data3 DISPC_DATA_L RFBI_DA3 DSI_DY1 CD3 dss_data4 DISPC_DATA_L RFBI...

Page 1567: ... lanes data lanes RFBI 1 mode 16 bit dss_data13 DISPC_DATA_L RFBI_DA13 CD13 dss_data14 DISPC_DATA_L RFBI_DA14 RFBI_DA 6 15 RFBI_DA 6 15 CD14 dss_data15 Display DISPC_DATA_L RFBI_DA15 DISPC_DATA_L subsystem CD15 CD 6 17 dss_data16 DISPC_DATA_L RFBI_TE_VSYN RFBI sync0 RFBI sync0 CD16 C0 dss_data17 DISPC_DATA_L RFBI_HSYNC0 CD17 dss_data18 DISPC_DATA_L RFBI_TE_VSYN DISPC_DATA_L RFBI_DA0 DISPC_DATA_L R...

Page 1568: ...e DISPC_DATA_LCD 23 18 data is additionally multiplexed on the sys_boot device pads to allow simultaneous availability of the DSI interface and the complete parallel 24 bit DSS interface NOTE The DISPC_DATA_LCD 5 0 data multiplexed with the DSI signals on dss_data 5 0 pads is limited to up to 60 MHz pixel clock frequency If the parallel 18 24 bit interface in bypass mode with a pixel clock above 6...

Page 1569: ... GPOUT 1 0 bits control selection of the display subsystem modules see Table 7 2 Table 7 2 I O Pad Mode Selection DSS DISPC_CONTROL 16 GPOUT1 DSS DISPC_CONTROL 15 GPOUT0 Mode 0 0 Reset 0 1 RFBI mode 1 0 Invalid 1 1 Bypass mode The RFB of the LCD panel is connected directly to the RFBI module of the device The RFBI controls the reads writes from to the RFB The RFBI receives the output from the DISP...

Page 1570: ...hronization signal TE or VSYNC for LCD panel 1 RFBI_HSYNC0 I HSYNC from LCD panel 1 RFBI_TE_VSYNC1 I TE synchronization signal TE or VSYNC for LCD panel 2 RFBI_HSYNC1 I HSYNC from LCD panel 2 1 I Input O Output RFBI_DA 15 0 The pixel data comprises the RFBI pixel data bits 15 0 A write read command must be sent to the LCD panel to send read the data Before any data access the application must send...

Page 1571: ...er mode with the TE signal RFBI_TE_VSYNCx 0x2 External trigger mode with the RFBI_TE_VSYNCx and RFBI_HSYNCx signals with the programmable line counter These signals are multiplexed at the chip level boundary with dss_data 16 RFBI_TE_VSYNC0 and dss_data 18 RFBI_TE_VSYNC1 LCD panel 1 x 0 LCD panel 2 x 1 RFBI_HSYNCx The HSYNC pulse signals indicate to the RFBI module when horizontal synchronization o...

Page 1572: ...Input O Output I O Input Output DISPC_DATA_LCD 23 0 The panel pixel data comes directly from the display controller module DISPC_DATA_LCD is connected at the chip level boundary with dss_data 23 0 DISPC_PCLK This signal is the pixel clock that comes directly from the display controller This signal is multiplexed at the chip level boundary with dss_pclk DISPC_VSYNC Uses the vertical synchronization...

Page 1573: ...pixel data output pins In RFBI mode the pixel data bus is reformatted in accordance with the input and output data bus width Table 7 5 lists the number of displayed pixels per pixel clock cycle based on the type of display panel Table 7 5 Number of Displayed Pixels per Pixel Clock Cycle Based on Display Type Display Panel Number of Displayed Pixels per Pixel Clock Cycle Monochrome 4 bit 4 Monochro...

Page 1574: ...a 7 Public Version Display Subsystem Environment www ti com Figure 7 6 LCD Pixel Data Monochrome8 Passive Matrix Passive matrix technology color mode Color passive displays use 8 bit data input lines In a given pixel clock cycle each line represents one color component red green or blue Figure 7 7 shows an 8 bit color passive matrix display Figure 7 7 LCD Pixel Data Color Passive Matrix Active mat...

Page 1575: ...Pix1 G1 Pix1 G2 Pix1 G0 Pix2 G0 Pix3 G0 Pix2 G1 Pix3 G2 Pix2 G2 Pix3 G1 Pix1 G3 Pix3 G3 Pix2 G3 dss 008 dss_data 4 dss_data 5 dss_data 6 dss_data 7 dss_data 8 dss_data 9 dss_data 10 dss_data 11 dss_data 0 dss_data 1 dss_data 2 dss_data 3 Public Version www ti com Display Subsystem Environment Figure 7 8 LCD Pixel Data Color12 Active Matrix 1575 SWPU177N December 2009 Revised November 2010 Display ...

Page 1576: ...ta 14 dss_data 15 LCD controller output pins Pixel clock Pix1 B1 Pix1 B5 Pix1 B0 Pix2 B0 Pix3 B0 Pix1 R0 Pix1 R3 Pix1 R4 Pix1 R5 Pix2 B1 Pix2 R0 Pix2 R5 Pix3 B5 Pix3 R3 Pix2 B5 Pix2 R3 Pix3 R4 Pix2 R4 Pix3 B1 Pix3 R0 Pix3 R5 Pixel data 17 0 Pixel data dss 010 dss_data 0 dss_data 1 dss_data 5 dss_data 12 dss_data 15 dss_data 16 dss_data 17 Public Version Display Subsystem Environment www ti com Fig...

Page 1577: ...put by the display controller It is deasserted to indicate when new data must be outputted by the display controller Figure 7 12 RFBI Data Stall Signal Diagram To avoid underflow of the DMA FIFO the FIFO handcheck feature can be enabled by setting the DSS DISPC_CONFIG 16 FIFOHANDCHECK bit to 1 The fullness of the FIFOs associated with the pipelines used for the LCD output is checked when the STALL...

Page 1578: ...i 9 4 CS deassertion time from start access time CSOFFTIME with I 0 or 1 WeCycleTime DSS RFBI_CYCLE_TIMEi 5 0 The time when A0 becomes valid until write cycle WECYCLETIME with I 0 or 1 completion WEOnTime DSS_RFBI_ONOFF_TIMEi 13 10 WE assertion delay time from start access time WEONTIME with I 0 or 1 WEOffTime DSS_RFBI_ONOFF_TIMEi 19 14 WE deassertion delay time from start access time WEOFFTIME wi...

Page 1579: ...ck in bypass mode for both passive matrix and active matrix panels The display controller directly drives these signals which are related to the programmable fields described in Table 7 7 Table 7 7 Programmable Fields in Bypass Mode Name Register Description PPL DSS DISPC_SIZE_LCD 10 0 PPL bit field value 1 Pixels per line PPL LPP DSS DISPC_SIZE_LCD 26 16 LPP bit field value 1 Lines per panel HBP ...

Page 1580: ...IAS IPC DSS DISPC_POL_FREQ 14 IPC bit Invert DISPC_PCLK IHS DSS DISPC_POL_FREQ 13 IHS bit Invert DISPC_HSYNC IVS DSS DISPC_POL_FREQ 12 IVS bit Invert DISPC_VSYNC Active matrix timing configuration 1 DSS DISPC_POL_FREQ 17 ONOFF bit 0 DSS DISPC_POL_FREQ 16 RF bit 0 The DISPC_HSYNC and DISPC_VSYNC signals are driven on the opposite edge of DISPC_PCLK from the pixel data DSS DISPC_POL_FREQ 15 IEO 0 Th...

Page 1581: ...g Diagram of Configuration 1 End of Frame Active matrix timing configuration 2 DSS DISPC_POL_FREQ 17 ONOFF bit 1 DSS DISPC_POL_FREQ 16 RF bit 1 The DISPC_HSYNC and DISPC_VSYNC signals are driven on the rising edge of DISPC_PCLK DSS DISPC_POL_FREQ 15 IEO 1 The DISPC_ACBIAS signal is active low DSS DISPC_POL_FREQ 14 IPC 1 The pixel data is driven on the falling edge of DISPC_PCLK DSS DISPC_POL_FREQ ...

Page 1582: ... 23 Active Matrix Timing Diagram of Configuration 2 Between Frames Figure 7 24 Active Matrix Timing Diagram of Configuration 2 End of Frame Active matrix timing configuration 3 DSS DISPC_POL_FREQ 17 ONOFF bit 1 DSS DISPC_POL_FREQ 16 RF bit 1 The DISPC_HSYNC and DISPC_VSYNC signals are driven on the rising edge of DISPC_PCLK DSS DISPC_POL_FREQ 15 IEO 0 The DISPC_ACBIAS signal is active high DSS DIS...

Page 1583: ...system Environment Figure 7 25 Active Matrix Timing Diagram of Configuration 3 Start of Frame Figure 7 26 Active Matrix Timing Diagram of Configuration 3 Between Lines Figure 7 27 Active Matrix Timing Diagram of Configuration 3 Between Frames Figure 7 28 Active Matrix Timing Diagram of Configuration 3 End of Frame Passive matrix timing configuration DSS DISPC_POL_FREQ 17 ONOFF bit 0 DSS DISPC_POL_...

Page 1584: ...BIAS signal is active high DSS DISPC_POL_FREQ 14 IPC 0 The pixel data are driven on the rising edge of DISPC_PCLK DSS DISPC_POL_FREQ 13 IHS 0 The DISPC_HSYNC signal is active high DSS DISPC_POL_FREQ 12 IVS 0 The DISPC_VSYNC signal is active high Figure 7 29 Passive Matrix Timing Diagram Start of Frame Figure 7 30 Passive Matrix Timing Diagram Between Lines Figure 7 31 Passive Matrix Timing Diagram...

Page 1585: ...tiplexing 7 2 2 LCD Support With MIPI DSI 1 0 Protocol and Data Format This section summarizes the MIPI DSI1 0 protocol and data format NOTE Copyright 2005 2008 MIPI Alliance Inc All rights reserved MIPI Alliance Member Confidential 7 2 2 1 Physical Layer Table 7 8 lists the DSI interface I O Table 7 8 I O Description for DSI Serial Interface Signal Name I O 1 Description Value at Reset dsi_dx0 li...

Page 1586: ...in the host sends the data in quadrature with the DDR clock in high speed mode otherwise the clock is extracted from the received data in low speed mode The data is transmitted byte wise least significant bit LSB first The clock signal carries the DDR clock signal in high speed transmission Software users must configure the order of the data lanes to indicate the byte order while splitting the byt...

Page 1587: ...power state ULPS by software configuration The ULPS mode requires all the following conditions The lane must be in stop state For data lanes no data must be pending in the DSI module For data lane 1 no BTA should have been sent The DSI module should have control of the bus The control of each lane is independently controlled by the DSS DSI_COMPLEXIO_CFG2 register 7 2 2 2 Video Port VP Interface NO...

Page 1588: ...S DSI_CTRL 13 12 LINE_BUFFER bit field defines the number of lines to be used for transferring data from the video port to the DSI link 7 2 2 2 1 Video Port Used for Video Mode If the video port is used for video mode the VP_STALL is not used Table 7 11 lists the active signals on the video port Table 7 11 Video Interface in the Context of Video Mode Signal Name Type 1 Description VP_HSYNC I Horiz...

Page 1589: ...he display controller to flush the line buffers The synchronization packets are never stored into the line buffer NOTE If more active lines are received on the video port than the number defined in the DSS DSI_VM_TIMING3 15 0 VACT bit field the extra lines are discarded by the DSI protocol engine These lines are treated as blanking lines Figure 7 34 Figure 7 35 and Figure 7 36 show these three vid...

Page 1590: ...HFP HSW HSW HBP PCLK VSYNC HSYNC DE DATA 23 0 PIXELS PIXELS HSW HFP VFP VSW HBP HSW VBP PCLK VSYNC HSYNC DE DATA 23 0 PIXELS HBP HSW HSW HSW VFP Not used for the first frame PIXELS PIXELS DSI waveform VP waveforms dss 136 Active matrix timing Between frames Active matrix timing End of the frame last one tL VSA VBP VACT VFP tL tL tL tL tL tL tL Public Version Display Subsystem Environment www ti co...

Page 1591: ...VSYNC HSYNC DE DATA 23 0 PIXELS HSW VSW VBP HBP PCLK VSYNC HSYNC DE DATA 23 0 HBP HFP HSW HSW HBP PCLK VSYNC HSYNC DE DATA 23 0 PIXELS PIXELS PIXELS HSW HFP VFP VSW HBP HSW VBP PCLK VSYNC HSYNC DE DATA 23 0 PIXELS HBP HSW HSW HSW VFP Not used for the first frame Buffer Extended HBP due to buffering HBP Reduced HFP due to buffering HBP PIXELS PIXELS VP waveforms DSI waveform dss 137 Public Version ...

Page 1592: ... PCLK VSYNC HSYNC DE DATA 23 0 PIXELS HSW VSW VBP HBP PCLK VSYNC HSYNC DE DATA 23 0 HBP HFP HSW HSW HBP PCLK VSYNC HSYNC DE DATA 23 0 PIXELS PIXELS HSW HFP VFP VSW HBP HSW VBP PCLK VSYNC HSYNC DE DATA 23 0 PIXELS HBP HSW HSW HSW VFP Not used for the first frame Buffer 1 Buffer 2 Dummy line not stored in the buffer PIXELS PIXELS tL tL tL tL tL VP waveforms DSI waveform dss 138 Public Version Displa...

Page 1593: ...ings internal and received are out of sync the interrupt for out of sync must be generated and the interface must be disabled DSS DSI_CTRL 0 IF_EN bit is automatically reset by hardware The unsynchronization window is defined by the DSS DSI_VM_TIMING2 27 24 WINDOW_SYNC bit field 7 2 2 2 2 Video Port Used on Command Mode If the video port is used for command mode the VP_HSYNC VP_VSYNC and VP_DE sig...

Page 1594: ...R 7 0 PCD bit field In the DSI protocol engine the information is defined in the DSS DSI_CTRL 4 VP_CLK_RATIO bit and must be aligned with the display controller configuration Deassertion of the VP_STALL signal must occur at least 4 VP_CLK cycles before assertion of VP_PCLK Assertion of VP_STALL must occur one cycle VP_CLK after deassertion of VP_PCLK for the last pixel to be transferred The VP_CLK...

Page 1595: ...dware automatically inserts the DCS Write Start command for the first packet of the frame transfer and the DCS Write Continue command for all subsequent packets 7 2 2 2 3 Burst Mode When the burst mode is enabled the video port receives data from the display controller at the pixel clock The DSI protocol engine buffers the data in its own line FIFO double line buffer of 1024 x 24 bit pixels maximu...

Page 1596: ...d EoT in Multilane Configurations Since a HS transmission is composed of an arbitrary number of bytes that may not be an integer multiple of the number of lanes some lanes may run out of data before others Therefore the lane management layer as it buffers up the final set of less than N bytes deasserts its valid data signal into all lanes for which there is no further data Although all lanes start...

Page 1597: ...SI protocol layer defines how the display data is transported onto the physical layer Packets can be sent using high speed or low speed mode LLP is selected through DSI registers The features of the DSI protocol layer are Transport of arbitrary data payload independent 8 bit word size Support for up to four interleaved VCs on the same link Special packets for frame start frame end line start and l...

Page 1598: ...acket footer must be included in the word count The ECC byte allows single bit errors to be corrected and 2 bit errors to be detected in the packet header This includes the data identifier and the word count fields After the end of the packet header the receiver reads the next word count bytes of the data payload There are no limitations on the value of a data word within the data payload block th...

Page 1599: ...VC assignment and can be directed to different peripherals The VC ID is defined in the DSS DSI_VCn_SHORT_PACKET_HEADER and DSS DSI_VCn_LONG_PACKET_HEADER registers for short and long packets respectively It should not be modified by hardware There is one set of registers for each VC Each set of registers defines the characteristics of the traffic between the host and the display associated with th...

Page 1600: ...t if the generation is enabled When the transition from active to inactive state is detected the VSEC short packet is generated if the generation is enabled replacing the HSSC synchronization packet corresponding to the following HSYNC When the DSI protocol engine detects that the HSYNC signal from the display controller transition from inactive to active state the HSSC short packet is generated i...

Page 1601: ...sing the blanking values formerly defined the packets short and long are considered in HS mode Timing parameters VSA VBP VFP HSA HBP HFP VACT and tL are defined in the DSS DSI_VM_TIMINGx x between 1 and 7 register HSA HBP HFP and tL are defined using the byte clock unit TxByteClkHS and also in low power clock cycles TxClkEsc VSA VBP VFP and VACT are defined in term of number of lines When the HS b...

Page 1602: ...more data from the TX FIFO to send in LP mode or the trigger has been sent the lane is put into LPS If the lanes must be kept in HS mode during blanking periods except for the last blanking period of the frame the HS blanking packets must be used In case one trigger is sent at the beginning of the blanking period the rest of the blanking period is in ULPS Figure 7 48 and Figure 7 49 show a nonburs...

Page 1603: ...lines H S B L L P tL tL tL tL tL tL tL tL tL dss 149 Public Version www ti com Display Subsystem Environment Figure 7 49 DSI Video Mode Nonburst Transfer Without VE and HE NOTE HSA timing is not used and does not have to be programmed when HE short packet is not generated 1603 SWPU177N December 2009 Revised November 2010 Display Subsystem Copyright 2009 2010 Texas Instruments Incorporated ...

Page 1604: ...ronment www ti com Figure 7 50 DSI Video Mode Burst Transfer Without VE and HE NOTE HSA timing is not used and does not have to be programmed when HE short packet is not generated In Figure 7 49 and Figure 7 50 if HSync end short packet is not generated HSA does not exist HBP must be other than 0 7 2 2 4 9 Frame Structures Figure 7 51 shows the general DSI frame structure 1604 Display Subsystem SW...

Page 1605: ...nking Line blanking FS FE Frame of pixels Video mode Packet footer PF Packet header PH Packet footer PF Packet header PH dss 151 Public Version www ti com Display Subsystem Environment Figure 7 51 DSI General Frame Structure Figure 7 52 shows the general frame structure using burst mode 1605 SWPU177N December 2009 Revised November 2010 Display Subsystem Copyright 2009 2010 Texas Instruments Incorp...

Page 1606: ...ng FS FE Frame of pixels Video mode Packet footer PF Packet header PH Packet footer PF Packet header PH dss 152 Public Version Display Subsystem Environment www ti com Figure 7 52 DSI General Frame Structure Using Burst Mode Figure 7 53 shows the general frame structure using burst mode and interleaving 1606 Display Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas I...

Page 1607: ...of pixels Panel 2 Frame of pixels Panel 2 FS FE Video mode Command mode Packet header PH Packet footer PF Packet footer PF Packet header PH Packet header PH Packet footer PF Packet footer PF Packet header PH dss 153 Public Version www ti com Display Subsystem Environment Figure 7 53 DSi General Frame Structure Using Burst Mode and Interleaving 1607 SWPU177N December 2009 Revised November 2010 Disp...

Page 1608: ...al channel 3 0x3 In the case of multiple displays connected to the single DSI port on the host a hub may be used to root the data stream to the appropriate display based on the VC ID Typically VC ID 0x0 is used for the primary display and 0x1 for the secondary The hub may have its own VC ID to provide communication capability between the host and the hub 7 2 2 5 Pixel Data Formats This section sum...

Page 1609: ...ystem Environment Figure 7 54 24 Bits per Pixel RGB Color Format Long Packet Packed pixel stream 24 bit format is a long packet used to transmit image data formatted as 24 bit pixels to a video mode display module The packet consists of the DI byte a two byte WC an ECC byte a payload of length WC bytes and a two byte checksum The pixel format is red 8 bits green 8 bits and blue 8 bits in that orde...

Page 1610: ...r bits of the byte such that the valid pixel bits occupy bits 7 2 of each byte Bits 1 0 of each payload byte representing active pixels are ignored As a result each pixel requires three bytes as it is transmitted across the link This requires more bandwidth than the packed format but requires less shifting and multiplexing logic in the packing and unpacking functions on each end of the link This f...

Page 1611: ...ay Subsystem Environment Figure 7 56 18 Bits per Pixel Packed RGB Color Format Long Packet Packed pixel stream 18 bit format packed is a long packet It is used to transmit RGB image data formatted as pixels to a video mode display module that displays 18 bit pixels The packet consists of the DI byte a two byte WC an ECC byte a payload of length WC bytes and a two byte checksum Pixel format is red ...

Page 1612: ... following modules Display controller Video encoder Video DAC stage comprising two single 10 bit DACs AVDAC1 and AVDAC2 with video amplifiers The display controller module receives synchronization signals from the video encoder and synchronously sends pixel data to the video encoder with these signals The digital output of the display controller is always a 24 bit RGB value based on a pixel reques...

Page 1613: ...AC1 amplifier Composite input vssa_dac vdda_dac Power IC dss 191 NC NC cvideo2_out cvideo2_vfb Public Version www ti com Display Subsystem Environment Figure 7 58 TV Display Interface S video mode DC coupled High FS Swing Figure 7 59 is a block diagram of the TV display interface Composite mode DC coupled High Full Scale Swing Figure 7 59 TV Display Interface Composite Mode DC coupled High FS Swin...

Page 1614: ...ut2 loads can be integrated in the amplifier and thus not needed as external components Public Version Display Subsystem Environment www ti com Figure 7 60 TV Display Interface Composite Mode AC coupled Low FS Swing NOTE In composite video mode the video DAC2 chroma output must be disabled by setting the DSS VENC_OUTPUT_CONTROL 2 CHROMA_ENABLE bit to 0 Figure 7 61 is a block diagram of the TV disp...

Page 1615: ...deo2_out cvideo1_rset I O External resistor pin to set the reference current of the AVDAC1 The value of the resistor Rset depends on the mode of operation Refer to Table 7 18 Typical values for Rout Rset and Cout vdda_dac Power Analog supply voltage for the video DAC stage vssa_dac Power Analog ground for the video DAC stage 1 O Output Power Power pin Table 7 18 lists the typical values for the Ro...

Page 1616: ...pins must have a characteristic impedance of 75 Ω starting from the closest possible place to the device pin output If the TV output is not used the following configurations for the AVDACs pins must be applied Configuration 1 cvideo1_out must be grounded cvideo1_vfb must be grounded cvideo2_out must be grounded cvideo2_vfb must be grounded cvideo1_rset must be grounded vdda_dac must be grounded vs...

Page 1617: ...ling Suitable for low power consumer video applications Power down mode with less than 12 µA standby current Differential gain error and differential phase error within 3 percent and 1 degree respectively NOTE To enhance the TV color display it is highly recommended to set the DSS DSS_CONTROL 4 DAC_DEMEN bit For more information about the video DAC stage architecture and configuration see Section ...

Page 1618: ...s Syncs Status PLL control DSS_DMA_REQ 3 0 DSI1_PLL_FCLK DSI2_PLL_FCLK DSI PLL PRCM STANDBY WAIT handshake M_IRQ_25 IVA2_IRQ 13 S_DMA_5 S_DMA_ 71 74 camdss 036 L4 interconnect DSS_L3_ICLK DSS_L4_ICLK DSS1_ALWON_FCLK DSS2_ALWON_FCLK DSS_TV_FCLK DSS_L3_ICLK DSS_L4_ICLK DSS1_ALWON_FCLK DSS2_ALWON_FCLK DSS_TV_FCLK CONTROL_DEVCONF1 11 CONTROL_DEVCONF1 18 COMP_EN CONTROL_AVDACx 20 16 Public Version Disp...

Page 1619: ...mdss 158 Public Version www ti com Display Subsystem Integration 7 3 1 Clocking Reset and Power Management Scheme 7 3 1 1 Clocks The power reset and clock management PRCM module provides six clock signals to the display subsystem The L3 interface clock DSS_L3_ICLK and the L4 interface clock DSS_L4_ICLK with frequencies equal to the L3 interconnect clock and the L4 interconnect clock respectively t...

Page 1620: ...p to 100 MHz at low voltage OPP50 DSS_TV_FCLK Functional clock DSS video mode 54 MHz or From PRCM DPLL4 source DAC DPLL4_ALWON_FCLK or sys_alt_clk up to 59 External input clock See Chapter 3 MHz Power Reset and Clock Management To enable or disable each functional clock set the following bit 1 Enable 0 Disable PRCM CM_FCLKEN_DSS 0 EN_DSS1 bit to enable DSS1_ALWON_FCLK PRCM CM_FCLKEN_DSS 1 EN_DSS2 ...

Page 1621: ...OTE It is possible to switch between these two clocks even when both of them are not active There are five clock domains in the DSI module Byte clock domain TxByteClkHS is generated from the bit clock and converted into a byte clock The maximum frequency is 112 5 MHz at nominal voltage OPP100 and 100 MHz at low voltage OPP50 It is generated by the DSI complex I O Functional clock domain The DSI_FC...

Page 1622: ...epending on the DPLL4 input clock frequency by setting the PRCM CM_CLKSEL_DSS 12 8 CLKSEL_TV bit field If the DPLL4 is selected the DSS_TV_FCLK is provided by the DPLL4_ALWON_FCLKOUTM3X2 clock NOTE If the DSS_TV_FCLK is not provided by DPLL4 but rather by the sys_alt_clk pin an external clock generator must be connected to this pin In this case a 54 MHz clock is needed for PAL or NTSC 601 a 49 09 ...

Page 1623: ... are maintained during the wake up period DSS DISPC_SYSCONFIG 9 8 CLOCKACTIVITY bit field set to 0x3 The interface and functional clocks are maintained during the wake up period The DSI protocol engine clocks can be configured in one of the following clock activity modes DSS DSI_SYSCONFIG 9 8 CLOCKACTIVITY bit field set to 0x0 reset value The interface and functional clocks can be switched off DSS...

Page 1624: ...ISPC_SYSCONFIG 4 3 SIDLEMODE bit field to 0x1 for display controller set the DSS DSI_SYSCONFIG 4 3 SIDLEMODE bit field to 0x1 for DSI protocol engine and finally the DSS RFBI_SYSCONFIG 4 3 SIDLEMODE bit field to 0x1 for RFBI Smart idle mode Display controller After receiving a low power mode request from the PRCM module the display controller module enters the idle state when all the following con...

Page 1625: ... following events occur Graphics pipe is disabled or graphics pipe is enabled but data fetch completed for graphics window or graphics pipe is enabled and data fetch is not completed and number of data bytes in FIFO is greater than the high threshold programmed value Video1 pipe is disabled or video1 pipe is enabled but data fetch completed for video1 window or video1 pipe is enabled and data fetc...

Page 1626: ...t is set to 0 and the display subsystem is in standby mode DSS2_ALWON_FCLK is shut down when the PRCM CM_FCLKEN_DSS 1 EN_DSS2 bit is set to 0 and the display subsystem is in standby mode DSS_L3_ICLK and DSS_L4_ICLK are controlled together They are shut down when the PRCM CM_ICLKEN_DSS 0 EN_DSS bit is set to 0 and the display subsystem is in standby mode CAUTION Do not stop DSS1_ALWON_FCLK or DSS2_...

Page 1627: ...e DSS_TV_FCLK if the video encoder is used Set the PRCM CM_CLKSTCTRL_DSS 1 0 CLKTRCTRL_DSS bit field to 0x3 autocontrol mode supervised by hardware Shut down the display subsystem Disable the display subsystem Manually disable DSS1_ALWON_FCLK DSS2_ALWON_FCLK DSS_TV_FCLK DSS_L3_ICLK and DSS_L4_ICLK For more details on low power programming settings see Section 7 6 2 1627 SWPU177N December 2009 Revi...

Page 1628: ...Q and the DSI protocol engine DSI_DMA_REQ3 are merged on line DSS_DMA3 The software must only use DSS_DMA3 on one module at a time RFBI or DSI protocol engine 7 3 2 1 1 Display Controller DMA Request Line Trigger One DMA synchronization line DSS_LINE_TRIGGER is connected to the sDMA by the sDMA controller S_DMA_5 input line This DMA request is not a classical one but a synchronization signal from ...

Page 1629: ...from the DSI RX FIFO to the system memory and from the system memory to the DSI TX FIFO Two independent DMA requests for RX FIFO and TX FIFO for the same VC are supported 7 3 2 1 3 RFBI DMA Request The RFBI_DMA_REQ is used to receive data into the RFBI FIFO The DMA request is always generated when there is enough room in the FIFO to accept the full burst 7 3 2 2 Interrupt Requests The DSI protocol...

Page 1630: ...ubsystem interrupt events Table 7 22 Display Subsystem Interrupts Interrupt Name Description FRAMEDONE Active frame is complete and LCD output is disabled VSYNC VSYNC interrupt occurred at the end of the frame EVSYNC_EVEN 1 EVSYNC_EVEN interrupt occurred at the end of the frame EVSYNC is received and the field polarity is even EVSYNC_ODD 1 EVSYNC_ODD interrupt occurred at the end of the frame EVSY...

Page 1631: ...again NOTE The SYNCLOSTDIGITAL interrupts which occur before the first VSYNC pulse signal from the video encoder must not be considered After the first VSYNC pulse signal the SYNCLOSTDIGITAL interrupt status bit must be cleared by writing 1 in the DSS DISPC_IRQSTATUS 15 SYNCLOSTDIGITAL bit then the SYNCLOSTDIGITAL interrupt can be enabled by setting the DSS DISPC_IRQENABLE 15 SYNCLOSTDIGITAL bit 7...

Page 1632: ...LE Table 7 24 indicates the DSI complex I O interrupt events Table 7 24 DSI Complex I O Interrupts Interrupt Name Description ULPSActiveNot_ALL0_IRQ All signals ULPSActiveNOT are 0 ULPSActiveNot_ALL1_IRQ All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high STATEULPS3_IRQ Lane 3 in ultralow power state STATEULPS2_IRQ Lane 2 in ultralow power state STATEULPS1_...

Page 1633: ...O overflow The FIFO used on the L4 interconnect slave port for buffering the data received on the L4 interconnect slave port has overflowed BTA_IRQ Bus turnaround is received from the peripheral the VC ID used for the last BTA request transfer to the peripheral is used to determine which VC is used to flag the interrupt ECC_NO_CORRECTION_IRQ ECC error short and long packets No correction of the he...

Page 1634: ... Functional Description This section describes the functions of the LCD and TV display supports by describing the following modules display controller DSI protocol engine DSI PLL controller DSI complex I O RFBI and video encoder The functions of the display controller are common to both LCD and TV data paths the RFBI are LCD specific and the video encoder functions are specific to the TV set 7 4 1...

Page 1635: ...g Color space conversion 1 0 Extend 24 Color phase rotation matrix 24 dss 038 OCP slave port OCP master port arbitrator YUV2RGB Re sampling Video2 path Up down sampling Color space conversion 24 1 0 1 0 Extend 24 16 Public Version www ti com Display Subsystem Functional Description Figure 7 68 Display Controller Architecture Overview Several processes can be configured to manage the graphics pipel...

Page 1636: ...olors depends on the color depth 24 BPP supports 16 777 216 colors 18 BPP supports 262 144 colors 16 BPP supports 65 536 colors 12 BPP supports 4096 colors 7 4 2 1 2 Digital Output The digital output is always a 24 bit RGB value based on an external pixel request 7 4 2 2 Graphics Pipeline The graphics pipeline is connected to the graphics FIFO controller for the input port and to the two overlay m...

Page 1637: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 3 Pixel 2 Pixel 0 Pixel 1 dss T045 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 dss T066 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R0 G0 Unused R1 G1 B1 B0 Unused dss T046 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 1638: ...i com ARGB 16 BPP data memory organization little endian ARGB 16 BPP data memory organization big endian RGB 24 BPP data memory organization little or big endian ARGB 32 BPP data memory organization little or big endian RGBA 32 BPP data memory organization little or big endian RGB 24 BPP packet data memory organization little or big endian 7 4 2 2 2 Color Look Up Table Gamma Table The graphics pat...

Page 1639: ...ree 8 bit fields one for each color component red green and blue For color operation an individual frame is limited to a selection of 256 colors the number of palette entries The format of one of the palette values in the memory is as follows 24 BPP Data Memory Organization Little Endian or Nibble 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused R G B In...

Page 1640: ... replication logic increases the color depth of the graphics and video encoded pixels from true color RGB 12 and 16 BPP to 24 BPP The encoded value is shifted to the 24 bit alignment The MSB bits are copied to the LSB missing ones Then the graphics are merged with the video data based on the transparency color keys When the replication logic is not selected the encoded pixel values are shifted to ...

Page 1641: ... 4 3 2 1 0 A R G B dss T052 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y1 Cr0 Y0 Cb0 dss T058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cb0 Y0 Cr0 Y1 dss T071 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cr0 Y1 Cb0 Y0 dss T059 Public Version www ti com Display Subsystem F...

Page 1642: ...2 2 to YCbCr 4 4 4 90 or 270 Degree Rotation The interpolation of the missing chrominance component is given by the equation in Figure 7 72 Figure 7 72 Interpolation of the Missing Chrominance Component First to convert the YCbCr 4 2 2 encoded pixel values into YCbCr 4 4 4 format the missing chrominance samples Cb and Cr are interpolated using the average values of the two closest values on the sa...

Page 1643: ...e YUV4 2 2 to YUV4 4 4 processing is bypassed in the color space conversion unit If the active range for the luminance samples Y is 16 235 and 16 240 for the chrominance samples Cb and Cr the values of R G and B output components are clipped to the range 0 255 The equation shown in Figure 7 73 gives the 11 bit coefficients of the YCbCr to RGB color space conversion Figure 7 73 YCbCr to RGB Registe...

Page 1644: ...nt cursor When the alpha blender is enabled the graphics layer is on top of the video layers The cursor uses the graphics layer The pixel alpha blending or the transparency color key can be used 7 4 2 3 4 Up Down Sampling The video layer has a dedicated resizing block to upsample and downsample the video encoded pixels The supported input formats from memory are RGB24 RGB16 and YUV4 2 2 RGB12 and ...

Page 1645: ...CALTAPS 1 DISPC_VIDn_PICTURE_SIZE 10 0 VIDORGSIZEX 4 and even Figure 7 76 shows an example of video upsampling Figure 7 76 Video Upsampling Filter Description The up downsampling filter is a poly phase filter with five taps and eight phases for the horizontal filter and a programmable number of taps three or five and eight phases for vertical filter The upsampling ratio is up to x8 The downsamplin...

Page 1646: ...isplay Subsystem Functional Description www ti com Figure 7 77 Resampling Macro Architecture 3 Coefficient Processing To determine if the minimum functional clock matches the down sampling ratio and the desired Pixel clock the following formula must be used in conjunction with Table 7 26 and Table 7 27 Ratio V when performing a vertical down sampling only NOTE For frequency ratio calculation on th...

Page 1647: ...4 25 MHz with a DSS functional clock of 133 MHz In this example a H V down sampling is done on the input picture Firstly the Ratio V and H are determined and the resulting maximum value is taken to calculate the functional clock frequency required Ratio V h_ratio 1 6 and v_ratio 1 28 then Ratio 0 4 Ratio H Ratio 1 28 Ratio H V Ratio max 1 28 0 4 1 28 In this use case the horizontal and vertical do...

Page 1648: ...ering and Passive Matrix units and back to the palette unit in the case of Gamma correction 7 4 2 4 1 Priority Rule The overlay manager can be configured in two distinct modes Alpha mode only source color key with the graphics layer Normal mode no alpha support The following rules apply in normal mode The video1 layer is always on top of the graphics layer The video2 layer is always on top of the ...

Page 1649: ...ttributes in Normal Mode The following rules apply in alpha mode The video2 layer is always on top of the video1 layer The graphics layer is always on top of the video1 and video2 The display controller reads the data for each buffer from the system memory and depending on the transparency color key values displays either the pixels in the video layer the pixels in the graphics layer or the solid ...

Page 1650: ...ent pixel increment rotation Display Video1 window width Gfx window width Display width 0 0 x y Additional display attributes type STN TFT mono color depth x y video1 graphics background layers view Video1 video2 Video2 window width Graphics transparency color key Video2 background color timings window height Video2 dss 164 Display height Video1 window height Gfx window height Public Version Displ...

Page 1651: ...lay Subsystem Functional Description Figure 7 82 Alpha Blending Macro Architecture with Pre multiplied Alpha Support NOTE 1 alpha operator corresponds to the basic 1 s complement operation The pre multiplied alpha option is accessible through DSS DISPC_GFX_ATTRIBUTES 28 PREMULTIPLYALPHA and DSS DISPC_VIDn_ATTRIBUTES 28 PREMULTIPLYALPHA registers bits The following settings are available 1651 SWPU1...

Page 1652: ...the graphics destination transparency color key The encoded pixel color value is compared to the transparency color key For CLUT bitmaps the palette index is compared to the transparency color key and not to the palette value pointed out by the palette index NOTE The video source transparency color key and graphics destination transparency color key cannot be active at the same time Video source t...

Page 1653: ... the graphics region when graphics and video overlap otherwise the destination transparency color key is ignored To enable the graphics destination transparency color key set to 0x0 the DSS DISPC_CONFIG 11 TCKLCDSELECTION bit for LCD output or the DSS DISPC_CONFIG 13 TCKDIGSELECTION bit for digital output Program the DSS DISPC_CONFIG 10 TCKLCDENABLE bit LCD output or the DSS DISPC_CONFIG 12 TCKDIG...

Page 1654: ... be configured to take advantage of the fact that the graphics pixels under video window 1 are not visible when the transparency color key is not used The optimization can be selected to reduce the bandwidth used to fetch the pixels for graphics The color key must be disabled The graphics pixels under the video window 1 are not fetched from system memory At least the video window 1 and the graphic...

Page 1655: ...icients The output of the calculation is clipped to 0 255 The color phase rotation is processed by the equation shown in Figure 7 85 Figure 7 85 Color Phase Rotation Matrix Figure 7 86 shows the color phase rotation macro architecture Figure 7 86 Color Phase Rotation Macro Architecture 7 4 2 5 1 1 Spatial Temporal Dithering The spatial temporal dithering logic can be selected for passive matrix an...

Page 1656: ...es the visual perception of color gray graduations Active matrix technology The passive matrix dithering logic is always bypassed in active displays NOTE If the interface data bus is smaller than the pixel format size dithering logic can be enabled If the interface data bus is wider than the pixel format size the dithering logic cannot be enabled and replication feature can be used 7 4 2 5 3 Passi...

Page 1657: ...terrupt is a level signal and stays active during the programmed line of the display 7 4 2 8 Rotation In case of SDRAM buffer the display controller accesses the encoded pixels in burst always considering the consecutive data in memory The rotation engine VRFB in the SDRAM scheduler SDRC is in charge of translating the addresses from virtual to physical SDRAM addresses see Chapter 10 Memory Subsys...

Page 1658: ...ht 2005 2008 MIPI Alliance Inc All rights reserved MIPI Alliance Member Confidential The DSI protocol engine integrates DSI interface to the display through the DSI DSI_PHY module L4 interconnect interface and video interface from the display controller The DSI DSI_PHY or complex I O module is detailed in Section 7 4 5 The DSI transmitter protocol engine PHY port can be connected to multiple displ...

Page 1659: ...ock or Data The DSI complex I O receives the configuration for pin order and the differential in a pair from the settings in DSS DSI_COMPLEXIO_CFG1 register The DSI serial interface is a bidirectional differential serial interface with data clock for the physical layer configured in unidirectional link in case the display module is only unidirectional The maximum DSI data transfer capacity is 900 ...

Page 1660: ...for displays that require continuous clock It is software programmed through the DSS DSI_CLK_CTRL 13 DDR_CLK_ALWAYS_ON bit This bit can be programmed only when the interface is disabled that is DSS DSI_CTRL 0 IF_EN bit set to 0 The peripheral can use two different kinds of clocks The first one is the DDR clock provided on the clock lane The second clock is some transitions on the data lane 1 even ...

Page 1661: ... 16 REG_TLPXBY2 bit field REG_TLPXBY2 is half of the TLPX Time to drive the CLK lane to LP 00 state to prepare DSI_PHY_REGISTER2 7 0 TCLK PREPARE for HS clock transmission REG_TCLKPREPARE Time to drive the CLK lane to HS 0 state before DSI_PHY_REGISTER1 7 0 TCLK ZERO starting the clock REG_TCLKZERO Time that the HS clock must be driven before any associated data lane begins the transition from LP ...

Page 1662: ...to HS mode It is critical that ENTER_HS_MODE_LATENCY 1 DIVROUNDUP ENTER_HS_MODE_LATENCY DSI_VM_TIMING7 31 16 2 REG_TLPXBY2 4 DIVROUNDUP 1 ENTER_HS_MODE_LATENCY REG_THSPREPARE 4 DIVROUNDUP REG_THSPRPR_THSZERO 3 4 2 1 The formula for ENTER_HS_MODE_LATENCY timing is relevant only in video mode It does not need to be programmed in command mode 2 The formula DIVROUNDUP value div is equivalent to ROUNDU...

Page 1663: ...tical that DSI_VM_TIMING7 15 0 EXIT_HS_MODE_LATENCY 1 EXIT_HS_MODE_LATENCY DIVROUNDUP THS TRAIL EXIT_HS_MODE_LATENCY THS EXIT 4 1 THS EOT 2 1 The formula for EXIT_HS_MODE_LATENCY timing is relevant only in video mode It does not need to be programmed in command mode 2 The formula DIVROUNDUP value div is equivalent to ROUNDUP value div 7 4 3 2 3 Extra LP Transitions Some DSI receivers require extra...

Page 1664: ...PI 1 0 standard The sync events and pixels must be sent according to the display mode timings Data are received from the video port The display controller is in charge of fetching the data from the system memory and providing the data to the DSI protocol engine using the video port The short packets used for the sync event are using precalculated 32 bit values The long packets are constructed usin...

Page 1665: ...s implemented to allow the DSI protocol engine to store incoming pixels from the display controller through the video port while sending the DSI formatted frame to the DSI_PHY The ping pong buffer is supported in command mode provided the size of the packet defined in the header register is less than the size of each line buffer 768 32 bits If the size of the packet is greater than the size of the...

Page 1666: ...ng during that period Two set of registers are available for High speed interleaving when high speed command mode packets must be sent during a video stream on the PPI link Low power interleaving when low power command mode packets must be sent during a video stream on the PPI link 7 4 3 3 5 1 HS Command Mode Interleaving Programming Model Figure 7 91 shows the various HS mode scenarios in interle...

Page 1667: ...IL THS EXIT For the following equations BLANKING_PERIOD represents the BLLP HSA HBP or HFP blanking periods The HS_INTERLEAVING period represents the maximal period HS command mode packets Its value is set in the BL_HS_INTERLEAVING HSA_HS_INTERLEAVING HBP_HS_INTERLEAVING or HFP_HS_INTERLEAVING registers depending on the blanking type In each scenario two calculations are present depending on the v...

Page 1668: ...MODE 1 HS_INTERLEAVING min HS_INTER1 HS_INTER2 7 4 3 3 5 2 LP Command Mode Interleaving Programming Model Figure 7 92 shows the various LP mode scenarios in interleaving mode during a blanking gap For each type of blanking gap a dedicated bit field determines the number of TxByteClkHS clock cycles used for interleaving in LP command mode packets BL_LP_INTERLEAVING bit field DSI_VM_TIMING6 15 0 def...

Page 1669: ...VING or HFP_LP_INTERLEAVING registers depending on the blanking type ALLOWED_HSBYTE_CLOCKS_FOR_LP represents the number of TxByteClkHS clock cycles during which LP interleaving can appear To calculate the LP_INTERLEAVING value 1 Calculate how many TxByteClkHS clock cycles can be reserved for LP interleaving during the appropriate blanking video mode gap 2 Calculate the LP_INTERLEAVING value accord...

Page 1670: ...are users must consider the delay in processing the transfer of the data from to the slave port to from the module 7 4 3 5 1 Shadowing Register The two first SCP registers for the DSI complex I O address map must be implemented as shadow registers The shadowing mechanism is enabled disabled using the DSS DSI_COMPLEXIO_CFG1 31 SHADOWING bit When setting the DSS DSI_COMPLEXIO_CFG1 31 SHADOWING bit t...

Page 1671: ...th DSI complex I O and DSI PLL controller modules 7 4 3 6 1 Complex I O Power Control Commands 7 4 3 6 1 1 Complex I O Power Control Commands The DSI complex I O can be set into three modes OFF In this power state the complete DSI_PHY circuit is powered down The internal LDO is OFF ON In this power state the complete DSI_PHY circuit is powered on and functional ULPS In this power state the ULPS ex...

Page 1672: ... change to a state which is the current one acknowledge has been received the command is ignored nothing is sent to the DSI complex I O To change state to ULP state users must ensure that all the three ULPSActiveNot signals are low The ULPSActiveNot_ALL0_IRQ interrupt can be used by software users to determine the state of the ULPSActiveNot signals The change from ULP to ON state is required befor...

Page 1673: ...he DSI PLL Control module All the DSI PLL power is controlled by the DSI protocol engine except the LDO power of the PLL and HSDIVIDER that can be controlled by the DSI PLL controller module Indeed the HSDIVIDER and PLL SYSRESET signals can be forced by the DSI PLL controller module by setting DSS DSI_PLL_CONTROL 4 DSI_HSDIV_SYSRESET and DSS DSI_PLL_CONTROL 3 DSI_PLL_SYSRESET bits respectively By ...

Page 1674: ...0 VC_EN bit set to 1 and DSS DSI_VCn_CTRL 4 MODE bit set to 0 No command mode requiring high speed transfer one or more VCs using command mode can be active Or DSS DSI_CTRL 0 IF_EN bit reset to 0 if all previous conditions are not required The deassertion of the DSIStopClk depends on one of the following conditions the DSI interface is enabled by setting the DSS DSI_CTRL 0 IF_EN bit to 1 Clock lan...

Page 1675: ...general purpose GP timer to handle this This timer is used for existing ULP status mode for the active lanes clock and or data lanes The sequence to exit ULP state is 1 Change the state of TxULPSExit for each lane to ACTIVE 2 Wait for the interrupt indicating that all lanes with TxULPSExit active have acknowledged by asserting ULPSActiveNot This is done by reading the DSS DSI_COMPLEXIO_IRQSTATUS U...

Page 1676: ...op_State_x4_IO Stop_State_x16_IO field DSI_TIMING1 15 0 The FORCE_TX_STOP_MODE_IO bit is reset by hardware when the time is reached This bit can be reset by software The calculation of the number of DSI_FCLK cycles assertion period is defined by Total period in DSI_FCLK cycles DSI_TIMING1 12 0 STOP_STATE_COUNTER_IO x DSI_TIMING1 14 STOP_STATE_X16_IO x 15 1 x DSI_TIMING1 13 STOP_STATE_X4_IO x 3 1 7...

Page 1677: ...ate The ForceTXStopMode timer is used to define the minimum duration of LP 11 state The Stop State can be longer if there is no activity The hardware resets the ForceTXStopMode bit followed by an internal logic reset except all register values and TX FIFO content then resets the DSS DSI_CTRL 0 IF_EN bit The software should take action to recover by resetting the peripheral for example if it is not...

Page 1678: ...O to drive LP 11 stop state This is followed by the generation of the interrupt The hardware will perform an internal logic reset including the TX FIFO content but excluding the register values and then resets the DSS DSI_CTRL 0 IF_EN bit The software should wait for the DSS DSI_CTRL 0 IF_EN bit to be reset to 0 before taking any recovery action by resetting for example the peripheral if it is not...

Page 1679: ...VC_EN is set to 1 7 4 3 8 Bus Turnaround The bus turn around BTA is not automatically sent by default after each packet sent to the display s It is programmable independently for each VC ID The VC can be enabled when DSS DSI_VCn_CTRL 6 BTA_EN bit is set to 1 by software The software should ensure that when the BTA is sent to the peripheral there is enough time allocated for the response and the BT...

Page 1680: ...a transfer using the video port the bus turnaround enable bit DSS DSI_VCn_CTRL 6 BTA_EN can be selected at any time during the transfer of the packet In case of video mode packets data and synchronization events users cannot determine when the BTA is sent relatively the video mode packets so it is highly recommended to use manual BTA mode only for packets generated in command mode but it is possib...

Page 1681: ...ing requests in TX FIFO not already taken into account for transfer scheduling the RX FIFO requests and the data from video port are ignored Only the current transfer on DSI link and already scheduled ones are transmitted All the other transfers are discarded Synchronized reset The mode is only valid if there is VC using the video mode and if it is active The principle is to wait for the current v...

Page 1682: ... captured in the line buffer using the STALL mechanism In case there is no line buffer instantiated that is DSS DSI_CTRL 13 12 LINE_BUFFER bit field set to 0 it is not possible to use the video port to provide data The line buffer should be filled up according to the word count defined in the DSS DSI_VCn_LONG_PACKET_HEADER register header The value should be written before the TE trigger event is ...

Page 1683: ...he transmission of long packets a checksum is calculated over the payload portion of the data packet Note that for the special case of a zero length payload the 2 byte checksum is set to 0xFFFF The checksum can only indicate the presence of one or more errors in the payload Unlike ECC the checksum does not enable error correction For this reason checksum calculation is not useful for some unidirec...

Page 1684: ...t is a fixed short packet 4 bytes that is added at every HS to LP transition This function is enabled by the DSI_CTRL 19 EOT_ENABLE bit The EOT packet has a fixed format Data Type DI 5 0 0b001000 Virtual Channel DI 7 6 0b00 Payload Data 15 0 0x0F0F ECC 7 0 0x01 When more than one data lane is used the bytes in the EOT packet are distributed across multiple lanes EOT packet generation is supported ...

Page 1685: ...ve an interface to L4 interconnect The programmable features are managed by registers mapped into the DSI protocol engine 7 4 4 2 DSI PLL Controller Architecture The DSI PLL is an ADPLLM module The pixel clock PCLK frequency range is 2 to 68 25 MHz This may be divided by 2 This is performed by setting the DSS DSI_PLL_CONFIGURATION2 12 DSI_PLL_HIGHFREQ bit to 1 Figure 7 104 shows the internal DSI P...

Page 1686: ...gnals of the DSI PLL configuration operate according to Table 7 35 The values in the table indicate the operation when the PLL is not locked Table 7 35 DSI PLL Operation Modes When Not Locked DSI PLL Stop mode Stop mode Idle bypass Operation Mode Low power 1 Fast Relock 1 Mode Description Output clocks Output clocks Selects when PLL stopped stopped and HSDIVIDER Lowest Fastest bypass clocks power ...

Page 1687: ...RECAL_IRQ interrupt indicates that the DSI PLL control module has sent a recalibration request to the DSI PLL To monitor this event read the DSS DSI_IRQSTATUS 9 PLL_RECAL_IRQ bit Set this bit to 1 to clear the status bit 7 4 5 DSI Complex I O Functionalities 7 4 5 1 DSI Complex I O Overview DSI_PHY is a complex I O with 3 unidirectional HS Lane Modules This includes 2 data lane modules and 1 clock...

Page 1688: ...the interface width 16 bits and the pixel format output 24 bits 7 4 6 2 RFBI Interconnect FIFO The interconnect FIFO receives the data from RFBI_DATA write requests to the L4 interconnect slave port The data in the interconnect FIFO are read by the RFBI and sent to the LCD panel The width of the interconnect FIFO is 32 bits The size of the interconnect FIFO is 24 words of 32 bits that is 24 words ...

Page 1689: ...0 G0 0 R1 0 B1 0 7 4 6 5 Unmodified Bits In a cycle if every bit in the interface does not have a pixel value the status of the unused bits can be programmed to be 0 1 or the previous value I O power consumption optimization 7 4 6 6 Bypass Mode In bypass mode the RFBI path is bypassed and the display controller data and signals are sent directly to the output interface of the RFBI 7 4 6 7 Send Com...

Page 1690: ...pixels 3 cycles 1 pixel 6 1 pixel cycle 2 pixels 4 1 pixel 2 cycles 2 pixels 4 1 pixel 3 cycles 2 pixels 4 2 pixels 3 cycles 2 pixels 6 Display Controller 1 pixel cycle N A 4 1 pixel 2 cycles N A 3 1 pixel 3 cycles N A 3 2 pixels 3 cycles N A 6 7 4 7 Video Encoder Functionalities The input formats supported by the encoders are 24 bit 4 4 4 RGB The encoder output is the DAC stage for more informati...

Page 1691: ...re Overview NOTE Output video mode can be either composite video CVBS output or separate video S video Luma and Chroma outputs Composite video only AVDAC1 is used Separate video Luma Chroma Both AVDAC1 Luma and AVDAC2 Chroma are used The selection is programmed with DSS DSS_CONTROL 6 VENC_OUT_SEL bit Composite video is the default selection 7 4 7 1 Test Pattern Generation For diagnostic purposes t...

Page 1692: ...ently controlled by the DSS VENC_GAIN_U and DSS VENC_GAIN_V register bits 7 4 7 4 Subcarrier and Burst Generation The encoder uses a 32 bit subcarrier increment to synthesize the subcarrier The value of the subcarrier increments required to generate the desired subcarrier frequency for NTSC and PAL format is found by S_CARR ROUND Fsc Fclkenc x 232 where Fsc Frequency of the subcarrier Fclkenc Freq...

Page 1693: ...CAUTION The setting of the value of the SLINE 4 0 bit field depends on the video standard PAL mode Because there is a one line offset program the desired line number 1 To activate the closed caption on line 21 0x15 program the value 0x15 1 0x14 The default value is 0x15 1 0x16 line 22 NTSC mode Because there is a four line offset program the desired line number 4 To activate the closed caption on ...

Page 1694: ...e 7 107 shows the parameters of closed caption line data implemented in different standards Figure 7 107 Closed Captioning Timing NOTE The interval A is controlled by the DSS VENC_LN_SEL 25 16 LN21_RUNIN bit field The interval B is controlled by DSS VENC_CC_CARR_WSS_CARR 15 0 FCC bit field Table 7 43 Closed Caption Standard Timing Values Intervals Description Timing Values for Encoding Timing Valu...

Page 1695: ... VENC_CC_CARR_WSS_C ARR 31 16 FWSS bit field 0x043F 0x2F72 0x04AC 0x2B6D value To select the line where the WSS data are encoded program the DSS VENC_L21_WC_CTL 12 8 LINE bit field CAUTION The setting of the LINE 12 8 bit field value depends on the video standard PAL mode There is an one line offset so program the wanted line number 1 The recommended value is line 0x16 1 0x17 23rd line Note that t...

Page 1696: ...ode Color burst Data dss 081 Public Version Display Subsystem Functional Description www ti com Figure 7 108 WSS Timing 7 4 7 7 Video DAC Stage Architecture and Control Figure 7 109 shows the architecture of the video DAC stage comprising two 10 bit video DACs AVDAC1 and AVDAC2 instances 1696 Display Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incor...

Page 1697: ...S Video Chroma C analog TV output The device system control module provides two dedicated AVDAC registers CONTROL CONTROL_AVDAC1 and CONTROL CONTROL_AVDAC2 to configure the respective channels through the following bit field CONTROL CONTROL_AVDACx 20 16 AVDACx_COMP_EN Allows direct control over the configuration of the analog TV output See Table 7 45 Section 7 5 8 Video Encoder Basic Programming M...

Page 1698: ...e TV detection disconnection feature is supported only for AVDAC1 The TV disconnection feature is recommended to save power The TV detection disconnection is operational only when video out is active Therefore to detect cable connection automatically it is necessary to periodically activate the video out to test for cable presence This block compares the output of AVDAC1 cvideo1_out to a reference...

Page 1699: ...connected to the power IC TWL50xx device 5 The TVDET pulse is set high by hardware according to the settings in the DSS VENC_TVDETGP_INT_START_STOP_X and DSS VENC_TVDETGP_INT_START_STOP_Y registers 6 Check the TVINT output signal When TVINT is set to 1 the load is connected CAUTION If AC coupling is selected two TVDET pulses are required to set high the TVINT signal Due to the internal logic of th...

Page 1700: ... 4 7 9 4 Recommended TV Detection Disconnection Pulse Waveform To enable the detection disconnection of the load the circuit requires that the TVDET pulse resembles the following waveform As explained in Section 7 4 7 9 2 TV Detection Procedure and in Section 7 4 7 9 3 TV Disconnection Procedure by using the video encoder registers the TVDET pulse polarity start and stop is programmable The only c...

Page 1701: ...on Disconnection Usage The TV detection TV disconnection is based on the difference in voltage levels in the output of the TV buffer depending on the load status The operation is slightly different for ac and for dc operation For DC operation the cvideo1_out voltage is compared against a voltage reference that makes the comparator trigger in each sync pulse while the load is connected For AC opera...

Page 1702: ...de 7 4 7 10 Video DAC Stage Bypass Mode The 10 bit video DAC stage has a TVOUT buffer bypass mode that turns off the TVOUT buffers and redirects directly the outputs of the DACs to the VFB pins cvideo1_vfb for AVDAC1 and cvideo2_vfb for AVDAC2 This bypass mode is activated by setting the CONTROL CONTROL_DEVCONF1 18 TVOUTBYPASS bit to 1 The reset value of the CONTROL CONTROL_DEVCONF1 18 TVOUTBYPASS...

Page 1703: ...bypass mode an external amplifier is needed on the cvideo1_vfb and cvideo2_vfb pins 7 4 7 11 Video DAC Stage Test Mode The DAC stage can be tested for debug using either 10 bit external data or 10 bit internal register values directly connected to the DACs See Figure 7 114 for video DAC test in composite video mode and see Figure 7 115 for video DAC test in separate video mode Figure 7 114 DAC Tes...

Page 1704: ...the test mode 0x0 From the internal register DSS VENC_OUTPUT_TEST 25 16 CHROMA_TEST bit field for AVDAC2 and either DSS VENC_OUTPUT_TEST 9 0 COMPOSITE_TEST bit field composite video or DSS VENC_OUTPUT_CONTROL 25 16 LUMA_TEST s video mode for AVDAC1 0x1 From the video port G 1 0 B 7 0 NOTE In the external data test mode bypass mode the display controller must provide the data G 1 0 B 7 0 externally...

Page 1705: ...CONF1 11 Description DAC_POWERD CHROMA_ENAB COMPOSITE_ENA LUMA_ENABL TVOUTBYPASS TVACEN N_BGZ LE BLE E Total power down 0 x x x x x Bandgaps powered down Standby analog in 1 0 0 0 x x power down except bandgaps LDOs Full power up in DC 1 1 1 1 0 0 mode Full power up in AC 1 1 1 1 0 1 mode Full power up in 1 1 1 1 1 x TVOUT bypass mode DAC only mode 1705 SWPU177N December 2009 Revised November 2010...

Page 1706: ...o take the display subsystem out of reset PRCM CM_FCLKEN_DSS 0 EN_DSS1 bit set to 1 PRCM CM_FCLKEN_DSS 1 EN_DSS2 bit set to 1 PRCM CM_FCLKEN_DSS 2 EN_TV bit set to 1 PRCM CM_ICLKEN_DSS 0 EN_DSS bit set to 1 Once the clocks are enabled as shown the display subsystem can be taken out of reset 3 Write 1 in the DSS DSS_SYSCONFIG 1 SOFTRESET bit to apply the soft reset to the subsystem 4 Read the DSS D...

Page 1707: ...P Start Period Updated on External VSYNC LCD output Digital output DSS DISPC_CONTROL X 1 X 1 DSS DISPC_CONFIG X X DSS DISPC_DEFAULT_COLOR_m m 0 X DSS DISPC_DEFAULT_COLOR_m m 1 X DSS DISPC_TRANS_COLOR_m m 0 X DSS DISPC_TRANS_COLOR_m m 1 X DSS DISPC_LINE_NUMBER X DSS DISPC_TIMING_H X DSS DISPC_TIMING_V X DSS DISPC_POL_FREQ X DSS DISPC_DIVISOR X DSS DISPC_SIZE_DIG X DSS DISPC_SIZE_LCD X DSS DISPC_GFX...

Page 1708: ...raphics layer The graphics window is present and the graphics pipeline is active Burst size DSS DISPC_GFX_ATTRIBUTES 7 6 GFXBURSTSIZE field The default burst size at reset time is 4 x 32 bytes The possible values are 4 x 32 8 x 32 and 16 x 32 bytes The burst size is initialized at boot time by the software and never changes as long as the display controller is enabled This field indicates the maxi...

Page 1709: ...ABLE bit The bit indicates if the palette must be loaded before the graphics data for the following frame The bit is set by software and reset by hardware Base address of the palette gamma table buffer in system memory DSS DISPC_GFX_TABLE_BA register The default value of this register at reset time is 0x0 The base address is aligned on a 32 bit address Depending on the pixel size of graphics data ...

Page 1710: ...iple of eight pixels for 1 BPP four pixels for 2 BPP and two pixels for 4 BPP The maximum bandwidth efficiency for accessing the pixels in system memory is reached when the width of the graphics window in bytes is a multiple of the graphics burst size defined in the DSS DISPC_GFX_ATTRIBUTES 7 6 GFXBURSTSIZE bit field in bytes NOTE When the RGB24 packed format is selected the width must be a multip...

Page 1711: ...FXWINDOWSKIP bit field must be set according to the video1 and graphics windows overlap The default value at reset time is 0x0 Disable When video1 is not present the DSS DISPC_GFX_WINDOW_SKIP 31 0 GFXWINDOWSKIP bit field should be reset When the color key is used the DSS DISPC_GFX_WINDOW_SKIP 31 0 GFXWINDOWSKIP bit field should be reset Graphics window skip DSS DISPC_GFX_WINDOW_SKIP 31 0 GFXWINDOW...

Page 1712: ...OSX DISPC_GFX_SIZE 10 0 GFXSIZEX DISPC_VID1_POSITION 10 0 VIDPOSX 1 X DISPC_VID1_SIZE 10 0 VIDSIZEX 1 dss 091 X VID1 GFX VID1 GFX X OR BPP defines the number of bytes per pixel for graphics buffer OR VID1 GFX X X DISPC_VID1_SIZE 10 0 VIDSIZEX 1 DISPC_GFX_WINDOW_SKIP 31 0 X DISPC_GFX_PIXEL_INC 15 0 GFCPIXELINC 1 BPP 1 dss 092 Public Version Display Subsystem Basic Programming Model www ti com Figur...

Page 1713: ...is bit field indicates the maximum burst size for the specific pipeline In case of misalignment the DMA engine may issue single and or smaller burst requests because the burst size must be aligned to the burst boundary Preload configuration DSS DISPC_VIDn_ATTRIBUTES 19 VIDFIFOPRELOAD bit The default preload configuration uses the DSS DISPC_VIDn_PRELOAD register value the reset value is 256 bytes t...

Page 1714: ...eo buffer width DSS DISPC_VIDn_PICTURE_SIZE 10 0 VIDORGSIZEX The default value at reset time is 0x0 1 pixel The buffer width in system memory is from 1 up to 2048 pixels All the integer values in the range 1 2048 are allowed Software users must program this bit field to the value minus 1 Video buffer height DSS DISPC_VIDn_PICTURE_SIZE 26 16 VIDORGSIZEY The default value at reset time is 0x0 1 pixe...

Page 1715: ...on the height should be adjusted by software to limit the bottom edge of the window inside the screen Video picture width in system memory DSS DISPC_VIDn_PICTURE_SIZE 10 0 VIDORGSIZEX bit field with n 1 or 2 The default value at reset time is 0x0 1 pixel The window width is from 1 to 2048 pixels All integer values in the range 1 2048 are allowed with RGB16 and RGB24 video data For YUV2 4 2 2 and U...

Page 1716: ... and VIDSIZEY 10 0 bit field values must be programmed with the value desired minus 1 Horizontal up downsampling increment value DSS DISPC_VIDn_FIR 11 0 VIDFIRHINC bit field with n 1 or 2 The unsigned integer value range is 1 4096 The software calculates the value using the following equation 11 NOTE If the VIDFIRHINC 11 0 bit field value is greater than 4096 it is clipped to 4096 If VIDSIZEX 10 0...

Page 1717: ... to 7 The 3 tap vertical up downsampling coefficients are defined in these registers There are eight registers for the eight phases with three coefficients for each or a total of 24 programmable coefficients for the vertical up downsampling block Each register contains two 8 bit signed coefficients and one 8 bit unsigned coefficient the central one In addition there are 2 tap vertical up downsampl...

Page 1718: ...b 0 0 0 0 GY 298 256 298 256 GCr 208 179 137 118 GCb 100 86 55 47 BY 298 256 298 256 BCr 0 0 0 0 BCb 517 443 541 465 VidFullRange 0 1 0 1 7 5 3 4 Rotation Mirroring Display Subsystem Settings This section describes rotation mirroring settings The device provides flexible mechanisms for an efficient implementation of rotation using the display subsystem its DMA engine and the rotation engine of the...

Page 1719: ...tes pixel RGB16 YUV2 UYVY For more information on the graphics data formats please refer to Section 7 4 2 2 Graphics Pipeline For more information on the video data formats please refer to Section 7 4 2 3 Video Pipeline In the video pipeline the YUV 4 2 2 format is converted into a full YUV 4 4 4 format by interpolation of the chrominance values from neighboring pixels After this interpolation is ...

Page 1720: ...data is stored in internal SRAM 7 5 3 4 2 1 Rotation Mirroring Registers To set up the rotation and or mirroring the following registers must be programmed Graphics pipeline GFX DSS DISPC_GFX_BAj DSS DISPC_GFX_PIXEL_INC DSS DISPC_GFX_ROW_INC DSS DISPC_GFX_ATTRIBUTES DSS DISPC_GFX_POSITION DSS DISPC_GFX_SIZE DSS DISPC_GFX_FIFO_THRESHOLD Video pipelines VID 1 and 2 DSS DISPC_VIDn_BAj DSS DISPC_VIDn_...

Page 1721: ...pecify the format of the video frame RGB16 or YUV4 2 2 VIDCOLORCONVENABLE If the video is in YUV4 2 2 format set this field to enabled VIDROTATION Set this field to the value corresponding to the rotation angle desired only if the frame contains non RGB pixel data otherwise set it to 0x0 regardless of the degree of rotation See Section 7 5 3 4 4 for more information VIDROWREPEATENABLE Set this fie...

Page 1722: ...emory contiguous pixels except for the RGB24 packet format Table 7 52 lists the rotation register settings for RGB24 packet format only for the two video pipelines Table 7 51 DMA Rotation Register Settings Rotation Registers GFX VIDx 1 0 degree DSS DISPC_xxx_BAj ba DSS DISPC_xxx_PIXEL_INC 1 DSS DISPC_xxx_ROW_INC 1 90 degrees DSS DISPC_xxx_BAj ba iw x ih 1 x ps DSS DISPC_xxx_PIXEL_INC iw x ps 1 DSS...

Page 1723: ...se address of the buffer in the system memory top left corner of the picture iw number of pixels per row 1 original picture in system memory for BITMAP and RGB formats and number of pixels per row divided by 2 for YUB422 formats h number of lines 1 original picture in system memory ps pixel size in bytes BITMAP8 1 byte RGB16 2 bytes YUV4 2 2 4 bytes See Table 7 50 for more information of these par...

Page 1724: ... be set up as described for DMA rotation see Section 7 5 3 4 2 Image Data from On Chip SRAM The differences are in the setup of the following registers DISPC_xxx_ROW_INC This field contains the DMA addressing increment after each row line of pixels This field is used to add the remaining delta at the end of each line to reach the 2048 pixel line size of the VRFB see Table 7 54 for the formula DISP...

Page 1725: ...al base addresses because the VRFB module is not aware of the actual image size Figure 7 123 illustrates why this occurs and how the offset is calculated Figure 7 123 Offset for VRFB Rotation Δiw Image width delta between the actual image width and the programmed image width because of the page width Δih Image height delta between the actual image height and the programmed image height because of ...

Page 1726: ...XEL_INC 1 DSS DISPC_xxx_ROW_INC 2048 iw x ps 1 270 degrees DSS DISPC_xxx_BAj VBA90 2048 x iw 1 x ps offset DSS DISPC_xxx_PIXEL_INC 1 DSS DISPC_xxx_ROW_INC 2048 ih x ps 1 1 VBAx virtual address of the chosen VRFB context and orientation iw image width width in pixels for RGB width in pixels divided by 2 for YUV ih image height ps pixel size in bytes 2 bytes per pixel for RGB 4 bytes per pixel for Y...

Page 1727: ...from the SDRAM and SRAM The 2D addressing mode is used but even when accessing the SDRAM buffer some post processing must be performed on the YUV 4 2 2 data depending on the rotation These bits are set only when the video format is not RGB otherwise the bit field is reset to 0 Table 7 56 and Table 7 57 describe the configuration of these registers Table 7 56 Video Rotation Register Settings YUV On...

Page 1728: ...e generated by averaging the contiguous chrominance samples 7 5 3 4 5 Video DMA Optimization When a rotation of 90 or 270 degrees is required the memory traffic can be reduced as described in Section 7 4 2 8 Rotation 1 Enable DMA optimization for the video pipelines VID1 and VID2 by applying the following settings to the DISPC a Enable DISPC DMA optimization by setting DISPC_VIDn_ATTRIBUTES 20 VID...

Page 1729: ...C_CPR_COEF_R DSS DISPC_CPR_COEF_G DSS DISPC_CPR_COEF_B Setting resetting the DSS DISPC_CONTROL 0 LCDENABLE bit enables disables the LCD output A valid configuration must be set before enabling the LCD output 7 5 3 5 1 LCD Attributes The following fields define the attributes of the panel connected to the display controller Monochrome or color panel the DSS DISPC_CONTROL 2 MONOCOLOR bit Passive Mat...

Page 1730: ...trix display Figure 7 125 Timing Values Description Active Matrix Display The following bit fields define the timing generation of ac bias output enable in active matrix mode Invert output enable DSS DISPC_POL_FREQ 15 IEO bit ac bias pin frequency DSS DISPC_POL_FREQ 7 0 ACB bit field ac bias pin transitions per interrupt DSS DISPC_POL_FREQ 11 8 ACBI bit field ac bias gated DSS DISPC_CONFIG 8 ACBIA...

Page 1731: ...12 16 1 1 1 2 3 tap 8 8 16 24 32 5 tap 4xPCDmin 4xPCDmin 4xPCDmin 4xPCDmin 4xPCDmin 1 2 1 4 4xPCDmin 4xPCDmin 4xPCDmin 4xPCDmin 4xPCDmin Table 7 61 Pixel Clock Frequency Limitations RGB16 and YUV4 2 2 Passive Matrix Display Mono8 Min PCD Values Horizontal Resampling Off Up 1 1 1 2 1 2 1 3 1 3 1 4 Vertical Off 8 8 16 24 32 Resampling Up 8 8 16 24 32 1 1 1 2 3 tap 16 16 32 48 64 5 tap 8xPCDmin 8xPCD...

Page 1732: ...ic enabled DSS DISPC_CONTROL 7 SPATIALTEMPORALDITHERENABLE bit Spatial temporal dithering logic number of frames DSS DISPC_CONTROL 31 30 SPATIALTEMPORALDITHERFRAMES bit field The default value of this bit field at reset time is 0x0 which is 1 frame only spatial processing without temporal dithering The possible values are 0x0 one frame 0x1 two frames and 0x2 four frames The number of frames is ini...

Page 1733: ... field When all of these bit fields are set to the appropriate values set the DSS DISPC_CONTROL 5 GOLCD bit to indicate that all shadow registers of the pipelines connected to the LCD output are latched by the hardware only if the DSS DISPC_CONTROL 0 LCDENABLE bit is already set to 1 If the LCD output is disabled the new values will be updated when the DSS DISPC_CONTROL 0 LCDENABLE bit will be set...

Page 1734: ...gure 7 129 Color Phase Rotation Matrix G Component Only Figure 7 130 Color Phase Rotation Matrix B Component Only When all of these bit fields are set to the appropriate values set the DSS DISPC_CONTROL 5 GOLCD bit to indicate that all shadow registers of the pipelines connected to the LCD output are latched by the hardware only if the DSS DISPC_CONTROL 0 LCDENABLE bit is already set to 1 If the L...

Page 1735: ... component only depends on the corresponding input color The coefficients can easily be used to reduce the impact of a non white backlight Let s take the example of a blue backlight In this case users have the feeling that a blue film has been added on the screen and then each color seems to be too much blue The goal is then to reduce the Blue component and to keep the Red and Green ones unchanged...

Page 1736: ...efficients of the CPR matrix to better correct a non white backlight The goal is to find the correct coefficients that remove the color offset added by the non white backlight 7 5 3 5 6 2 Color Phase Rotation Standard Matrix In the following example the LCD backlight adds an offset of 128 B_offset to the Blue component Figure 7 134 shows an example of matrix that reduces the offset of the screen t...

Page 1737: ... the matrix the result will always be equal to the offset added by the LCD backlight 7 5 3 6 TV Set Specific Control Registers The following registers define the digital output configuration DSS DISPC_CONTROL DSS DISPC_CONFIG DSS DISPC_DEFAULT_COLOR_m m 1 DSS DISPC_TRANS_COLOR_m m 1 DSS DISPC_SIZE_DIG The digital output is enabled disabled by setting resetting the DSS DISPC_CONTROL 1 DIGITALENABLE...

Page 1738: ...ALPHA The value 0xFF corresponds to 100 opaque and 0 to 100 transparent NOTE The destination graphics transparency color key is available only to the overlay with which the graphics pipeline is connected The software must set the correct configuration of the LCD and digital overlays NOTE When the alpha blender is enabled the destination transparency color key is not available and the source transp...

Page 1739: ...enerated an interrupt Based on the VC number the register DSI_VCn_IRQSTATUS indicates the event generating the interrupt In addition it includes one bit for the status of error reporting for the complex I O 7 5 4 4 Global Register Controls Prior to receive data from the DSI complex I O the DSI_PHY_SCP registers in the DSI complex I O must be configured Refer to Section 7 5 6 for more details Table...

Page 1740: ...MA threshold DSS DSI_VCn_CTRL 26 24 DMA_RX_THRESHOLD bit field for RX FIFO and DSS DSI_VCn_CTRL 19 17 DMA_TX_THRESHOLD bit field for TX FIFO Mode speed DSS DSI_VCn_CTRL 9 MODE_SPEED bit ECC transmission DSS DSI_VCn_CTRL 8 ECC_TX_EN bit CS transmission DSS DSI_VCn_CTRL 7 CS_TX_EN bit The VC ID not calculated by the DSI module but provided while writing into the registers DSI_VCn_SHORT_PACKET_HEADER...

Page 1741: ...g to the display module timings The DSI complex I O pads must also be configured first See Section 7 5 6 DSI Complex I O Basic Programming Model 7 5 4 8 Video Mode The DSS DSI_VM_TIMING1 DSS DSI_VM_TIMING2 DSS DSI_VM_TIMING3 DSS DSI_VM_TIMING4 DSS DSI_VM_TIMING5 DSS DSI_VM_TIMING6 and DSS DSI_VM_TIMING7 registers define the timings of the video mode The DSS DSI_CTRL 20 BLANKING_MODE bit defines if...

Page 1742: ...case it is not required to write into the payload register For consecutive long packets the header should be written into the DSS DSI_VCn_LONG_PACKET_HEADER register even if the value remains the same The TX FIFO stores all the pending bytes to be sent to the peripheral s Multiple receivers can be addressed using the VC capability The 32 bit write requests only for each VC to the TX FIFO should be...

Page 1743: ... complex I O This interrupt can be monitoring by reading the DSS DSI_VCn_IRQSTATUS 2 PACKET_SENT_IRQ status bit The DSS DSI_CTRL 3 TX_FIFO_ARBITRATION bit defines if the arbitration scheme is Round robin between enabled VCs with pending ready requests pending ready request means that all bytes for the packets are in the FIFO or the space of the FIFO for the VC is full starting from the VC which ha...

Page 1744: ...ess When waiting to receive the first VSYNC event on the video port to start the video mode on DSI link no command data from TX FIFO should be sent on the interface It is required to ensure that when receiving the VSYNC event there is no on going command mode transfer that could delay the start of video mode on the DSI link 7 5 4 10 2 Command Mode RX FIFO The RX FIFO is used to store the data rece...

Page 1745: ...the received bytes in the RX FIFO only the DSS DSI_VCn_SHORT_PACKET_HEADER register is used since the hardware does not keep track of the header position for long packets and start end of each packet The software must extract the information from the bytes read from the RX FIFO There is no specific hardware to track the received bytes in the RX FIFO The DSS DSI_VCn_LONG_PACKET_HEADER and DSS DSI_V...

Page 1746: ... DSI_VCn_CTRL 23 21 DMA_TX_REQ_NB is dedicated to DMA request numbering for the TX FIFO The DSS DSI_VCn_CTRL 29 27 DMA_RX_REQ_NB is dedicated to DMA request numbering for the RX FIFO When the DMA request is used to indicate the number of 32 bit values ready in the RX FIFO or BTA has been received from peripheral indicating end of the transfer from peripheral to host for a transfer to the system me...

Page 1747: ...CFG2 LANEx_ULPS_SIG2 and DSS DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG1 bits are both being written to 0 they can be combined into one write Both bits must be read back to confirm they are effective before proceeding 7 5 4 11 2 Exiting ULPS To exit from ULPS for a clock lane the following sequence is required 1 Change the state of TxUlpsExit for each lane to ACTIVE by setting the DSS DSI_COMPLEXIO_CFG2 LA...

Page 1748: ...orresponding to lane 1 to lane 3 bit to 0 6 Reset the DSS DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG1 x range is 1 to 3 corresponding to lane 1 to lane 3 bit to 0 NOTE When the DSS DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG2 and DSS DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG1 bits are both being written to 0 they can be combined into one write Both bits must be read back to confirm they are effective before proceeding To ex...

Page 1749: ...fter disabling video mode in DSI 7 5 4 12 2 Command Mode Transfer Example 1 CAUTION In DSI command mode the display controller must be configured in stall mode by setting the DSS DISPC_CONTROL 11 STALLMODE bit to 1 Description One channel command mode no DMA requests manual bus turn around 1 Configure the DSS DSI_VCn_CTRL register as follows SOURCE bit set to 0 The source is the L4 interconnect po...

Page 1750: ...tion One channel command mode DMA request automatic bus turn around 1 Configure the DSS DSI_VCn_CTRL register as follows SOURCE bit set to 0 The source is the L4 interconnect port BTA_LONG_EN bit is set to 1 Automatic BTA on long packet BTA_SHORT_EN bit is set to 1 Automatic BTA on short packet MODE bit set to 0 The command mode is selected 2 Enable the packet sent interrupt by setting the DSS DSI...

Page 1751: ...eset The DSI PLL control module does not have its own software reset It is reset by the DSI protocol engine Nevertheless software users can monitor the reset status of the DSI PLL control module by reading the DSS DSI_PLL_STATUS 0 DSI_PLLCTRL_RESET_DONE status bit 7 5 5 2 DSI PLL Programming Blocks Figure 7 135 shows the DSI PLL programming blocks Figure 7 135 DSI PLL Programming Blocks 1751 SWPU1...

Page 1752: ...bit to 1 to prevent uncontrolled frequencies affecting the DSI_PHY and display subsystem during PLL locking In manual mode the shadow register must be updated anyway so that valid values are present when later selecting automatic mode Figure 7 136 shows the DSI PLL Go flow chart in manual mode DSS DSI_PLL_CONTROL 0 DSI_PLL_AUTOMODE bit set to 0 Figure 7 136 DSI PLL Go Sequence Manual Mode NOTE All...

Page 1753: ... outlined blocks show operations performed by software Other blocks show operations performed by hardware 7 5 5 4 DSI PLL Clock Gating Sequence Clock gating can be used to reduce system power consumption when the DSI protocol engine indicates that it does not need the clock If the HSDIVIDER is not used the PLL can also be stopped at the cost of additional unstarting latency The DSI protocol engine...

Page 1754: ...Basic Programming Model www ti com Figure 7 138 Gated Mode Sequence NOTE All thick outlined blocks show operations performed by software 7 5 5 5 DSI PLL Lock Sequence The DSI PLL ADPLLM generates the CLKIN4DDR clock The HSDIVIDER generates two clocks DSI1_PLL_FCLK connected to the display controller DISPC and the DSI2_PLL_FCLK connected to the DSI protocol engine If these two clocks are not used t...

Page 1755: ... Set bit to 1 DSI_PLL_CONFIGURATION2 12 DSI_PLL_HIGHFREQ Set REGN factor such that Set REGN factor such that 0 75 int 2 1 2 1 CLKin MHz F MHz REGN 0 75 int 2 1 1 CLKin MHz F MHz REGN Set REGM4 factor such that _ 2 _ _ 4 1 DSI PHY MHz DSI PLL FCLK MHz REGM dss 190 CLKIN4DDR CLKIN4DDR CLKIN4DDR Public Version www ti com Display Subsystem Basic Programming Model REGM factor is programed by DSS DSI_PL...

Page 1756: ...o lower than 173 MHz at nominal voltage OPP100 and lower than 100 MHz at low voltage OPP50 program these frequencies to 90 MHz by setting the REGM3 and REGM4 factors to 11 divide by 12 This is done by setting the DSS DSI_PLL_CONFIGURATION1 22 19 DSS_CLOCK_DIV bit field and DSS DSI_PLL_CONFIGURATION1 26 23 DSIPROTO_CLOCK_DIV to 0xB DSI1_PLL_FCLK DSI2_PLL_FCLK 1080 12 90 MHz XGA Display on two data ...

Page 1757: ...L_LOSSREF status bit informs if the DSI PLL has lost the reference The DSS DSI_PLL_STATUS 4 DSI_PLL_LIMP status bit informs about the DSI PLL limp status 7 5 5 7 DSI PLL Recommended Values Table 7 68 shows the DSI PLL recommended values Table 7 68 Recommended Programming Values Field Name Value Description DSI_HSDIV_SYSRESET 0 Allow power FSM to control DSI_PLL_SYSRESET 0 Allow power FSM to contro...

Page 1758: ... O Basic Programming Model 7 5 6 1 Software Reset The clock domain using the TxByteClkHS from the DSI complex I O has a dedicated reset done information in the DSS DSI_COMPLEXIO_CFG1 29 RESET_DONE bit The DSS DSI_SYSCONFIG 1 SOFT_RESET bit is used to reset the TxByteClkHS power domain A dummy read using the SCP interface to any DSI_PHY register is required after DSI_PHY reset to complete the reset...

Page 1759: ...SI_COMPLEXIO_CFG1 10 8 DATA2_POSITION bit To add or remove the lane 2 it is required to be in OFF mode for the DSI complex I O The minimum requirement for the number of lanes is one clock lane and one data lane Note that by default the data lane 2 is not connected the DSS DSI_COMPLEXIO_CFG1 10 8 DATA2_POSITION bit reset value is 0 7 5 6 4 Display Timing Configuration NOTE Copyright 2005 2008 MIPI ...

Page 1760: ..._TCLKTRAIL bit field THS EXIT timing is programmed by the DSS DSI_PHY_REGISTER0 7 0 REG_THSEXIT bit field The DSI_PHY completes the SoT and EoT procedures once begun irrespective of any change in PPI signals If TXREQUESTHS goes low during the SoT procedure the PHY start the EoT procedure immediately after finishing the SoT procedure and no clock is transmitted STOPSTATE is high whenever the line i...

Page 1761: ...t field THS PREPARE THS ZERO timing is programmed by the DSS DSI_PHY_REGISTER0 23 16 REG_THSPRPR_THSZERO bit field THS ZERO will be extended if required so that the entire LP SoT procedure lasts an integer number of TXByteClkHS cycles THS SYNC corresponds to the length of the sync pattern which is 8 high speed bits and can be configured through the DSI_PHY_REGISTER2 31 24 HSSYNCPATTERN bit field T...

Page 1762: ...ck cycle of TxClkEsc see Section 7 4 3 7 3 TurnRequest FSM The DSI PHY transmits the turn around request pattern LP 11 10 00 10 00 00 00 00 see Figure 7 142 The number of 00 states in the end of the pattern is defined by TTA GO timing parameter and is programmable through the DSS DSI_PHY_REGISTER1 31 29 REG_TTAGO bit field in number of TxClkEsc clocks Following the transmission of the pattern the ...

Page 1763: ... command transmission on data lanes ULP state transmission on clock lane Low power data in receive mode Low power trigger in receive mode ULP state command on clock lane in receive mode ULP state command on data lane in receive mode 7 5 6 5 Error Handling A dedicated register for the DSI complex I O DSS DSI_COMPLEXIO_IRQSTATUS indicates the state of each error provided by the DSI complex I O error...

Page 1764: ... Basic Programming Model The RFBI programming model must be used for LCD display support only 7 5 7 1 DISPC Control Registers The following DISPC registers are used in RFBI mode The STALL mode is selected by setting the DSS DISPC_CONTROL 11 STALLMODE bit The DSS DISPC_CONTROL 5 GOLCD bit must not be set to 1 but the display controller configuration DMA engine pipelines associated to the LCD output...

Page 1765: ...en the transfer is finished the configuration used can be modified Table 7 69 RFBI Behavior RFBI_CONTROL 1 BYPASSMODE RFBI_CONTROL 0 ENABLE bit value RFBI Behavior bit value 0 0 L4 interconnect can write command param data and read data status from the Remote Frame Buffer RFB L4 interconnect access can only be done to the CSx actually active 0 1 The DISPC sends pixels to the RFB The stall signal i...

Page 1766: ...t and a new value is written in the DSS RFBI_PIXEL_CNT register when the current value in the register is a non zero the remaining number of pixels to transfer the ongoing transfer is aborted From the L4 interconnect side if the DSS RFBI_CONFIGi 10 9 CYCLEFORMAT bit field is equal to 0x3 and the DSS RFBI_CONFIGi 8 7 L4FORMAT bit field is equal to 0x0 an even number of write accesses to the data re...

Page 1767: ... 7 3 4 HSYNC Pulse Width Minimum Value The DSS RFBI_HSYNC_WIDTH 15 0 MINHSYNCPULSEWIDTH bit field defines the minimum number of L4 clock cycles of the HSYNC pulse for detection on HSYNC It allows differentiation between VSYNC and HSYNC which are ORed on the same signal and is also used in the VSYNC HSYNC mode on the separate two input lines The HSYNC pulse width must always be at least equal to tw...

Page 1768: ...Ei 20 WWENABLE bit Write to write access The DSS RFBI_CYCLE_TIMEi 18 RWENABLE bit Read to write access The DSS RFBI_CYCLE_TIMEi 21 WRENABLE bit Write to read access By default it applies to any access read to read read to write write to read write to write when the chip select changes Access time The total access time is the time from when A0 becomes valid until data are sampled before deasserting...

Page 1769: ... to 63 0 to 126 DSS RFBI_CYCLE_TIMEi 5 0 WECYCLETIME 0 to 63 0 to 126 DSS RFBI_ONOFF_TIMEi 13 10 WEONTIME 0 to 15 0 to 30 DSS RFBI_ONOFF_TIMEi 19 14 WEOFFTIME 0 to 63 0 to 126 DSS RFBI_CYCLE_TIMEi 11 6 RECYCLETIME 0 to 63 0 to 126 DSS RFBI_ONOFF_TIMEi 23 20 REONTIME 0 to 15 0 to 30 DSS RFBI_ONOFF_TIMEi 29 24 REOFFTIME 0 to 63 0 to 126 1 Where i 0 or 1 2 Number of L4Clk cycles The granularity can b...

Page 1770: ... 8 BUSY bit is set until the data are available in the register When the DSS RFBI_SYSSTATUS 8 BUSY bit is set by hardware the read or write access is stalled until the register is updated with a new value from the LCD panel To avoid the stall the software can poll the DSS RFBI_SYSSTATUS 8 BUSY bit until it is reset by hardware To receive the data send the appropriate command parameters 7 5 7 3 9 R...

Page 1771: ...le output Set DSS DISPC_CONTROL 0 LCDENABLE bit to 1 Enable the RFBI module output to update the remote frame buffer Set DSS RFBI_CONTROL 0 ENABLE bit to 1 No Yes Internal trigger mode used Enable internal software trigger Set DSS RFBI_CONTROL 4 ITE bit to 1 dss 192 Public Version www ti com Display Subsystem Basic Programming Model Figure 7 144 How to Use RFBI Figure 7 145 details how to configur...

Page 1772: ...HSYNC and VSYNC polarity VSYNC Set DSS RFBI_CONFIGi 20 TE_VSYNC_POLARITY HSYNC Set DSS RFBI_CONFIGi 21 HSYNCPOLARITY Program TE polarity Set DSS RFBI_CONFIGi 20 TE_VSYNC_POLARITY Program minimum pulse width Set DSS RFBI_VSYNC_WIDTH 15 0 MINVSYNCPULSEWIDTH Set DSS RFBI_HSYNC_WIDTH 15 0 MINHSYNCPULSEWIDTH Program parallel data widths Output data width Set DSS RFBI_CONFIGi 1 0 PARALLELMODE Input data...

Page 1773: ... Enable internal software trigger Set DSS RFBI _CONTROL 4 ITE bit to 1 End RFBI output enable dss 324 Public Version www ti com Display Subsystem Basic Programming Model Figure 7 146 RFBI Output Enable 7 5 8 Video Encoder Basic Programming Model 7 5 8 1 Video Encoder Software Reset By setting the DSS VENC_F_CONTROL 8 RESET bit to 1 the video encoder is reset This bit is automatically cleared by ha...

Page 1774: ...ale high full scale low full scale CONTROL CONTROL_ 0 Buffer Mode 0 Buffer mode 0 Buffer mode 1 Bypass mode DEVCONF1 18 TVOUTBYPASS CONTROL CONTROL_ 0 DC coupling 1 AC coupling 0 DC coupling 0 DC coupling DEVCONF1 11 TVACEN AVDAC1 CONTROL CONTROL_ 0 Don t care 0 Don t care 0 Don t care 0 Don t care AVDAC1 20 AVDAC1_COMP_EN CONTROL CONTROL_ 0 Single channel 0 Single channel 1 Dual channel 1 Dual ch...

Page 1775: ...ng values only for the TV display support NTSC 601 and PAL 601 standards Table 7 72 Video Encoder Register Programming Values Register Name NTSC 601 PAL 601 VENC_F_CONTROL 0x00000000 0x00000000 VENC_VIDOUT_CTRL 0x00000001 0x00000001 VENC_SYNC_CTRL 0x00008040 0x00000040 VENC_LLEN 0x00000359 0x0000035F VENC_FLENS 0x0000020C 0x00000270 VENC_HFLTR_CTRL 0x00000000 0x00000000 VENC_CC_CARR_WSS_CARR 0x043...

Page 1776: ... Y VENC_TVDETGP_INT_START_STOP_X 0x00140001 0x00140001 VENC_TVDETGP_INT_START_STOP_Y 0x00010001 0x00010001 VENC_GEN_CTRL 0x00F90000 0x00FF0000 VENC_OUTPUT_CONTROL 0x0000000A composite video CVBS 0x0000000A composite video CVBS 0x0000000D split video S video 0x0000000D split video S video VENC_OUTPUT_TEST 0x00000000 0x00000000 NOTE The following display controller registers must be programmed to th...

Page 1777: ... pixel format in system memory is not RGB the color space conversion unit in front of the scaling unit converts the YUV pixels into RGB pixels The two scaling units are independent Neither of them only one or both can be used simultaneously 7 6 1 1 Filtering The scaling is used to down scale up scale or process the image while keeping the same size It is applied independently horizontally and vert...

Page 1778: ...LTAPS 1 DISPC_VIDn_PICTURE_SIZE 10 0 VIDORGSIZEX 4 and even The programmable three coefficients of the poly phase filters are signed 8 bit values except for the central coefficient C0 which is unsigned The vertical filtering unit can be configured to support five taps The vertical 5 tap filtering macro architecture is shown in Figure 7 148 Figure 7 148 Vertical Filtering Macro Architecture Five Ta...

Page 1779: ... programmable The horizontal filtering macro architecture is shown in Figure 7 149 Figure 7 149 Horizontal Filtering Macro Architecture Five Taps For the 5 tap horizontal up downsampling the equation is with the example of R component 16 Legend Rout R component output Ci Vertical FIR coefficients Rin R component input The line n 1 is older than line n To horizontally and vertically filter the vide...

Page 1780: ...t s accu 512 inc 10 accu 512 10 Phase accu 9 7 7 ø ö ç ç è æ å p i p i i n R in C i n R out f Accu accu inc 1 New pixel on the same line 2 New pixel on following line no line to load 3 New pixel on following line line s to load 4 End of frame 5 Restart of a new frame 1 2 3 4 5 Public Version Display Subsystem Use Cases and Tips www ti com Figure 7 150 Vertical Up Down Sampling Algorithm Figure 7 1...

Page 1781: ... Figure 7 151 Horizontal Up Down Sampling Algorithm 7 6 1 3 Scaling Settings NOTE In this section the screen word refers to LCD panel or TV set n indicates pipeline 0 or 1 because there are two video pipelines in the DISPC 7 6 1 3 1 Register List The following registers define the scaling registers for the video layer n configuration DSS DISPC_VIDn_BAj DSS DISPC_VIDn_ATTRIBUTES DSS DISPC_VIDn_FIR ...

Page 1782: ... 15 8 VIDFIRVC0 VidFIRVC00 DSS DISPC_VIDn_FIR_COEF_Vi 7 0 VIDFIRVC00 Table 7 75 lists the registers for programming the horizontal FIR coefficients 5 tap configuration Table 7 75 Horizontal FIR Coefficients Corresponding Table 5 Tap Configuration CX VidFIRHCX C 2 VidFIRHC4 C 1 VidFIRHC3 C0 VidFIRHC2 C1 VidFIRHC1 C2 VidFIRHC0 The corresponding registers for programming the vertical FIR coefficients...

Page 1783: ...nge is 1 4096 The software calculates the value using the following equation 17 NOTE If the VIDFIRVINC 11 0 bit field value is greater than 4096 it is clipped to 4096 If VIDSIZEY 10 0 equals 0x1 VIDSIZEY 10 0 is replaced by 0x2 in the previous equation The VIDORGSIZEY 10 0 and VIDSIZEY 10 0 bit field values must be programmed with the value desired minus 1 Horizontal up downsampling increment valu...

Page 1784: ...sters for the eight phases with two coefficients for each of them so a total of 16 programmable coefficients for the vertical up downsampling block used in addition of the 3 tap registers defined above Each register contains two 8 bit signed coefficients C22 and C00 In case of 5 tap configuration both sets of registers DSS DISPC_VIDn_FIR_COEF_HVi and DSS DISPC_VIDn_FIR_COEF_V are used In case of 3...

Page 1785: ...tal Filter Coefficients Five Taps Phases VidFIRHC4 VidFIRHC3 VidFIRHC2 VidFIRHC1 VidFIRHC0 0 0 0 128 0 0 1 1 13 124 8 0 2 2 30 112 11 1 3 5 51 95 11 2 4 0 9 73 73 9 5 2 11 95 51 5 6 1 11 112 30 2 7 0 8 124 13 1 The upsampling coefficients register configuration vertical three taps and horizontal five taps is the following DSS DISPC_VIDn_FIR_COEF_H0 0x00800000 DSS DISPC_VIDn_FIR_COEF_HV0 0x00800000...

Page 1786: ...35FF5FE DSS DISPC_VIDn_FIR_COEF_HV3 0x335FF5FB DSS DISPC_VIDn_FIR_COEF_V3 0x0000FBFE DSS DISPC_VIDn_FIR_COEF_H4 0xF74949F7 DSS DISPC_VIDn_FIR_COEF_HV4 0xF7404000 DSS DISPC_VIDn_FIR_COEF_V04 0x000000F7 DSS DISPC_VIDn_FIR_COEF_H5 0xF55F33FB DSS DISPC_VIDn_FIR_COEF_HV5 0xF55F33FE DSS DISPC_VIDn_FIR_COEF_V5 0x0000FEFB DSS DISPC_VIDn_FIR_COEF_H6 0xF5701EFE DSS DISPC_VIDn_FIR_COEF_HV6 0xF5701EFF DSS DIS...

Page 1787: ... horizontal five taps is the following DSS DISPC_VIDn_FIR_COEF_H0 0x24382400 DSS DISPC_VIDn_FIR_COEF_HV0 0x24382400 DSS DISPC_VIDn_FIR_COEF_H1 0x28371FFE DSS DISPC_VIDn_FIR_COEF_HV1 0x28391F04 DSS DISPC_VIDn_FIR_COEF_H2 0x2C361BFB DSS DISPC_VIDn_FIR_COEF_HV2 0x2D381B08 DSS DISPC_VIDn_FIR_COEF_H3 0x303516F9 DSS DISPC_VIDn_FIR_COEF_HV3 0x3237170C DSS DISPC_VIDn_FIR_COEF_H4 0x11343311 DSS DISPC_VIDn_...

Page 1788: ...power domains and unused modules into idle mode This process can be expanded to include the screen saver mode in which the MPU subsystem wakes up to update the frame buffer and then returns to idle mode On the device platform where power consumption is of high importance the display modes must be configured properly to achieve optimal power savings The display low power refresh mode can be used in...

Page 1789: ...devices The LCD logic clock is determined by the DSS DISPC_DIVISOR 23 16 LCD bit field This divisor is used on the DSS functional clock that is selected in the DSS_CONTROL register either DSS1_ALWON_FCLK or DSS2_ALWON_FCLK This LCD divisor selects the logical clock frequency which is used to clock the logic in the display subsystem For some applications there is a required minimum logical clock fr...

Page 1790: ...setting DSS DISPC_DIVISOR 23 16 LCD to 0x2 and DSS DISPC_DIVISOR 7 0 PCD to 0x4 7 6 2 2 2 Display Subsystem Clock Enable To take the DSS out of reset all DSS related clocks must be enabled and the DPLL4 clock must be enabled After taking the DSS out of reset these clocks can be disabled if they are not used The following clocks must be enabled before the DSS can come out of reset PRCM CM_FCLKEN_DS...

Page 1791: ...s to further save power consumption Display subsystem DSS DSS_SYSCONFIG 4 3 SIDLEMODE Display controller DSS DISPC_SYSCONFIG 4 3 SIDLEMODE RFBI DSS RFBI_SYSCONFIG 4 3 SIDLEMODE 7 6 2 5 FIFO Thresholds The display subsystem internal FIFO is used to move data to the LCD panel This FIFO is filled by the display subsystem DMA controller The DMA controller is triggered to start and stop based on two th...

Page 1792: ...laying the data transfer if the data is not ready because of bandwidth limitations Care must be taken to determine the fps when modifying these parameters Use the following formula to determine the fps for a 240 x 320 QVGA LCD 22 With Hsw DSS DISPC_TIMING_H 7 0 HSW bit field value Hfp DSS DISPC_TIMING_H 19 8 HFP bit field value Hbp DSS DISPC_TIMING_H 31 20 HBP bit field value Vsw DSS DISPC_TIMING_...

Page 1793: ...mall a FIFO underflow may occur 7 6 3 How to Configure the DSI PLL in Video Mode Figure 7 153 shows a global overview of the DSI clock tree when used in video mode Figure 7 153 DSI Clock Tree in Video Mode The settings of the DSI PLL registers can be summarized by the following equations Equation 1 24 where T L THS HSADSI THE HFPDSI WC 6 NDL HBPDSI N is an integer NDL Number of data lane WC Word c...

Page 1794: ...rmat Ratio R 1 16 bits pixel 1 2 1 18 bits pixel 4 9 1 24 bits pixel 1 3 2 16 bits pixel 1 2 18 bits pixel 8 9 2 24 bits pixel 2 3 All cases are covered by Equation 3 26 Equation 4 27 Example The desired performances are Clock lane at 150 MHz RGB24 888 1 data lane LCD size 480 640 with HSA_DISP HFP_DISP HBP_DISP 20 VSA_DISP VFP_DISP VBP_DISP 2 Step 1 Determine REGM and REGN To obtain correct stabi...

Page 1795: ...e DISPC Video Port This section details the basic programming model of video mode using the DISPC video port The DSI interface is connected to an external MIPI display controller and the following parameters are used 1 data lane NDL 1 Clock lane at 150 MHz DSI_DDR_CLK LCD size is 640 x 480 480 pixels per line PPL 680 lines per panel LPP Display controller input format YUV Display controller output...

Page 1796: ...teps listed in Table 7 84 are described in the following sections Table 7 84 Main Steps Steps Section Configure DSS clocks Section 7 6 4 1 Display Subsystem Clock Configuration Configure the DSI and DSI PLL Section 7 6 4 2 Configure DSI DSI PLL and Complex I O Configure the external MIPI display controller Section 7 6 4 3 Initialization of the External MIPI Display Controller Configure the DISPC S...

Page 1797: ...egisters Value Turn on PLL and HSDIVIDER DSI_CLK_CTRL 31 30 PLL_PWR_CTRL 0x2 Wait until PLL_PWR_STATUS 0x2 DSI_CLK_CTRL 29 28 PLL_PWR_STATUS Read 0x2 DSI_PLL_CONFIGURATION1 26 23 See the calculation following this table 5 DSIPROTO_CLK_DIV DSI_PLL_CONFIGURATION1 22 19 See the calculation following this table 15 DSS_CLOCK_DIV DSI_PLL_CONFIGURATION1 18 8 See the calculation following this table 150 D...

Page 1798: ...89 lists the steps to set up the DSI complex I O registers Table 7 88 DSI Control Registers Steps Registers Value Enable SYNCLOST event DSI_IRQENABLE 31 0 0x4 0000 Set PACKET_SENT_IRQ_EN DSI_VC0_IRQENABLE 31 0 0x4 While the HSYNC START pulse is detected the associated short DSI_CTRL 17 VP_HSYNC_START 0x1 packet HSYNC START is generated While the VSYNC START pulse is detected the associated short D...

Page 1799: ...US Read 0x1 Reset is complete DSI_SYSSTATUS 0 RESETDONE Read 0x1 7 6 4 2 4 2 Configure DSI Timing and Virtual Channels Table 7 90 lists the steps to configure DSI timing and the virtual channels Table 7 90 DSI Timing Registers Steps Registers Value STOP_STATE_COUNTER_IO 0x999 DSI_TIMING1 31 0 0x0000 0999 HS_TX_TO_X8 HS_TX_TO_COUNTER 0x0FD2 DSI_TIMING2 31 0 0x2FD2 40CD LP_RX_TO_X16 LP_RX_TO_COUNTER...

Page 1800: ...GISTER0 23 16 ceil 175 ns DDR clock period 2 REG_THSPRPR_THSZERO DSI_PHY_REGISTER0 7 0 REG_THSEXIT ceil 145 ns DDR clock period DSI_PHY_REGISTER0 15 8 REG_THSTRAIL ceil 60 ns DDR clock period 5 DSI_PHY_REGISTER2 7 0 REG_TCLKPREPARE ceil 65 ns DDR clock period DSI_PHY_REGISTER1 7 0 REG_TCLKZERO ceil 265 ns DDR clock period DSI_PHY_REGISTER1 15 8 REG_TCLKTRAIL ceil 60 ns DDR clock period 2 DSI_PHY_R...

Page 1801: ...FP 16 PPL 1 Set default RGB value when there is no DISPC_DEFAULT_COLOR0 0XFF data Set video FIFO height and low threshold DISPC_VID1_FIFO_THRESHOLD 0xfc00c0 Set the X Y location of the upper left pixel 0 DISPC_VID1_POSITION 0x0 0 to the upper left corner Set size of the window DISPC_VID1_SIZE LPP 1 16 PPL 1 Set the size of the picture DISPC_VID1_PICTURE_SIZE LPP 1 16 PPL 1 Set the input address pi...

Page 1802: ...le Video Mode Using the DISPC Video Port Table 7 98 lists the steps to enable DISPC to send frames continuously Table 7 98 Enable DISPC Steps Registers Value Set up long packet header DSI_VC0_LONG_PACKET_HEADER 31 0 0x0005 A03E Enable VC0 DSI_VC0_CTRL 1 VC_EN 0x1 Enable IF DSI_CTRL 0 IF_EN 0x1 Wait until IF_EN 0 DSI_CTRL 0 IF_EN Read 0x0 Enable VID1 DISPC_VID1_ATTRIBUTES 0 VIDENABLE 0x1 Enable LCD...

Page 1803: ...l DISPC and virtual channel 0 VC0 used to send data Automatic TE used for synchronization Interleaving not used It is assumed that all modules used in these programming models are in after POR state Figure 7 155 is an overview of the connections in the display subsystem Figure 7 155 Overview Table 7 99 lists the steps of the main sequence and the sections that describe them Table 7 99 Main Sequenc...

Page 1804: ...0 EN_DSS 0x1 DSS_L4_ICLK interface clocks 1 TV_CLK is required only for a correct reset 7 6 5 1 2 Configure DSI Protocol Engine DSI PLL and Complex I O Table 7 101 lists the steps to configure the DSI protocol engine DSI PLL and complex I O and the sections that describe the sequence Table 7 101 Configure DSI Protocol Engine DSI PLL and Complex I O Steps Register Bit Field Programming Model Reset ...

Page 1805: ...LKIN4DDR control DSI_PLL_CONFIGURATION2 14 DSI_PHY_CLKINEN 0x1 Enable DSS clock divider DSI_PLL_CONFIGURATION2 16 DSS_CLOCK_EN 0x1 DSI_PLL_CONFIGURATION2 18 Enable DSI protocol engine clock divider 0x1 DSI_PROTO_CLOCK_EN Enable DSI configuration update with DSI_PLL_CONTROL 0 DSI_PLL_AUTOMODE 0x0 DISPC_UPDATE_SYNC Start PLL locking sequence DSI_PLL_GO 0 DSI_PLL_GO 0x1 Wait until DSI_PLL_GO 0 DSI_PL...

Page 1806: ...N 0x1 Enable IRQ to indicate that packet has been DSI_VC1_IRQENABLE 2 PACKET_SENT_IRQ 0x1 sent on VC1 Enable IRQ to indicate that packet has been DSI_VC0_IRQENABLE 2 PACKET_SENT_IRQ 0x1 sent on VC0 Set the trigger reset mode to immediate DSI_CTRL 14 TRIGGER_RESET_MODE 0x1 Activate the two line buffers DSI_CTRL 13 12 LINE_BUFFER 0x2 Set the size of the video port data bus to 24 DSI_CTRL 7 6 VP_DATA...

Page 1807: ...turn around timer settings DSI_TIMING1 30 16 0x0000 Determine the number of DSI_FCLK clock DSI_TIMING2 12 0 LP_RX_TO_COUNTER 0x0CD cycles for the LP RX timer Disable the multiplication factor of 4 for the number of DSI_FCLK clock cycles for the LP DSI_TIMING2 13 LP_RX_TO_X4 0x0 RX timer Enable the multiplication factor of 16 for the number of DSI_FCLK clock cycles for the LP DSI_TIMING2 14 LP_RX_T...

Page 1808: ...uration TX and RX FIFO Set size of the RX FIFO allocated for VC1 to DSI_RX_FIFO_VC_SIZE 15 12 0x1 32 x 33 bits VC1_FIFO_SIZE Set size of the TX and TX FIFO allocated for DSI_TX_FIFO_VC_SIZE 15 12 0x3 VC1 to 96 x 33 bits VC1_FIFO_SIZE Freq TxByteClkHS Length of the line in video mode in number of byte clock cycles TxByteClkHS Blanking periods HBP HFP in DSI are calculated based on the following for...

Page 1809: ...ler Table 7 110 Initialization of the External MIPI LCD Controller Steps Register Bit Field Programming Value Reset the MIPI LCD controller using 0x1 GPIO87 Wait until initialization of the external MIPI LCD controller is finished after power up Configure the external MIPI LCD controller 7 6 5 1 4 Configure the DISPC 7 6 5 1 4 1 Reset DISPC Table 7 111 lists the steps to reset the DISPC Table 7 11...

Page 1810: ...KFREEENABLE 0x1 DISPC_CONTROL 16 GPOUT1 0x1 Disable RFBI DISPC_CONTROL 15 GPOUT0 0x1 Enable the stall mode DISPC_CONTROL 11 STALLMODE 0x1 Select size of DATALINES DISPC_CONTROL 9 8 TFTDATALINES 0x3 Select active matrix display operation mode DISPC_CONTROL 3 STNTFT 0x1 Disable LCD output interface DISPC_CONTROL 0 LCDENABLE 0x0 Update the internal DISPC registers DISPC_CONTROL 5 GOLCD 0x1 7 6 5 1 5 ...

Page 1811: ...A to give bus possession to DSI_VC1_CTRL 6 BTA_EN 0x1 the display module Wait until BTA IRQ DSI_VC1_IRQSTATUS 5 BTA_IRQ 0x1 Write 1 to clear BTA IRQ DSI_VC1_IRQSTATUS 5 BTA_IRQ 0x1 Enable second BTA to get the TE trigger DSI_VC1_CTRL 6 BTA_EN 0x1 Wait until BTA IRQ DSI_VC1_IRQSTATUS 5 BTA_IRQ 0x1 Write 1 to clear BTA IRQ DSI_VC1_IRQSTATUS 5 BTA_IRQ 0x1 Wait until transfer is complete DSI_VC0_TE 30...

Page 1812: ...0014 DSS_IRQSTATUS R 32 0x018 0x4805 0018 DSS_CONTROL RW 32 0x040 0x4805 0040 DSS_CLK_STATUS R 32 0x05C 0x4805 005C 7 7 1 2 Display Controller Register Mapping Summary Table 7 118 Display Controller Register Mapping Summary Register Name Type Register Width Address Offset Physical Address Bits DISPC_REVISION R 32 0x000 0x4805 0400 DISPC_SYSCONFIG RW 32 0x010 0x4805 0410 DISPC_SYSSTATUS R 32 0x014 ...

Page 1813: ...ontroller VID1 Register Mapping Summary Table 7 119 Display Controller VID1 Register Mapping Summary Register Name n 1 for VID1 Type Register Width Address Offset Display controller VID1 Bits Physical Address DISPC_VIDn_BAj RW 32 0x0BC n 1 0x90 0x4805 04BC j j 0x04 1 0x04 1 DISPC_VIDn_POSITION RW 32 0x0C4 n 1 0x90 0x4805 04C4 DISPC_VIDn_SIZE RW 32 0x0C8 n 1 0x90 0x4805 04C8 DISPC_VIDn_ATTRIBUTES R...

Page 1814: ...IFO_SIZE_STATUS R 32 0x0D4 n 1 0x90 0x4805 0564 DISPC_VIDn_ROW_INC RW 32 0x0D8 n 1 0x90 0x4805 0568 DISPC_VIDn_PIXEL_INC RW 32 0x0DC n 1 0x90 0x4805 056C DISPC_VIDn_FIR RW 32 0x0E0 n 1 0x90 0x4805 0570 DISPC_VIDn_PICTURE_SIZE RW 32 0x0E4 n 1 0x90 0x4805 0574 DISPC_VIDn_ACCUl RW 32 0x0E8 n 1 0x90 0x4805 0578 l 0x04 2 l 0x04 2 DISPC_VIDn_FIR_COEF_Hi RW 32 0x0F0 n 1 0x90 0x4805 0580 i 0x08 3 i 0x08 3...

Page 1815: ... 1 i 0 to 1 2 i 0 to 1 7 7 1 6 Video Encoder Register Mapping Summary Table 7 122 Video Encoder Register Mapping Summary Register Name Type Register Width Address Offset Physical Address Bits VENC_REV_ID R 32 0x00 0x4805 0C00 VENC_STATUS R 32 0x04 0x4805 0C04 VENC_F_CONTROL RW 32 0x08 0x4805 0C08 VENC_VIDOUT_CTRL RW 32 0x10 0x4805 0C10 VENC_SYNC_CTRL RW 32 0x14 0x4805 0C14 VENC_LLEN RW 32 0x1C 0x4...

Page 1816: ...C_TVDETGP_INT_START_STOP_X RW 32 0xB0 0x4805 0CB0 VENC_TVDETGP_INT_START_STOP_Y RW 32 0xB4 0x4805 0CB4 VENC_GEN_CTRL RW 32 0xB8 0x4805 0CB8 VENC_OUTPUT_CONTROL RW 32 0xC4 0x4805 0CC4 VENC_OUTPUT_TEST RW 32 0xC8 0x4805 0CC8 7 7 1 7 DSI Protocol Engine Register Mapping Summary Table 7 123 DSI Protocol Engine Register Mapping Summary Register Name Type Register Width Bits Address Offset Physical Addr...

Page 1817: ...VCn_IRQSTATUS RW 32 0x118 n 0x20 1 0x4804 FD18 n 0x20 1 DSI_VCn_IRQENABLE RW 32 0x11C n 0x20 1 0x4804 FD1C n 0x20 1 1 n 0 to 3 7 7 1 8 DSI_PHY Register Mapping Summary Table 7 124 DSI_PHY Register Mapping Summary Register Name Type Register Width Bits Address Offset Physical Address DSI_PHY_REGISTER0 RW 32 0x0000 0000 0x4804 FE00 DSI_PHY_REGISTER1 RW 32 0x0000 0004 0x4804 FE04 DSI_PHY_REGISTER2 RW...

Page 1818: ...ddress 0x4805 0010 Instance DISS Description This register controls the various parameters of the interconnect interface Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Reserved AUTOIDLE SOFTRESET Bits Field Name Description Type Reset 31 5 Reserved Write 0s for future compatibility Reads return zero RW 0x00000000 4 3 Reserved Reserve...

Page 1819: ...ETDONE Bits Field Name Description Type Reset 31 1 Reserved Read returns 0 R 0x00000000 0 RESETDONE Internal reset monitoring R 1 Read 0x0 Internal module reset is ongoing Read 0x1 Reset completed Table 7 131 Register Call Summary for Register DSS_SYSSTATUS Display Subsystem Integration Software Reset 0 Display Subsystem Basic Programming Model Display Subsystem Reset 1 Display Subsystem Register ...

Page 1820: ..._BGZ VENC_CLOCK_4X_ ENABLE Bits Field Name Description Type Reset 31 7 Reserved Reserved for future DAC use RW 0x0000000 6 VENC_OUT_SEL Video DAC1 input selection RW 0 0x0 CVBS VENC output selected for composite video mode 0x1 Luminance VENC output selected for s video mode 5 DAC_POWERDN_BGZ DAC Power Down Control RW 0 0x0 DAC Power Down Band Gap powered down 0x1 DAC Power Down Band Gap powered up...

Page 1821: ...ttings 15 Display Subsystem Use Cases and Tips Display Subsystem Clock Configuration 16 17 18 DPLL4 in Low Power Mode 19 20 Switch to DSI PLL Clock Source 21 Switch to DSI PLL Clock Source 22 23 Display Subsystem Register Manual Display Subsystem Register Mapping Summary 24 Table 7 136 DSS_CLK_STATUS Address Offset 0x05C Physical address 0x4805 005C Instance DISS Description This register contains...

Page 1822: ...DISPC Table 7 137 Register Call Summary for Register DSS_CLK_STATUS Display Subsystem Register Manual Display Subsystem Register Mapping Summary 0 7 7 2 2 Display Controller Registers Table 7 138 DISPC_REVISION Address Offset 0x000 Physical address 0x4805 0400 Instance DISC Description This register contains the IP revision code Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 1823: ... period 0x2 Interface clocks can be switched off and functional clocks are maintained during wakeup period 0x3 Interface and functional clocks are maintained during wakeup period 7 5 Reserved Write 0s for future compatibility Read returns 0 RW 0x0 4 3 SIDLEMODE Slave interface power management idle req ack control RW 0x0 0x0 Force idle An idle request is acknowledged unconditionally 0x1 No idle An...

Page 1824: ...cription This register provides status information about the module excluding interrupt status information Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved RESETDONE Bits Field Name Description Type Reset 31 8 Reserved Write 0s for future compatibility Read returns 0 R 0x000000 7 1 Reserved Reserved Read returns 0 R 0x00 0 RESETDONE Int...

Page 1825: ...1 Wakeup status bit reset 15 SYNCLOSTDIGITAL SyncLostDigital RW 0 Read 0x0 SyncLostDigital is false Write 0x0 SyncLostDigital status bit unchanged Read 0x1 SyncLostDigital is true pending Write 0x1 SyncLostDigital status bit reset 14 SYNCLOST SyncLost RW 0 Read 0x0 SyncLost is false Write 0x0 SyncLost status bit unchanged Read 0x1 SyncLost is true pending Write 0x1 SyncLost status bit reset 13 VID...

Page 1826: ...fxFIFOUnderflow RW 0 Read 0x0 GfxFIFOUnderflow is false Write 0x0 GfxFIFOUnderflow status bit unchanged Read 0x1 GfxFIFOUnderflow is true pending Write 0x1 GfxFIFOUnderflow status bit reset 5 PROGRAMMEDLINE ProgrammedLineNumber RW 0 NUMBER Read 0x0 ProgrammedLineNumber is false Write 0x0 ProgrammedLineNumber status bit unchanged Read 0x1 ProgrammedLineNumber is true pending Write 0x1 ProgrammedLin...

Page 1827: ...ress 0x4805 041C Instance DISC Description This register allows the masking unmasking of module internal interrupt sources on an event by event basis Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VSYNC WAKEUP SYNCLOST OCPERROR FRAMEMASK EVSYNC_ODD EVSYNC_EVEN GFXENDWINDOW VID2ENDWINDOW ENDVID1WINDOW SYNCLOSTDIGITAL GFXFIFOUNDERFLOW VID2FIFOU...

Page 1828: ...NDWINDOW GfxEndWindow RW 0 0x0 GfxEndWindow is masked 0x1 GfxEndWindow generates an interrupt when it occurs 6 GFXFIFOUNDERFLOW GfxFIFOUnderflow RW 0 0x0 GfxFIFOUnderflow is masked 0x1 GfxFIFOUnderflow generates an interrupt when it occurs 5 PROGRAMMEDLINE ProgrammedLineNumber RW 0 NUMBER 0x0 ProgrammedLineNumber is masked 0x1 ProgrammedLineNumber generates an interrupt when it occurs 4 ACBIASCOUN...

Page 1829: ...T1 GPOUT0 Reserved GODIGITAL LCDENABLE STALLMODE TDMENABLE MONOCOLOR TFTDATALINES DIGITALENABLE LCDENABLEPOL TDMUNUSEDBITS PCKFREEENABLE STDITHERENABLE LCDENABLESIGNAL TDMCYCLEFORMAT TDMPARALLELMODE OVERLAYOPTIMIZATION SPATIALTEMPORALDITHERINGFRAMES Bits Field Name Description Type Reset 31 30 SPATIALTEMPORAL Spatial Temporal dithering number of frames RW 0x0 DITHERINGFRAMES wr VFP 0x0 Spatial onl...

Page 1830: ...oded value from 0 to 7 holds time for digital output The data will be held for HT 1 external digital clock periods 16 GPOUT1 General Purpose Output Signal RW 0 0x0 The GPout1 is reset 0x1 The GPout1 is set 15 GPOUT0 General Purpose Output Signal RW 0 0x0 The GPout0 is reset 0x1 The GPout0 is set 14 GPIN1 General Purpose Input Signal R 0 WR VFP Read The GPin1 has been reset 0x0 Read The GPin1 has b...

Page 1831: ...ng the shadow registers of the pipeline s associated with the digital output and the hardware can update the internal registers at the external VSYNC 5 GOLCD LCD GO Command RW 0 0x0 The hardware has finished updating the internal shadow registers of the pipeline s connected to the LCD output using the user values The hardware resets the bit when the update is completed 0x1 Users have finished prog...

Page 1832: ...tes 22 Video DMA Registers 23 Video Configuration Register 24 25 Video Up Down Sampling Configuration 26 27 DMA Register Settings 28 LCD Specific Control Registers 29 30 LCD Attributes 31 32 33 34 LCD Timings 35 36 37 LCD Overlay 38 39 40 LCD TDM 41 42 43 44 45 46 47 LCD Spatial Temporal Dithering 48 49 50 51 52 LCD Color Phase Rotation 53 54 55 TV Set Specific Control Registers 56 57 58 59 Digita...

Page 1833: ...IFO are refilled only when the LOW threshold is RW 0 reached or if all FIFO are refilled when at least one of them reaches the LOW threshold 0x0 Each FIFO is refilled when it reaches LOW threshold 0x1 All FIFOs are refilled up to high threshold when at least one of them reaches the LOW threshold only active FIFOs should be considered and when reaching the end of the frame the FIFO goes to empty co...

Page 1834: ... Transparency color key enabled LCD output RW 0 WR VFP 0x0 Disable the transparency color key for the LCD 0x1 Enable the transparency color key for the LCD 9 FUNCGATED Functional clocks gated enabled RW 0 WR immediate 0x0 Functional clocks gated disabled 0x1 Functional clocks gated enabled 8 ACBIASGATED ACBias Gated Enabled RW 0 WR VFP 0x0 AcBias Gated Disabled 0x1 AcBias Gated Enabled 7 VSYNCGATE...

Page 1835: ...play only in Active Matrix mode Table 7 151 Register Call Summary for Register DISPC_CONFIG Display Subsystem Environment Transaction Timing Diagrams 0 Display Subsystem Integration Autoidle Mode 1 Wake Up Mode 2 Display Subsystem Functional Description Normal Mode 3 4 5 6 7 8 9 10 Alpha Mode 11 12 13 14 Display Subsystem Basic Programming Model Display Controller Basic Programming Model 15 Graphi...

Page 1836: ...Specific Control Registers 2 LCD Overlay 3 TV Set Specific Control Registers 4 Digital Overlay 5 Display Subsystem Register Manual Display Controller Register Mapping Summary 6 Table 7 154 DISPC_TRANS_COLOR_m Address Offset 0x054 m 0x04 Index m 0 to 1 Physical address 0x4805 0454 m 0x04 Instance DISPC Description The register sets the transparency color value for the video graphics overlays for th...

Page 1837: ... incremented Table 7 157 Register Call Summary for Register DISPC_LINE_STATUS Display Subsystem Register Manual Display Controller Register Mapping Summary 0 Table 7 158 DISPC_LINE_NUMBER Address Offset 0x060 Physical address 0x4805 0460 Instance DISC Description The control register indicates the LCD panel display line number for the interrupt and the DMA request Shadow register updated on VFP st...

Page 1838: ...on before line clock is asserted program to value minus 1 7 0 HSW Horizontal synchronization pulse width RW 0x00 Encoded value from 1 to 256 to specify the number of pixel clock periods to pulse the line clock at the end of each line program to value minus 1 Table 7 161 Register Call Summary for Register DISPC_TIMING_H Display Subsystem Environment Transaction Timing Diagrams 0 1 2 Display Subsyst...

Page 1839: ...troller Basic Programming Model 3 LCD Specific Control Registers 4 LCD Timings 5 6 7 8 9 10 Display Subsystem Use Cases and Tips Vertical and Horizontal Timings 11 12 13 Configure DISPC Timing Window and Color 14 Display Subsystem Register Manual Display Controller Register Mapping Summary 15 Table 7 164 DISPC_POL_FREQ Address Offset 0x06C Physical address 0x4805 046C Instance DISC Description The...

Page 1840: ...8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Video Port VP Interface 30 Display Subsystem Basic Programming Model Display Controller Basic Programming Model 31 LCD Specific Control Registers 32 LCD Timings 33 34 35 36 37 38 39 40 Display Subsystem Register Manual Display Controller Register Mapping Summary 41 Table 7 166 DISPC_DIVISOR Address Offset 0x070 Physical address 0x4805...

Page 1841: ...ics and video 2 pipelines Shadow register updated on VFP start period or EVSYNC for each bit field depending on the association of the each pipeline with the LCD or TV output Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VID2GLOBALALPHA RESERVED GFXGLOBALALPHA Bits Field Name Description Type Reset 31 24 RESERVED Write 0s for future compatib...

Page 1842: ...Call Summary for Register DISPC_SIZE_DIG Display Subsystem Functional Description Up Down Sampling 0 Display Subsystem Basic Programming Model Display Controller Basic Programming Model 1 TV Set Specific Control Registers 2 Digital Frame Field Size 3 4 Video Encoder Register Settings 5 6 Display Subsystem Register Manual Display Controller Register Mapping Summary 7 Table 7 172 DISPC_SIZE_LCD Addr...

Page 1843: ...ry 12 Table 7 174 DISPC_GFX_BAj Address Offset 0x080 j 0x04 Index j 0 to 1 Physical address 0x4805 0480 j 0x04 Instance DISC Description The register configures the base address of the graphics buffer displayed in the graphics window 0 1 for ping pong mechanism with external trigger based on the field polarity 0 only used when graphics pipeline on the LCD output and 0 1 when on the 24 bit digital ...

Page 1844: ...ay Subsystem Basic Programming Model Display Controller Basic Programming Model 0 Graphics Layer Configuration Registers 1 Graphics Window Attributes 2 3 Rotation Mirroring Registers 4 Display Subsystem Register Manual Display Controller Register Mapping Summary 5 Table 7 178 DISPC_GFX_SIZE Address Offset 0x08C Physical address 0x4805 048C Instance DISC Description The register configures the size...

Page 1845: ...data as RW 0 pre multiplied alpha data or non premultiplied alpha data Default setting is non pre multiplied alpha data 0x0 Non pre multiplyalpha data color component 0x1 Pre multiplyalpha data color component NOTE The pre multiplied alpha option is only valid when bit field 4 1 GFXFORMAT is set to ARGB or RGBA formats Otherwise the PREMULTIPLYALPHA bit field is ignored by the hardware 27 16 Reser...

Page 1846: ...ELOUT Graphics Channel Out configuration RW 0 wr immediate 0x0 LCD output selected 0x1 24 bit output selected 7 6 GFXBURSTSIZE Graphics DMA Burst Size RW 0x0 0x0 4x32bit bursts 0x1 8x32bit bursts 0x2 16x32bit bursts 0x3 Reserved 5 GFXREPLICATION GfxReplicationEnable RW 0 ENABLE 0x0 Disable Graphics replication logic 0x1 Enable Graphics replication logic 4 1 GFXFORMAT Graphics format Other enums Re...

Page 1847: ...Type Reset 31 28 Reserved Write 0s for future compatibility Read returns 0 RW 0x00 27 16 GFXFIFOHIGH Graphics FIFO High Threshold RW 0x3FF THRESHOLD Number of bytes defining the threshold value 15 12 Reserved Write 0s for future compatibility Read returns 0 RW 0x00 11 0 GFXFIFOLOW Graphics FIFO Low Threshold RW 0x3C0 THRESHOLD Number of bytes defining the threshold value Table 7 183 Register Call ...

Page 1848: ...00001 Encoded signed value from 231 1 to 231 to specify the number of bytes to increment at the end of the row in the graphics buffer The value 0 is invalid The value 1 means next pixel The value 1 n BPP means increment of n pixels The value 1 n 1 BPP means decrement of n pixels Table 7 187 Register Call Summary for Register DISPC_GFX_ROW_INC Display Subsystem Basic Programming Model Display Contr...

Page 1849: ...ysical address 0x4805 04B4 Instance DISC Description The register configures the number of bytes to skip during video window display Shadow register updated on VFP start period or EVSYNC Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GFXWINDOWSKIP Bits Field Name Description Type Reset 31 0 GFXWINDOWSKIP Number of bytes to skip during video window 1 R...

Page 1850: ...r VID1 or 2 for VID2 j 0 to 1 Physical address 0x4805 04BC n 1 0x90 j Instance DISC 0x04 Description The register configures the base address of the video buffer for video window n j for ping pong mechanism with external trigger based on the field polarity 0 for even field and 1 for odd field Shadow register updated on VFP start period or EVSYNC Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 1851: ...ramming Model Display Controller Basic Programming Model 0 Video Configuration Register 1 Video Window Attributes 2 3 Rotation Mirroring Registers 4 Display Subsystem Register Manual Display Controller VID1 Register Mapping Summary 5 Display Controller VID2 Register Mapping Summary 6 Table 7 198 DISPC_VIDn_SIZE Address Offset 0x0C8 1 0x90 Index n 1 for VID1 or 2 for VID2 Physical address 0x4805 04...

Page 1852: ...DDMAOPTIMIZATION VIDROWREPEATENABLE VIDCOLORCONVENABLE VIDREPLICATIONENABLE Bits Field Name Description Type Reset 31 29 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0000 28 PREMULTIPLYALPHA The field configures the DISPC VID2 to process incoming data as RW 0 pre multiplied alpha data or non pre multiplied alpha data Default setting is non pre multiplied alpha data 0x0 Non pre mu...

Page 1853: ...ixels for each 32 bit OCP request RGB16 and YUV422 while doing 90 and 270 degree rotation accessing on chip memory and off chip memory The bit field 21 VIDVERTICALTAPS shall be set to 0x1 bit field 22 VIDLINEBUFFERSPLIT to 0x1 and all scaler registers shall be configured even for 1 1 ratio Even width is required for the input picture when 5 taps are used 19 VIDFIFOPRELOAD Video preload value RW 0 ...

Page 1854: ...processing 0x2 Enable the vertical resize processing 0x3 Enable both horizontal and vertical resize processing 4 1 VIDFORMAT Video1 channel Format Other enums Reserved all other values RW 0x0 Video 1 channel between 0x0 and 0x3 0x5 0x7 and between 0xC and 0xF 0x4 RGB12 16 bit container 0x6 RGB 16 0x8 RGB 24 unpacked in 32 bit container 0x9 RGB 24 packed in24 bit container 0xA YUV2 4 2 2 co sited 0...

Page 1855: ... for VID2 Physical address 0x4805 04D0 1 0x90 Instance DISC Description The register configures the video FIFO associated with video pipeline n Shadow register updated on VFP start period or EVSYNC Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VIDFIFOHIGHTHRESHOLD Reserved VIDFIFOLOWTHRESHOLD Bits Field Name Description Type Reset 31 28 Rese...

Page 1856: ...configures the number of bytes to increment at the end of the row for the buffer associated with video window n Shadow register updated on VFP start period or EVSYNC Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VIDROWINC Bits Field Name Description Type Reset 31 0 VIDROWINC Number of bytes to increment at the end of the row RW 0x00000001 Encoded sig...

Page 1857: ... Model 0 Video DMA Registers 1 Rotation Mirroring Registers 2 DMA Register Settings 3 4 Display Subsystem Register Manual Display Controller VID1 Register Mapping Summary 5 Display Controller VID2 Register Mapping Summary 6 Table 7 210 DISPC_VIDn_FIR Address Offset 0x0E0 1 0x90 Index n 1 for VID1 or 2 for VID2 Physical address 0x4805 04E0 1 0x90 Instance DISC Description The register configures th...

Page 1858: ...program to value minus one 15 11 Reserved Write 0s for future compatibility RW 0x00 Read returns 0 10 0 VIDORGSIZEX Number of pixels of the video picture RW 0x000 Encoded value from 1 to 2048 to specify the number of pixels of the video picture in memory program to value minus one The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is process...

Page 1859: ...odel 0 Video Up Down Sampling Configuration 1 2 Display Subsystem Use Cases and Tips Register List 3 Initial Phase 4 5 Display Subsystem Register Manual Display Controller VID1 Register Mapping Summary 6 Display Controller VID2 Register Mapping Summary 7 Table 7 216 DISPC_VIDn_FIR_COEF_Hi Address Offset 0x0F0 1 0x90 i 0x08 Index n 1 for VID1 or 2 for VID2 i 0 to 7 Physical address 0x4805 04F0 n 1 ...

Page 1860: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VIDFIRVC2 VIDFIRVC1 VIDFIRVC0 VIDFIRHC4 Bits Field Name Description Type Reset 31 24 VIDFIRVC2 Signed coefficient C2 for the vertical up down scaling with the phase n RW 0x00 23 16 VIDFIRVC1 Unsigned coefficient C1 for the vertical up down scaling with the phase n RW 0x00 15 8 VIDFIRVC0 Signed coefficient C0 for ...

Page 1861: ...ystem Basic Programming Model Rotation Mirroring Registers 0 1 Video DMA Optimization 2 Display Subsystem Register Manual Display Controller VID1 Register Mapping Summary 3 Display Controller VID2 Register Mapping Summary 4 Table 7 222 DISPC_VIDn_CONV_COEF1 Address Offset 0x134 1 0x90 Index n 1 for VID1 or 2 for VID2 Physical address 0x4805 0534 1 0x90 Instance DISC Description The register config...

Page 1862: ...10 0 GCR GCr Coefficient RW 0x000 Encoded signed value from 1024 to 1023 Table 7 225 Register Call Summary for Register DISPC_VIDn_CONV_COEF2 Display Subsystem Basic Programming Model Rotation Mirroring Registers 0 Display Subsystem Register Manual Display Controller VID1 Register Mapping Summary 1 Display Controller VID2 Register Mapping Summary 2 Table 7 226 DISPC_VIDn_CONV_COEF3 Address Offset ...

Page 1863: ...ue from 1024 to 1023 Table 7 229 Register Call Summary for Register DISPC_VIDn_CONV_COEF4 Display Subsystem Basic Programming Model Rotation Mirroring Registers 0 1 Video DMA Optimization 2 Display Subsystem Register Manual Display Controller VID1 Register Mapping Summary 3 Display Controller VID2 Register Mapping Summary 4 Table 7 230 DISPC_DATA_CYCLEk Address Offset 0x1D4 k 0x04 Index k 0 to 2 P...

Page 1864: ...ndex n 1 for VID1 or 2 for VID2 0x04 i 0 to 7 Physical address 0x4805 05E0 n 1 0x20 Instance DISC i 0x04 Description This bank of registers configures the down up down scaling coefficients for the vertical resize of the video picture associated with video window n for phases 0 to 7 Shadow register updated on VFP start period or EVSYNC Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1...

Page 1865: ...ystem Basic Programming Model Display Controller Basic Programming Model 0 LCD Specific Control Registers 1 LCD Color Phase Rotation 2 3 Display Subsystem Register Manual Display Controller Register Mapping Summary 4 Table 7 236 DISPC_CPR_COEF_G Address Offset 0x224 Physical address 0x4805 0624 Instance DISC Description This register configures the color phase rotation matrix coefficients for the ...

Page 1866: ...lue from 512 to 511 10 Reserved Write 0s for future compatibility Read returns 0 RW 0 9 0 BB BB coefficient RW 0x000 Encoded signed value from 512 to 511 Table 7 239 Register Call Summary for Register DISPC_CPR_COEF_B Display Subsystem Basic Programming Model Display Controller Basic Programming Model 0 LCD Specific Control Registers 1 LCD Color Phase Rotation 2 3 Display Subsystem Register Manual...

Page 1867: ...value RW 0x100 Constraint Maximum value is FIFO size DMA burst size 8 bytes Table 7 243 Register Call Summary for Register DISPC_VIDn_PRELOAD Display Subsystem Basic Programming Model Display Controller Basic Programming Model 0 Video DMA Registers 1 2 3 4 Display Subsystem Register Manual Display Controller VID1 Register Mapping Summary 5 Display Controller VID2 Register Mapping Summary 6 7 7 2 3...

Page 1868: ...on the internal activity of the module 11 Reserved 2 Reserved Write 0s for future compatibility RW 0 Read returns 0 1 SOFTRESET Software reset RW 0 Sets this bit to 1 to trigger a module reset The bit is automatically reset by the hardware During reads it always returns 0 0 Normal mode 1 The module is reset 0 AUTOIDLE Internal clock gating strategy interconnectL4 and display controller RW 1 clock ...

Page 1869: ...ARAM RFBI_READ Read 0x1 The access to any of the following registers is stalled RFBI_CMD RFBI_DATA RFBI_STATUS RFBI_PARAM RFBI_READ 7 1 Reserved Reserved Read returns 0 R 0x00 0 RESETDONE Internal reset monitoring R 1 0 Internal module reset is on going 1 Reset completed Table 7 249 Register Call Summary for Register RFBI_SYSSTATUS Display Subsystem Basic Programming Model RFBI Configuration 0 RFB...

Page 1870: ...n to RFBI_DATA are sent using system DMA 0x0 Size of the transfer of 4 words of 32 bit wide 0x1 Size of the transfer of 8 words of 32 bit wide 0x2 Size of the transfer of 16 words of 32 bit wide 4 ITE Internal Trigger RW 0 0 H W waits for ITE bit to be set if in internal trigger mode for the configuration in use 1 User sets the ITE bit to start the transfer when H W takes into account the bit the ...

Page 1871: ...to Transfer 2 3 4 Display Subsystem Register Manual RFBI Register Mapping Summary 5 Table 7 254 RFBI_LINE_NUMBER Address Offset 0x48 Physical address 0x4805 0848 Instance RFBI Description The control register configures the number of lines to synchronize the beginning of the transfer Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LINENUMBER B...

Page 1872: ...el Number of Pixels to Transfer 1 2 RFBI State Machine 3 4 Display Subsystem Register Manual RFBI Register Mapping Summary 5 RFBI Registers 6 7 Table 7 258 RFBI_PARAM Address Offset 0x50 Physical address 0x4805 0850 Instance RFBI Description The control register configures the RFBI parameter Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PARAM...

Page 1873: ...splay Subsystem Overview Display Subsystem Overview 0 Display Subsystem Functional Description RFBI Interconnect FIFO 1 2 Display Subsystem Basic Programming Model High Threshold 3 4 5 RFBI State Machine 6 7 8 9 10 Display Subsystem Register Manual RFBI Register Mapping Summary 11 RFBI Registers 12 13 14 Table 7 262 RFBI_READ Address Offset 0x58 Physical address 0x4805 0858 Instance RFBI Descripti...

Page 1874: ...ing on the parallel mode 7 0 8 bit Data type 8 0 9 bit Data type 11 0 12 bit Data type 15 0 16 bit Data type Table 7 265 Register Call Summary for Register RFBI_STATUS Display Subsystem Basic Programming Model Number of Pixels to Transfer 0 1 RFBI State Machine 2 3 Display Subsystem Register Manual RFBI Register Mapping Summary 4 RFBI Registers 5 6 Table 7 266 RFBI_CONFIGi Address Offset 0x60 i 0x...

Page 1875: ...1 cycle for 1 pixel 01 2 cycles for 1 pixel 10 3 cycles for 1 pixel 11 3 cycles for 2 pixels 8 7 L4FORMAT L4 Write Access format RW 0x0 00 1 pixel per L4 access to the register data 01 Reserved 10 2 pixels per L4 access to the register data with 1st pixel at the position 15 0 11 2 pixels per L4 access to the register data with 1st pixel at the position 31 16 6 5 DATA TYPE Data type from the displa...

Page 1876: ...FFTIME CSONTIME Reserved Bits Field Name Description Type Reset 31 30 Reserved Write 0s for future compatibility RW 0x0 Read returns 0 29 24 REOFFTIME Read Enable deassertion time from start access time RW 0x00 Number of L4Clk cycles 23 20 REONTIME Read Enable assertion time from start access time RW 0x0 Number of L4Clk cycles 19 14 WEOFFTIME Write Enable deassertion time from start access time RW...

Page 1877: ...ame CS RW 0 0 CSPulseWidth does not apply on Write to Write access 1 CSPulseWidth applies on Write to Write access 19 RRENABLE Read to Read Pulse Width Enable same CS RW 0 0 CSPulseWidth does not apply on Read to Read access 1 CSPulseWidth applies on Read to Read access 18 RWENABLE Read to Write Pulse Width Enable same CS RW 0 0 CSPulseWidth does not apply on Read to Write access 1 CSPulseWidth ap...

Page 1878: ...ibility RW 0x0 Read returns 0 20 16 NBBITSPIXEL2 Number of bits RW 0x00 Number of bits from the pixel 2 value from 0 to16 bits The values from 17 to 31 are invalid 15 12 Reserved Write 0s for future compatibility RW 0x0 Read returns 0 11 8 BITALIGNMENTPIXEL1 Bit alignment RW 0x0 Alignment of the bits from pixel 1 on the output interface 7 5 Reserved Write 0s for future compatibility RW 0x0 Read re...

Page 1879: ...ibility RW 0x0 Read returns 0 20 16 NBBITSPIXEL2 Number of bits RW 0x00 Number of bits from the pixel 2 value from 0 to16 bits The values from 17 to 31 are invalid 15 12 Reserved Write 0s for future compatibility RW 0x0 Read returns 0 11 8 BITALIGNMENTPIXEL1 Bit alignment RW 0x0 Alignment of the bits from pixel 1 on the output interface 7 5 Reserved Write 0s for future compatibility RW 0x0 Read re...

Page 1880: ...tibility RW 0x0 Read returns 0 20 16 NBBITSPIXEL2 Number of bits RW 0x00 Number of bits from the pixel 2 value from 0 to16 bits The values from 17 to 31 are invalid 15 12 Reserved Write 0s for future compatibility RW 0x0 Read returns 0 11 8 BITALIGNMENTPIXEL1 Bit alignment RW 0x0 Alignment of the bits from pixel 1 on the output interface 7 5 Reserved Write 0s for future compatibility RW 0x0 Read r...

Page 1881: ...ue 2 Display Subsystem Register Manual RFBI Register Mapping Summary 3 Table 7 280 RFBI_HSYNC_WIDTH Address Offset 0x94 Physical address 0x4805 0894 Instance RFBI Description The control register configures the RFBI HSYNC minimum pulse width Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MINHSYNCPULSEWIDTH Bits Field Name Description Type Res...

Page 1882: ...Q CCE CCO Bits Field Name Description Type Reset 31 5 Reserved Reserved Read returns 0s R 0x0000000 4 CCE Closed caption status for even Field R 0 This bit is set immediately after the data in registers LINE21_E0 and LINE21_E1 have been encoded to closed caption This bit is reset when both of these registers are written 3 CCO Closed Caption Status for Odd Field R 0 This bit is set immediately afte...

Page 1883: ...put RGB data are in binary format with coding range 0 255 The input YCrCb data are in binary format with coding range 0 255 0x1 The input RGB data are in binary format with coding range 16 235 The input YCrCb data are in binary format conforming to ITU 601 standard 4 2 BCOLOR Background color select RW 0x1 0x0 black 0x1 blue 0x2 red 0x3 magenta 0x4 green 0x5 cyan 0x6 yellow 0x7 white 1 0 FMT These...

Page 1884: ...ter Settings 0 Display Subsystem Register Manual Video Encoder Register Mapping Summary 1 Table 7 290 VENC_SYNC_CTRL Address Offset 0x14 Physical address 0x4805 0C14 Instance VENC Description Sync Control Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved IGNP FREE ESAV VBLKM HBLKM NBLNKS FID_POL Reserved Bits Field Name Descrip...

Page 1885: ...output polarity RW 0 0x0 Odd field 0 Even field 1 0x1 Odd field 1 Even field 0 5 0 Reserved Reserved Read returns 0 RW 0x00 Table 7 291 Register Call Summary for Register VENC_SYNC_CTRL Display Subsystem Basic Programming Model Video Encoder Programming Sequence 0 Video Encoder Register Settings 1 Display Subsystem Register Manual Video Encoder Register Mapping Summary 2 Video Encoder Registers 3 ...

Page 1886: ...bsystem Basic Programming Model Video Encoder Register Settings 0 Display Subsystem Register Manual Video Encoder Register Mapping Summary 1 Video Encoder Registers 2 Table 7 296 VENC_HFLTR_CTRL Address Offset 0x24 Physical address 0x4805 0C24 Instance VENC Description VENC_HFLTR_CTRL Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CINTP YINTP...

Page 1887: ...631 For common values for FCC 15 0 bit field refer to Table 7 42 Reset value is for NTSC 601 standard Table 7 299 Register Call Summary for Register VENC_CC_CARR_WSS_CARR Display Subsystem Functional Description Closed Caption Encoding 0 1 2 Wide Screen Signaling WSS Encoding 3 4 Display Subsystem Basic Programming Model Video Encoder Register Settings 5 Display Subsystem Register Manual Video Enc...

Page 1888: ...C with no pedestal WHITE BLACK 100 IRE GU 0x117 PAL with no pedestal WHITE BLACK 100 IRE GU 0x111 Table 7 303 Register Call Summary for Register VENC_GAIN_U Display Subsystem Functional Description Chroma Stage 0 Display Subsystem Basic Programming Model Video Encoder Register Settings 1 Display Subsystem Register Manual Video Encoder Register Mapping Summary 2 Table 7 304 VENC_GAIN_V Address Offs...

Page 1889: ...Y 0x147 PAL with no pedestal WHITE BLACK 100 IRE GY 0x140 Table 7 307 Register Call Summary for Register VENC_GAIN_Y Display Subsystem Functional Description Luma Stage 0 Display Subsystem Basic Programming Model Video Encoder Register Settings 1 Display Subsystem Register Manual Video Encoder Register Mapping Summary 2 Table 7 308 VENC_BLACK_LEVEL Address Offset 0x3C Physical address 0x4805 0C3C ...

Page 1890: ...38 NTSC with no pedestal WHITE BLACK 100 IRE BLANK_LEVEL 0x38 PAL with no pedestal WHITE BLACK 100 IRE BLANK_LEVEL 0x3B Table 7 311 Register Call Summary for Register VENC_BLANK_LEVEL Display Subsystem Functional Description Luma Stage 0 Display Subsystem Basic Programming Model Video Encoder Register Settings 1 Display Subsystem Register Manual Video Encoder Register Mapping Summary 2 Table 7 312...

Page 1891: ...Basic Programming Model Video Encoder Register Settings 0 Display Subsystem Register Manual Video Encoder Register Mapping Summary 1 Table 7 314 VENC_M_CONTROL Address Offset 0x48 Physical address 0x4805 0C48 Instance VENC Description VENC_M_CONTROL Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CBW PAL PALI PALN FFRQ PALPHS Bits Field Name D...

Page 1892: ... 1 2 Display Subsystem Basic Programming Model Video Encoder Register Settings 3 Display Subsystem Register Manual Video Encoder Register Mapping Summary 4 Video Encoder Registers 5 6 Table 7 316 VENC_BSTAMP_WSS_DATA Address Offset 0x4C Physical address 0x4805 0C4C Instance VENC Description VENC BSTAMP and WSS_DATA Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 1893: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSC Bits Field Name Description Type Reset 31 0 FSC These four bytes data program the color subcarrier frequency and are RW 0x21F07C1F determined by the following formula S_CARR ROUND Fsc Fclkenc 232 Where Fsc Frequency of the subcarrier Fclkenc Frequency of the internal video encoding clock 2 LLEN Fh LLEN Number of pixels in a scan line For LLEN set...

Page 1894: ...1 Closed Caption Data Format 15 8 First byte of data 7 0 Second byte of data Table 7 321 Register Call Summary for Register VENC_LINE21 Display Subsystem Functional Description Closed Caption Encoding 0 1 2 3 Display Subsystem Basic Programming Model Video Encoder Register Settings 4 Display Subsystem Register Manual Video Encoder Register Mapping Summary 5 Table 7 322 VENC_LN_SEL Address Offset 0...

Page 1895: ...et 0x5C Physical address 0x4805 0C5C Instance VENC Description VENC L21 WC_CTL registers Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LINE Reserved L21EN INV EVEN_ODD_EN Bits Field Name Description Type Reset 31 16 Reserved Reserved Read returns 0s RW 0x0000 15 INV WSS inverter RW 0 0x0 No effect 0x1 Invert WSS data 14 13 EVEN_ODD_EN This b...

Page 1896: ...9 8 7 6 5 4 3 2 1 0 Reserved VTRIG Reserved HTRIG Bits Field Name Description Type Reset 31 26 Reserved Reserved Read returns 0s RW 0x00 25 16 VTRIG Vertical trigger reference for VSYNC These bits specify the phase RW 0x000 between VSYNC input and the lines in a field The VTRIG field is expressed in units of half line 15 11 Reserved Reserved Read returns 0s RW 0x00 10 0 HTRIG Horizontal trigger ph...

Page 1897: ...8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FAL Reserved FLEN Bits Field Name Description Type Reset 31 25 Reserved Reserved Read returns 0s RW 0x00 24 16 FAL First Active Line of Field These bits define the first active line of a field RW 0x016 15 10 Reserved Reserved Read returns 0s RW 0x00 9 0 FLEN Field length These bits define the number of half_lines ...

Page 1898: ...del Video Encoder Register Settings 0 Display Subsystem Register Manual Video Encoder Register Mapping Summary 1 Video Encoder Registers 2 3 Table 7 334 VENC_HS_INT_START_STOP_X Address Offset 0x70 Physical address 0x4805 0C70 Instance VENC Description VENC_HS_INT_START_STOP_X Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HS_INT_STOP_X Reser...

Page 1899: ...ideo Encoder Register Settings 0 Display Subsystem Register Manual Video Encoder Register Mapping Summary 1 Video Encoder Registers 2 Table 7 338 VENC_VS_INT_START_X Address Offset 0x78 Physical address 0x4805 0C78 Instance VENC Description VENC_VS_INT_START_X Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VS_INT_START_X Reserved Bits Field N...

Page 1900: ...play Subsystem Register Manual Video Encoder Register Mapping Summary 1 Table 7 342 VENC_VS_INT_STOP_Y_VS_EXT_START_X Address Offset 0x80 Physical address 0x4805 0C80 Instance VENC Description VENC VS_INT_STOP_Y and VS_EXT_START_X Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VS_EXT_START_X Reserved VS_INT_STOP_Y Bits Field Name Description ...

Page 1901: ..._VS_EXT_STOP_X_VS_EXT_START_Y Display Subsystem Basic Programming Model Video Encoder Register Settings 0 Display Subsystem Register Manual Video Encoder Register Mapping Summary 1 Table 7 346 VENC_VS_EXT_STOP_Y Address Offset 0x88 Physical address 0x4805 0C88 Instance VENC Description VENC VS_EXT_STOP_Y Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 1902: ...ual Video Encoder Register Mapping Summary 1 Video Encoder Registers 2 3 Table 7 350 VENC_AVID_START_STOP_Y Address Offset 0x94 Physical address 0x4805 0C94 Instance VENC Description VENC_AVID_START_STOP_Y Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved AVID_STOP_Y Reserved AVID_START_Y Bits Field Name Description Type Reset 31 26 Reserved Res...

Page 1903: ... Subsystem Register Manual Video Encoder Register Mapping Summary 1 Table 7 354 VENC_FID_INT_OFFSET_Y_FID_EXT_START_X Address Offset 0xA4 Physical address 0x4805 0CA4 Instance VENC Description VENC FID_INT_OFFSET_Y and FID_EXT_START_X Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FID_EXT_START_X Reserved FID_INT_OFFSET_Y Bits Field Name Desc...

Page 1904: ...STOP_X Address Offset 0xB0 Physical address 0x4805 0CB0 Instance VENC Description TV Detection Start and Stop pixel values Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TVDETGP_INT_STOP_X Reserved TVDETGP_INT_START_X Bits Field Name Description Type Reset 31 26 Reserved Reserved Read returns 0s RW 0x00 25 16 TVDETGP_INT_STOP_X TVDETGP intern...

Page 1905: ...escription TV Detection Disconnection Pulse Generation 0 TV Detection Procedure 1 2 3 TV Disconnection Procedure 4 5 6 Display Subsystem Basic Programming Model Video Encoder Register Settings 7 Display Subsystem Register Manual Video Encoder Register Mapping Summary 8 Table 7 362 VENC_GEN_CTRL Address Offset 0xB8 Physical address 0x4805 0CB8 Instance VENC Description TVDETGP enable and SYNC_POLAR...

Page 1906: ...eserved Reserved Read returns 0s RW 0x00 0 EN TVDETGP generation enable RW 0 0x0 Disabled 0x1 Enabled Table 7 363 Register Call Summary for Register VENC_GEN_CTRL Display Subsystem Functional Description TV Detection Disconnection Pulse Generation 0 1 TV Detection Procedure 2 3 TV Disconnection Procedure 4 5 Display Subsystem Basic Programming Model Video Encoder Register Settings 6 Display Subsys...

Page 1907: ...mes from internal register OUTPUT_CONTROL 25 16 0x1 Luma test data comes from display controller video port G 1 0 B 7 0 4 TEST_MODE This enables the video DACs to be tested The values sent to the RW 0x0 DACs comes from a register for each output channel Luma Composite or Chroma or from the display controller video port bits G 1 0 B 7 0 depending on the setting of the Source bits 0x0 Video outputs ...

Page 1908: ...ite video is selected and the Chroma Video DAC2 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CHROMA_TEST RESERVED COMPOSITE_TEST Bits Field Name Description Type Reset 31 26 RESERVED Reserved Read returns 0s RW 0x00 25 16 CHROMA_TEST In test mode DAC 2 input value RW 0x000 15 10 RESERVED Reserved Read returns 0s RW 0x00 9 0 COMPOSITE_TEST I...

Page 1909: ...tance DSI_PROTOCOL_ENGINE Description SYSTEM CONFIGURATION REGISTER This register is the system configuration register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED AUTO_IDLE ENWAKEUP SIDLEMODE SOFT_RESET CLOCKACTIVITY Bits Field Name Description Type Reset 31 14 RESERVED Write 0s for future compatibility RW 0x00000 Reads r...

Page 1910: ...erface clock gating strategy is applied based on the module interface activity Table 7 371 Register Call Summary for Register DSI_SYSCONFIG Display Subsystem Integration Software Reset 0 Clock Activity Mode 1 2 3 Autoidle Mode 4 Idle Mode 5 6 7 Display Subsystem Basic Programming Model Software Reset 8 Power Management 9 10 Software Reset 11 Display Subsystem Use Cases and Tips Reset DSI Modules 1...

Page 1911: ...e VC is disabled the interrupt is not generated Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED TA_TO_IRQ WAKEUP_IRQ PLL_LOCK_IRQ LP_RX_TO_IRQ HS_TX_TO_IRQ PLL_RECAL_IRQ SYNC_LOST_IRQ TE_TRIGGER_IRQ PLL_UNLOCK_IRQ ACK_TRIGGER_IRQ COMPLEXIO_ERR_IRQ LDO_POWER_GOOD_IRQ VIRTUAL_CHANNEL3_IRQ VIRTUAL_CHANNEL2_IRQ VIRTUAL_C...

Page 1912: ...Reads returns 0 12 11 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 10 COMPLEXIO_ Error signaling from complex I O status of the complex I O R 0x0 ERR_IRQ errors received from the complex I O events are defined in DSI_COMPLEXIO_IRQSTATUS 0x0 READS Event is false 0x1 READS Event is true pending 9 PLL_RECAL_IRQ PLL recalibration event assertion of recalibration signal from the RW...

Page 1913: ...are defined in DSI_VC2_IRQSTATUS 0x0 READS Event is false 0x1 READS Event is true pending 1 VIRTUAL_CHANNEL1_ Virtual channel 1 R 0x0 IRQ Error signaling from DSI Virtual Channel1 Status of DSI Virtual Channel1 errors received from DSI Virtual Channel1 events are defined in DSI_VC1_IRQSTATUS 0x0 READS Event is false 0x1 READS Event is true pending 0 VIRTUAL_CHANNEL0_ Virtual channel 0 R 0x0 IRQ Er...

Page 1914: ...ds returns 0 20 TA_TO_IRQ_EN Turn around Time out RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 19 LDO_POWER_GOOD_ Transition of the status signal LDOPWRGOOD from the RW 0x0 IRQ_EN DSI_PHY indicating a state change for the supply VDDALDODSIPLL from up to down or down to up 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 18 SYNC_LOST_IRQ_EN Synchroni...

Page 1915: ... RW 0x0 Reads returns 0 5 RESYNCHRONIZATION_ Resynchronization RW 0x0 IRQ_EN 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 4 WAKEUP_IRQ_EN Wakeup RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 3 0 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 Table 7 377 Register Call Summary for Register DSI_IRQENABLE Display Subsystem Function...

Page 1916: ... mode RW 0x0 MODE 0x0 Packets in TX FIFO are sent during HSA blanking period of video mode or LPS is used 0x1 LONG BLANKING PACKETS only are used during HSA blanking period of video mode 22 HBP_BLANKING_ Blanking mode RW 0x0 MODE 0x0 Packets in TX FIFO are sent during HBP blanking period of video mode or LPS is used 0x1 LONG BLANKING PACKETS only are used during HBP blanking period of video mode 2...

Page 1917: ...on as possible Only the current transfer on DSI link and already scheduled ones are transmitted All the other transfers are discarded 13 12 LINE_BUFFER Number of line buffers to be used while receiving data on the video RW 0x0 port 0x0 No line buffer 0x1 1 line buffer 0x2 2 line buffers 11 VP_VSYNC_POL VP vertical synchronization signal polarity RW 0x0 0x0 VSYNC signal on the video port is active ...

Page 1918: ...l VC IDs 0x0 Disabled 0x1 Enabled 1 CS_RX_EN Enables the checksum check for the received payload long packet RW 0x0 only for all VC IDs 0x0 Disabled 0x1 Enabled 0 IF_EN Enables the module When the module is disabled the signals from RW 0x0 the complex I O are gated no updates of the interrupt status register It is not possible to change the bit fields in the DSI_CTRL register except IF_EN when it ...

Page 1919: ...eo Port 76 77 Configure DSI Protocol Engine 78 79 80 81 82 83 84 85 86 Enable Command Mode Using DISPC Video Port 87 88 89 90 Display Subsystem Register Manual DSI Protocol Engine Register Mapping Summary 91 DSI Protocol Engine Registers 92 93 94 95 96 97 98 99 Table 7 380 DSI_COMPLEXIO_CFG1 Address Offset 0x0000 0048 Physical Address 0x4804 FC48 Instance DSI_PROTOCOL_ENGINE Description COMPLEXIO ...

Page 1920: ...ing 0x1 Reset completed 28 27 PWR_CMD Command for power control of the complex I O RW 0x0 0x0 Command to change to OFF state 0x1 Command to change to ON state 0x2 Command to change to ultralow power state 26 25 PWR_STATUS Status of the power control of the complex I O R 0x0 0x0 complex I O in OFF state 0x1 complex I O in ON state 0x2 complex I O in ultralow power state 24 22 RESERVED Write 0s for ...

Page 1921: ...dy 0x1 pin order dsi_dx and dsi_dy 2 0 CLOCK_POSITION Position and order of the CLOCK lane RW 0x0 The clock lane is always present 0x1 Clock lane is at the position 1 line 1 0x2 Clock lane is at the position 2 line 2 0x3 Clock lane is at the position 3 line 3 Other values reserved Table 7 381 Register Call Summary for Register DSI_COMPLEXIO_CFG1 Display Subsystem Environment Data Clock Configurati...

Page 1922: ...alse WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 30 ULPSACTIVENOT_ All signals ULPSActiveNOT are 0 RW 0x0 ALL0_IRQ 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 29 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 28 RESERVED Write 0s for future compatibility RW 0x0 Reads re...

Page 1923: ...ower state RW 0x0 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 15 STATEULPS1_IRQ Lane 1 in ultralow power state RW 0x0 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 14 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 13 RESERVED Write 0s for future c...

Page 1924: ... READS Event is true pending WRITES Status bit is reset 1 ERRSYNCESC2_IRQ Low power Data transmission synchronization error for lane 2 RW 0x0 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 0 ERRSYNCESC1_IRQ Low power Data transmission synchronization error for lane 1 RW 0x0 0x0 READS Event is false WRITES Status bit unchanged 0x1 REA...

Page 1925: ...1 Event generates an interrupt when it occurs 30 ULPSACTIVENOT_ All signals ULPSActiveNOT are 0 RW 0x0 ALL0_IRQ_EN 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 29 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 28 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 27 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 26 RESERVE...

Page 1926: ...s an interrupt when it occurs 11 ERRCONTROL2_IRQ_EN Control error for lane 2 RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 10 ERRCONTROL1_IRQ_EN Control error for lane 1 RW 0x0 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 9 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 8 RESERVED Write 0s for future compatibility RW 0x0 Reads ...

Page 1927: ...stance DSI_PROTOCOL_ENGINE Description CLOCK CONTROL This register controls the CLOCK GENERATION The register can be modified only when IF_EN is reset Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LP_CLK_DIVISOR CIO_CLK_ICG PLL_PWR_CMD LP_CLK_ENABLE PLL_PWR_STATUS DDR_CLK_ALWAYS_ON HS_AUTO_STOP_ENABLE HS_MANUAL_STOP_CTRL LP_RX_SYNCHRO_ENABLE...

Page 1928: ...manual control of the assertion de assertion of the signal DSIStopClk by users 0x0 DSIStopClk de assertion unconditionally 0x1 DSIStopClk assertion unconditionally 18 HS_AUTO_STOP_ENABLE Enables the automatic assertion de assertion of RW 0x0 DSIStopClk signal 0x0 Auto mode disabled 0x1 Auto mode enabled 17 16 LP_CLK_NULL_PACKET_ Indicates the size of LP NULL Packets to be sent RW 0x0 SIZE automati...

Page 1929: ...rotocol Engine 29 Display Subsystem Register Manual DSI Protocol Engine Register Mapping Summary 30 DSI Protocol Engine Registers 31 32 Table 7 388 DSI_TIMING1 Address Offset 0x0000 0058 Physical Address 0x4804 FC58 Instance DSI_PROTOCOL_ENGINE Description TIMING1 REGISTER This register controls the DSI Protocol Engine module timers Any bit field can be modified while DSI_CTRL IF_EN is set to 1 It...

Page 1930: ...r for the number of DSI_FCLK clock cycles RW 0x1 defined in STOP_STATE_COUNTER_IO bit field 0x0 The number of DSI_FCLK clock cycles defined in STOP_STATE _COUNTER_IO is multiplied by 1x 0x1 The number of DSI_FCLK clock cycles defined in STOP_STATE _COUNTER_IO is multiplied by 16x 13 STOP_STATE_X4_IO Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1 defined in STOP_STATE_COUNTER_...

Page 1931: ...onal clock RW 0x1 cycles defined in HS_TX_COUNTER bit 0x0 The number of TxByteClkHS functional clock cycles defined in HS_TX_TO_COUNTER is multiplied by 1x 0x1 The number of TxByteClkHS functional clock cycles defined in HS_TX_TO_COUNTER is multiplied by 8x 28 16 HS_TX_TO_ HS_TX_TIMER counter It indicates the number of TxByteClkHS RW 0x1FFF COUNTER function clock cycles for the HS TX timer The val...

Page 1932: ...ted values are from 0 to 255 23 12 HFP Defines the horizontal front porch used in video mode in number of RW 0x000 byte clock cycles TxByteClkHS The supported values are from 0 to 255 11 0 HBP Defines the horizontal back porch used in video mode in number of RW 0x000 byte clock cycles TxByteClkHS The supported values are from 0 to 255 Table 7 393 Register Call Summary for Register DSI_VM_TIMING1 D...

Page 1933: ...Basic Programming Model Video Mode 1 2 Display Subsystem Use Cases and Tips Configure DSI Timing and Virtual Channels 3 Display Subsystem Register Manual DSI Protocol Engine Register Mapping Summary 4 Table 7 396 DSI_VM_TIMING3 Address Offset 0x0000 0068 Physical Address 0x4804 FC68 Instance DSI_PROTOCOL_ENGINE Description VIDEO MODE TIMING REGISTER This register defines the video mode timing Type...

Page 1934: ...d if DSI_CLK_CTRL 13 DDR_CLK_ALWAYS_ON is set to 1 since the DDR clock is always present Table 7 399 Register Call Summary for Register DSI_CLK_TIMING Display Subsystem Functional Description Timing Parameters for an LP to HS Transaction 0 Timing Parameters for an HS to LP Transaction 1 Display Subsystem Use Cases and Tips Configure DSI Timing and Virtual Channels 2 Configure DSI Protocol Engine 3...

Page 1935: ..._SIZE Display Subsystem Basic Programming Model Command Mode TX FIFO 0 1 2 3 4 Display Subsystem Use Cases and Tips Configure DSI Protocol Engine 5 Display Subsystem Register Manual DSI Protocol Engine Register Mapping Summary 6 Table 7 402 DSI_RX_FIFO_VC_SIZE Address Offset 0x0000 0074 Physical Address 0x4804 FC74 Instance DSI_PROTOCOL_ENGINE Description Defines the corresponding memory entries a...

Page 1936: ...ister Mapping Summary 4 Table 7 404 DSI_COMPLEXIO_CFG2 Address Offset 0x0000 0078 Physical Address 0x4804 FC78 Instance DSI_PROTOCOL_ENGINE Description COMPLEXIO CONFIGURATION REGISTER for the complex I O This register contains the lane configuration for the ULPS for each lane Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED LP_BUSY HS...

Page 1937: ...active If the lane is a data lane TxRequestEsc is asserted and synchronously TxUlpsEsc is asserted for one period of TxClkEsc 5 LANE1_ULPS_ Enables the ULPS for the lane 1 The HW should change the state of RW 0x0 SIG2 the lane to ULPS only when it is in stop state and there is no data pending inside the DSI protocol engine and the DSI protocol engine has control of the bus BTA has not been sent Th...

Page 1938: ...ive WRITE Change request to active If the lane is a data lane TxRequestEsc is asserted and synchronously TxUlpsEsc is asserted for one period of TxClkEsc Table 7 405 Register Call Summary for Register DSI_COMPLEXIO_CFG2 Display Subsystem Environment ULPS 0 Display Subsystem Basic Programming Model Ultra Low Power State 1 Entering ULPS 2 3 4 5 6 7 8 9 Exiting ULPS 10 11 12 13 14 15 16 17 18 19 20 2...

Page 1939: ...NG Defines the number of TxByteClkHS cycles that can be used RW 0x00 for interleaving high speed command mode packet into Video Mode stream during HFP blanking period The supported values are from 0 to 255 7 0 HBP_HS_INTERLEAVING Defines the number of TxByteClkHS cycles that can be used RW 0x00 for interleaving high speed command mode packet into Video Mode stream during HBP blanking period The su...

Page 1940: ...defines the video mode timing Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED HSA_LP_INTERLEAVING HFP_LP_INTERLEAVING HBP_LP_INTERLEAVING Bits Field Name Description Type Reset 31 24 RESERVED Write 0s for future compatibility RW 0x00 Reads returns 0 23 16 HSA_LP_INTERLEAVING Defines the number of bytes for Low Power command RW 0x00 mode packet...

Page 1941: ...Environment Video Port Used for Video Mode 0 Display Subsystem Functional Description HS Command Mode Interleaving Programming Model 1 LP Command Mode Interleaving Programming Model 2 Display Subsystem Basic Programming Model Video Mode 3 Display Subsystem Register Manual DSI Protocol Engine Register Mapping Summary 4 Table 7 416 DSI_VM_TIMING7 Address Offset 0x0000 0090 Physical Address 0x4804 FC...

Page 1942: ...Mapping Summary 5 Table 7 418 DSI_STOPCLK_TIMING Address Offset 0x0000 0094 Physical Address 0x4804 FC94 Instance DSI_PROTOCOL_ENGINE Description Number of functional clock cycles to wait for TxByteClock to stop start after change in DSIStopClk signal Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DSI_STOPCLK_LATENCY Bits Field Name Descripti...

Page 1943: ...bits 0x2 4 x 32 bits 0x3 8 x 32 bits 0x4 16 x 32 bits 0x5 32 x 32 bits 23 21 DMA_TX_REQ_NB Selection of the use of the DMA request associated to RW 0x0 the TX FIFO 0x0 DSI_DMA_REQ0 is selected 0x1 DSI_DMA_REQ1 is selected 0x2 DSI_DMA_REQ2 is selected 0x3 DSI_DMA_REQ3 is selected 0x4 No DMA req selected 20 RX_FIFO_NOT_EMPTY FIFO status in command mode Otherwise this bit can be R 0x0 ignored 0x0 The...

Page 1944: ...lue 0x00 is used 0x1 Enabled The Check sum value is calculated by HW 6 BTA_EN Send the bus turn around to the peripheral It can be RW 0x0 used when the automatic mode is enabled BTA_SHORT_EN 1 or and BTA_LONG_EN 1 In that case only one BTA is sent to the peripheral The manual mode allows users to define for which packets the turn around is required for example getting acknowledge from the peripher...

Page 1945: ...e DSI_VCn_XXX registers the corresponding VC ID 0x1 Enabled No change is allowed to the VC registers except for setting the bit fields registers DSI_VCn_CTRL 6 BTA_EN DSI_VCn_TE 15 0 TE_SIZE DSI_VCn_TE 31 TE_START DSI_VCn_LONG_XXX DSI_VCn_SHORT_XXX DSI_VCn_IRQXXX registers Table 7 421 Register Call Summary for Register DSI_VCn_CTRL Display Subsystem Environment Blanking 0 1 2 3 Display Subsystem F...

Page 1946: ...0x0 Disables the automatic transfer of the data using the TE trigger as a synchronization event The interruption is used to know when the TE trigger is received The hardware resets the bit field when the transfer completes TE_SIZE 0 0x1 Enables the automatic transfer of the data using the TE trigger as a synchronization event 29 24 RESERVED Write 0s for future compatibility RW 0x0000 Reads returns...

Page 1947: ... DATA FIELD ECC W 0x00000000 Table 7 425 Register Call Summary for Register DSI_VCn_LONG_PACKET_HEADER Display Subsystem Environment Video Port Used on Command Mode 0 1 Virtual Channel ID VC Field DI 7 6 2 Display Subsystem Functional Description Video Mode 3 Command Mode 4 5 6 7 8 9 Bus Turnaround 10 Tearing Effect 11 12 13 Display Subsystem Basic Programming Model Global Register Controls 14 Vir...

Page 1948: ...5 Tearing Effect 6 7 Display Subsystem Basic Programming Model Global Register Controls 8 Packets 9 10 11 Command Mode TX FIFO 12 13 14 Command Mode RX FIFO 15 Command Mode Transfer Example 1 16 17 Display Subsystem Register Manual Display Subsystem Register Manual 18 DSI Protocol Engine Register Mapping Summary 19 DSI Protocol Engine Registers 20 Table 7 428 DSI_VCn_SHORT_PACKET_HEADER Address Of...

Page 1949: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CS_IRQ BTA_IRQ FIFO_TX_UDF_IRQ FIFO_TX_OVF_IRQ FIFO_RX_OVF_IRQ PACKET_SENT_IRQ ECC_CORRECTION_IRQ PP_BUSY_CHANGE_IRQ ECC_NO_CORRECTION_IRQ Bits Field Name Description Type Reset 31 9 RESERVED Write 0s for future compatibility RW 0x000000 Reads returns 0 8 PP_BUSY_CHANGE_IRQ Video port ping pong buffer busy status RW 0 0x0 READS Ev...

Page 1950: ...Status bit is reset 2 PACKET_SENT_IRQ Indicates that a packet has been sent It is used when RW 0x0 BTA manual mode is used 0x0 READS Event is false WRITES Status bit unchanged 0x1 READS Event is true pending WRITES Status bit is reset 1 ECC_CORRECTION_IRQ Virtual channel ECC has been used to do the correction RW 0x0 of the only 1 bit error status short and long packet only 0x0 READS Event is false...

Page 1951: ...nce the transfer of the packet are already started transfer started since the packet size is bigger than space allocated in the FIFO 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 6 ECC_NO_CORRECTION_ ECC error short and long packets No correction of the RW 0x0 IRQ_EN header because of more than 1 bit error 0x0 Event is masked 0x1 Event generates an interrupt when it occurs 5 ...

Page 1952: ...tial Table 7 434 DSI_PHY_REGISTER0 Address Offset 0x0000 0000 Physical Address 0x4804 FE00 Instance DSI_PHY Description Configuration register for HS mode timings Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REG_THSPREPARE REG_THSPRPR_THSZERO REG_THSTRAIL REG_THSEXIT Bits Field Name Description Type Reset 31 24 REG_THSPREPARE REG_THSPREPARE timing p...

Page 1953: ... 45 ns PROGRAMMED VALUE ceil 145 ns DDR_Clock_Period Default value is programmed for 400 MHz Table 7 435 Register Call Summary for Register DSI_PHY_REGISTER0 Display Subsystem Functional Description Timing Parameters for an LP to HS Transaction 0 1 2 Timing Parameters for an HS to LP Transaction 3 4 Shadowing Register 5 Display Subsystem Basic Programming Model High Speed Clock Transmission 6 7 Hi...

Page 1954: ...ne N REG_TLPXBY2 ceil 2 N 4 4 DDR_Clock_Period Default value is programmed for 400 MHz This is the internal timer value The value seen on line will have variance due to rise fall mismatch effects Note TLPX is used to define the length of LP 01 state in HS Start of Transmission sequences on clock and data lanes For all other purposes TLPX is defined by the period of TxLPEsc clock 15 8 REG_TCLKTRAIL...

Page 1955: ...al DSI_PHY Register Mapping Summary 19 Table 7 438 DSI_PHY_REGISTER2 Address Offset 0x0000 0008 Physical Address 0x4804 FE08 Instance DSI_PHY Description Sync pattern and reserved bits Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSSYNCPATTERN RESERVED REG_TCLKPREPARE Bits Field Name Description Type Reset 31 24 HSSYNCPATTERN Default 184 10111000 MS...

Page 1956: ...REG_TXTRIGGERESC3 is asserted first RW 0x62 C3 bit transmitted to last bit transmitted Default 01100010 23 16 REG_TXTRIGGERES Default 01011101 RW 0x5D C2 15 8 REG_TXTRIGGERES Default 00100001 RW 0x21 C1 7 0 REG_TXTRIGGERES Default 10100000 RW 0xA0 C0 Table 7 441 Register Call Summary for Register DSI_PHY_REGISTER3 Display Subsystem Functional Description PHY Triggers 0 Reset 1 Display Subsystem Re...

Page 1957: ...2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESETDONESCPCLK RESETDONEPWRCLK RESETDONETXCLKESC2 RESETDONETXBYTECLK RESETDONETXCLKESC1 RESETDONETXCLKESC0 Bits Field Name Description Type Reset 31 RESETDONETXBYT RESETDONETXBYTECLK R 0 ECLK 0x0 No reset 0x1 Reset done for the TXBYTECLK domain 30 RESETDONESCPCL RESETDONESCPCLK R 0 K 0x0 No reset 0x1 Reset done for the SC...

Page 1958: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DSI_PLL_SYSRESET DSI_PLL_HALTMODE DSI_PLL_GATEMODE DSI_PLL_AUTOMODE DSI_HSDIV_SYSRESET Bits Field Name Description Type Reset 31 5 RESERVED Reserved Write only zero for future compatibility Reads return R 0x0000000 zero 4 DSI_HSDIV_SYSRESET Force HSDIVIDER SYSRESET RW 0x0 0x0 HSDIVIDER SYSRESET controlle...

Page 1959: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DSI_PLL_LIMP DSI_PLL_LOCK DSI_PLL_RECAL DSI_PLL_BYPASS DSS_CLOCK_ACK DSI_BYPASSACKZ DSI_PLL_LOSSREF DSI_PLL_HIGHJITTER DSIPROTO_CLOCK_ACK DSI_PLLCTRL_RESET_DONE Bits Field Name Description Type Reset 31 10 RESERVED Reserved Reads return zero R 0x000000 9 DSI_BYPASSACKZ State of bypass mode on PHY and HSDIVIDER...

Page 1960: ...programming guide for the use of this bit 0x0 PLL is not locked 0x1 PLL is locked 0 DSI_PLLCTRL_ DSI PLL Controller reset done status R 0x0 RESET_DONE 0x0 Reset is in progress 0x1 Reset has completed Table 7 449 Register Call Summary for Register DSI_PLL_STATUS Display Subsystem Functional Description Error Handling 0 1 Display Subsystem Basic Programming Model Software Reset 2 DSI PLL Clock Gatin...

Page 1961: ...dule Registers 16 Table 7 452 DSI_PLL_CONFIGURATION1 Address Offset 0x0000 000C Physical Address 0x4804 FF0C Instance DSI_PLL_CTRL Description This register contains the latched PLL and HSDIVDER configuration bits Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DSI_PLL_REGM DSI_PLL_REGN DSS_CLOCK_DIV DSI_PLL_STOPMODE DSIPROTO_CLOCK_DIV Bits Fi...

Page 1962: ...SI_HSDIVBYPASS DSS_CLOCK_PWDN DSI_PLL_HIGHFREQ DSI_PLL_PLLLPMODE DSI_PROTO_CLOCK_EN DSI_PLL_LOWCURRSTBY DSI_PLL_DRIFTGUARDEN DSI_PROTO_CLOCK_PWDN DSI_PLL_TIGHTPHASELOCK Bits Field Name Description Type Reset 31 21 RESERVED Reserved Write only zero for future compatibility Reads return R 0x000 zero 20 DSI_HSDIVBYPASS Forces HSDIVIDER to bypass mode RW 0x0 0x0 HSDIVIDER in normal operation Bypass co...

Page 1963: ...SELOCK bit 0x1 Frequency lock 0x2 Spare 8 DSI_PLL_ DSI PLL DRIFTGUARDEN RW 0x0 DRIFTGUARDEN 0x0 Only RECAL flag is asserted in case of temperature drift The programmer should take appropriate action 0x1 Temperature drift will initiate automatic recalibration RECAL flag will be asserted while this is taking place 7 DSI_PLL_ DSI PLL Phase Lock criteria RW 0x0 TIGHTPHASELOCK If this bit is set the ph...

Page 1964: ... Programming Model DSI PLL Go Sequence 7 8 9 DSI PLL Lock Sequence 10 11 12 13 Display Subsystem Use Cases and Tips Set Up DSI DPLL 14 Configure DSI PLL 15 16 17 18 Display Subsystem Register Manual DSI PLL Controller Register Mapping Summary 19 1964 Display Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 1965: ...e from Imagination Technologies Ltd This document contains materials that are 2003 2007 Imagination Technologies Ltd POWERVR and USSE are trademarks or registered trademarks of Imagination Technologies Ltd Topic Page 8 1 SGX Overview 1966 8 2 SGX Integration 1969 8 3 SGX Functional Description 1971 8 4 SGX Register Manual 1973 1965 SWPU177N December 2009 Revised November 2010 2D 3D Graphics Accele...

Page 1966: ...X subsystem in the device Figure 8 1 Graphics Accelerator Highlight The SGX graphics accelerator can simultaneously process various multimedia data types Pixel data Vertex data Video data General purpose processing This is achieved through a multithreaded architecture using two levels of scheduling and data partitioning enabling zero overhead task switching The SGX subsystem is connected to the L3...

Page 1967: ...ure support Cube map Projected textures 2D textures Nonsquare textures Texture formats RGBA 8888 565 1555 Monochromatic 8 16 16f 32f 32int Dual channel 8 8 16 16 16f 16f Compressed textures PVR TC1 PVR TC2 ETC1 Programmable support for all YUV formats Resolution support Frame buffer maximum size 2048 x 2048 Texture maximum size 2048 x 2048 Texture filtering Bilinear trilinear anisotropic Independe...

Page 1968: ...EE float 2 way 16 bit fixed point 4 way 8 bit integer 32 bit bit wise logical only Static and dynamic flow control Subroutine calls Loops Conditional branches Zero cost instruction predication Procedural geometry Allows generation of primitives Effective geometry compression High order surface support External data access Permits reads from main memory using cache Permits writes to main memory Dat...

Page 1969: ...me I O 1 Description SGX_FCLK I Functional clock two possible clock sources Functional clock domain SGX_ICLK I Interface clock L3 interconnect clock domain Interface clock domain 1 I Input O Output The SGX_ICLK interface clock manages the data transfer on the L3 master and slave ports The source of SGX_ICLK is the PRCM clock SGX_ICLK which belongs to the SGX clock domain and runs at the L3 interco...

Page 1970: ...bsystem has its own reset domain Global reset of the SGX is performed by activating the SGX_RST signal in the SGX_RST domain Software controls the release of SGX_RST using the PRCM RM_RSTCTRL_SGX 0 SGX_RST bit 8 2 1 3 Power Management The SGX subsystem has its own power domain SGX power domain See Chapter 3 Power Reset and Clock Management for additional information about the SGX power domain As d...

Page 1971: ...hitecture comprises the following elements Coarse grain scheduler Programmable data sequencer PDS Data master selector DMS Vertex data master VDM Pixel data master PDM General purpose data master USSE Tiling coprocessor Pixel coprocessor Texturing coprocessor Multilevel cache Figure 8 3 shows a block diagram of the SGX cores Figure 8 3 SGX Block Diagram 8 3 2 SGX Elements Description The coarse gr...

Page 1972: ...ading and video imaging processing The multilevel cache is a 2 level cache consisting of two modules the main cache and the mux arbiter demux decompression unit MADD The MADD is a wrapper around the main cache module designed to manage and format requests to and from the cache as well as providing Level 0 caching for texture and USSE requests The MADD can accept requests from the PDS USSE and text...

Page 1973: ...S_RA RW 32 0x0000 FE28 0x5000 FE28 W_1 OCP_IRQSTATUS_RA RW 32 0x0000 FE2C 0x5000 FE2C W_2 OCP_IRQSTATUS_0 RW 32 0x0000 FE30 0x5000 FE30 OCP_IRQSTATUS_1 RW 32 0x0000 FE34 0x5000 FE34 OCP_IRQSTATUS_2 RW 32 0x0000 FE38 0x5000 FE38 OCP_IRQENABLE_SET RW 32 0x0000 FE3C 0x5000 FE3C _0 OCP_IRQENABLE_SET RW 32 0x0000 FE40 0x5000 FE40 _1 OCP_IRQENABLE_SET RW 32 0x0000 FE44 0x5000 FE44 _2 OCP_IRQENABLE_CLR R...

Page 1974: ...e refer to Table 8 3 Description Hardware implementation information Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SYS_BUS_WIDTH MEM_BUS_WIDTH Bits Field Name Description Type Reset 31 3 RESERVED R 0x0000 0000 2 MEM_BUS_WIDTH Memory bus width R Read 0x0 Memory bus width is 64 bits Read 0x1 Memory bus width is 128 bits 1 0 SYS_BUS_WIDTH System...

Page 1975: ...0x1 No Standby mode 0x2 0x3 Smart Standby mode 3 2 IDLE_MODE Clock Idle mode RW 0x2 0x0 Force Idle mode 0x1 No idle mode 0x2 0x3 Smart Idle mode 1 0 RESERVED R 0x0 Table 8 9 Register Call Summary for Register OCP_SYSCONFIG SGX Register Manual SGX OCP Register Summary 0 Table 8 10 OCP_IRQSTATUS_RAW_0 Address Offset 0x0000 FE24 Physical Address Instance SGX Please refer to Table 8 3 Description Raw ...

Page 1976: ...GX Please refer to Table 8 3 Description Raw IRQ 1 Status Slave port interrupt Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TARGET_SINTERRUPT_RAW Bits Field Name Description Type Reset 31 1 RESERVED R 0x0000 0000 0 TARGET_SINTERRUPT_RAW Interrupt 1 slave port raw event RW 0 Write 0x0 no action Read 0x0 no event pending Read 0x1 event pendin...

Page 1977: ...0 Write 0x0 no action Read 0x0 no event pending Read 0x1 event pending Write 0x1 set event used for debug Table 8 15 Register Call Summary for Register OCP_IRQSTATUS_RAW_2 SGX Register Manual SGX OCP Register Summary 0 Table 8 16 OCP_IRQSTATUS_0 Address Offset 0x0000 FE30 Physical Address Instance SGX Please refer to Table 8 3 Description Interrupt 0 Status event Master port interrupt Type RW 31 3...

Page 1978: ...Please refer to Table 8 3 Description Interrupt 1 slave port status event Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TARGET_SINTERRUPT_STATUS Bits Field Name Description Type Reset 31 1 RESERVED R 0x0000 0000 0 TARGET_SINTERRUPT_STATU Interrupt 1 slave port status event RW 0 S Write 0x0 no action Read 0x0 no event pending Read 0x1 event p...

Page 1979: ...vent RW 0 Write 0x0 no action Read 0x0 no event pending Read 0x1 event pending and interrupt enabled Write 0x1 clear event Table 8 21 Register Call Summary for Register OCP_IRQSTATUS_2 SGX Register Manual SGX OCP Register Summary 0 Table 8 22 OCP_IRQENABLE_SET_0 Address Offset 0x0000 FE3C Physical Address Instance SGX Please refer to Table 8 3 Description Enable Interrupt 0 Master port Type RW 31 ...

Page 1980: ...e refer to Table 8 3 Description Enable Interrupt 1 Target port interrupt Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TARGET_SINTERRUPT_ENABLE Bits Field Name Description Type Reset 31 1 RESERVED R 0x0000 0000 0 TARGET_SINTERRUPT_ENABL Enable interrupt 1 slave port interrupt RW 0 E Write 0x0 no action Read 0x0 interrupt is enabled Read 0x1...

Page 1981: ...re interrupt RW 0 Write 0x0 no action Read 0x0 interrupt is enabled Read 0x1 interrupt is disabled Write 0x1 enable interrupt Table 8 27 Register Call Summary for Register OCP_IRQENABLE_SET_2 SGX Register Manual SGX OCP Register Summary 0 Table 8 28 OCP_IRQENABLE_CLR_0 Address Offset 0x0000 FE48 Physical Address Instance SGX Please refer to Table 8 3 Description Disable Interrupt 0 Master port Typ...

Page 1982: ...SGX Please refer to Table 8 3 Description Disable Interrupt 1 slave port Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TARGET_SINTERRUPT_DISABLE Bits Field Name Description Type Reset 31 1 RESERVED R 0x0000 0000 0 TARGET_SINTERRUPT_DISAB Disable interrupt 1 slave port RW 0 LE Write 0x0 no action Read 0x0 interrupt is enabled Read 0x1 interru...

Page 1983: ...interrupt RW 0 Write 0x0 no action Read 0x0 interrupt is enabled Read 0x1 interrupt is disabled Write 0x1 disable interrupt Table 8 33 Register Call Summary for Register OCP_IRQENABLE_CLR_2 SGX Register Manual SGX OCP Register Summary 0 Table 8 34 OCP_PAGE_CONFIG Address Offset 0x0000 FF00 Physical Address Instance SGX Please refer to Table 8 3 Description Configure memory pages Type RW 31 30 29 2...

Page 1984: ...gister Summary 0 Table 8 36 OCP_INTERRUPT_EVENT Address Offset 0x0000 FF04 Physical Address Instance SGX Please refer to Table 8 3 Description Interrupt events Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED INIT_RESP_ERROR INIT_RESP_UNUSED_TAG INIT_RESP_UNEXPECTED TARGET_CMD_FIFO_FULL TARGET_RESP_FIFO_FULL INIT_PAGE_CROSS_ERROR TARGE...

Page 1985: ...vent and interrupt if enabled debug only 3 INIT_PAGE_CROSS_ERROR Memory page had been crossed during a burst RW 0 Write 0x0 clear the event Read 0x0 no event pending Read 0x1 event pending Write 0x1 set event and interrupt if enabled debug only 2 INIT_RESP_ERROR Receiving error response RW 0 Write 0x0 clear the event Read 0x0 no event pending Read 0x1 event pending Write 0x1 set event and interrup...

Page 1986: ...connect protocol should act on RW 0 0 0x0 Whole SGX Idle 0x1 OCP initiator idle only 4 FORCE_PASS_DATA Forces the initiator to pass data independent of RW 0 disconnect protocol 0x0 Normal mode Don t force 0x1 Never fence request to OCP 3 2 FORCE_INIT_IDLE Forces the OCP master port to Idle RW 0x0 0x0 Normal mode no force 0x1 Force port to be always Idle 0x2 Forces target port to never be in Idle m...

Page 1987: ...FIFO_FULL Target response FIFO full R 27 CMD_FIFO_FULL Target command FIFO full R 26 RESP_ERROR Respond to OCP with error which could be caused by R either address misalignment or invalid byte enable 25 21 WHICH_TARGET_REGISTER Indicates which OCP target registers to read RW 0bxxxxx 20 18 TARGET_CMD_OUT Command received from OCP R 0bxxx Read 0x0 Command WRSYS received Read 0x1 Command RDSYS receiv...

Page 1988: ...e is M_CON 7 6 TARGET_SIDLEACK Acknowledge the SIdleAck state machine R 0bxx Read 0x0 State is FUNCT Read 0x1 State is SLEEP TRANS Read 0x2 Reserved Read 0x3 State is IDLE 5 4 TARGET_SDISCACK Acknowledge the SDiscAck state machine R 0bxx Read 0x0 State is FUNCT Read 0x1 State is TRANS Read 0x2 Reserved Read 0x3 State is IDLE 3 TARGET_SIDLEREQ Request the target to go idle R Read 0x0 Don t go idle ...

Page 1991: ... trademarks of Sonics Inc All such materials and trademarks are used under license from Sonics Inc For additional information see the SonicsMX or Sonics3220 Reference manuals or contact Sonics Inc SMX is an abbreviation for SonicsMX NOTE This chapter gives information about all modules and features in the high tier device To flag interconnect response being blocked the time out of target agents at...

Page 1992: ...vior is not associated to a precise OCP transaction or dataflow The OCP standard does not define specific semantics for these signals Out of band error Any OCP signal whose behavior is associated to an error reporting scheme of the device as opposed to in band errors NOTE Interrupt requests and DMA requests are not routed by the interconnect in the device Firewall A programmable feature integrated...

Page 1993: ... Opcode fetch MReqSupervisor 0 User mode 1 Supervisor mode MReqDebug 0 Functional access 1 Debug access L3_PM_REQ_INFO_PERMISSION_i Register that configures the combination of the MReqInfo allowing access permission to the TM based on the MReqInfo in band qualifier values SError Target that indicates an error condition to the initiator SResp qualifier Response from the target to the initiator conc...

Page 1994: ...an overview of the L3 and L4 interconnect architecture L3 handles many types of data transfers especially exchanges with system on chip external memories L3 transfers data with a maximum width of 64 bits from the initiator to the target The L3 interconnect is a little endian platform L4 is composed of the L4 Core L4 Per L4 Wakeup and L4 Emu interconnects and handles data transfers to peripherals I...

Page 1995: ...1 McBSP5 GPTIMER10 GPTIMER11 MAILBOX McSPI1 McSPI2 McSPI3 McSPI4 MMC SD SD SDIO1 MMC SD SDIO2 RNG HDQ 1 Wire ICR camera ISP MODEM INTC SR1 SR2 MPU INTC MMC SD SDIO3 L4 interconnect emulation L4 interconnect wake up GPTIMER1 WDT2 GPIO1 32KTIMER External peripherals ports External and stacked memories External peripherals ports L3 interconnect Firewall L4 HS USB HOST L4 L4 L4 L4 OCM RAM Emulation tr...

Page 1996: ...get agents L4 Per initiator and target agents L4 Emu initiator and target agents L4 Wakeup initiator and target agents 9 1 3 1 L3 Interconnect Agents Table 9 4 and Table 9 5 list the IAs and TAs respectively of the L3 interconnect Table 9 4 L3 Initiator Agents Module Name Description MPU SS MPU subsystem port Display SS Display subsystem port IVA2 2 SS IVA2 2 subsystem port SGX SS Graphics subsyst...

Page 1997: ... UART1 Universal asynchronous receiver transmitter port 1 UART2 Universal asynchronous receiver transmitter port 2 I2C1 Multimaster interintegrated circuit 1 I2C2 Multimaster interintegrated circuit 2 I2C3 Multimaster interintegrated circuit 3 McBSP1 Multichannel buffered serial port 1 McBSP5 Multichannel buffered serial port 5 GPTIMER10 General purpose timer 10 GPTIMER11 General purpose timer 11 ...

Page 1998: ...4 GPTIMER5 General purpose timer 5 GPTIMER6 General purpose timer 6 GPTIMER7 General purpose timer 7 GPTIMER8 General purpose timer 8 GPTIMER9 General purpose timer 9 GPIO2 General purpose I O 2 GPIO3 General purpose I O 3 GPIO4 General purpose I O 4 GPIO5 General purpose I O 5 GPIO6 General purpose I O 6 9 1 3 4 L4 Emu Agents Table 9 10 L4 Emu Initiator Agents Module Name Description L3 interconn...

Page 1999: ...erconnect initiator modules and the L3 and L4 TAs The functional paths are indicated by the use of the following Cell contains a sign when a functional path exists Cell is blank when no functional path exists Table 9 14 Connectivity Matrix Initiator L4 L4 Per L4 L4 SMS GPMC OCM OCM RT IVA2 2 SGX MAD2D Ports Core Target Emu Wakeu Target Target RAM ROM Target Target Target Target 1 Target p Target T...

Page 2001: ...nterconnect Figure 9 2 shows the L3 interconnect Figure 9 2 L3 Interconnect Overview The following are the main features of the L3 interconnect 64 bit multipath interconnect to eliminate on chip bottlenecks Special internal target for access to L3 registers RT Guaranteed quality of service for real time hardware operators while maintaining optimal memory latency for MPU accesses to memory resource...

Page 2002: ...tware reset for the L3 interconnect Table 9 16 L3 Interconnect Reset Type Reset Domain Source Description Hardware CORE_RST PRCM Asynchronous reset for the entire interconnect 9 2 2 1 3 Power Domain The L3 interconnect connects into the CORE power domain which can dynamically switch between supported OPPs For more details on power voltage scaling see Power Reset and Clock Management Table 9 17 L3 ...

Page 2003: ...cluding the following Initiator source identification for the protection mechanism see Section 9 2 3 3 L3 Protection and Firewalls Response route generation performed internally to the TAs Firewall error logging L3 interconnect error logging Table 9 19 InitiatorID Definition Initiator InitiatorID HS USB Host 0 HS USB OTG 2 sDMA rd 3 4 5 6 sDMA wr 7 8 DAP 9 CAM 10 11 12 SGX 13 IVA2 2 SS DMA 14 15 1...

Page 2004: ...elects one table entry of the firewall look up table The region ID points to a unique set of permission registers Read_Permission Write_Permission ReqInfo_Permission The Initiator ID is used to determine the permission of the initiator read write permission with respect to the concerned region The access types read or write and the transaction attributes MReqInfo in band qualifiers are used to gra...

Page 2005: ...memory space Software must configure the L3 firewalls properly to allow the right initiators with the right MReqInfo access on the well defined size region All the registers relative to the L3 firewalls are grouped in the protection mechanism PM register block NOTE The PM qualifies the protection mechanism register associated with a firewall target The targets protected by a firewall are listed in...

Page 2006: ...t including all of ADDR_SPACE It is not possible to program multiple ADDR_SPACE addresses in a normal region 9 2 3 3 1 2 Normal Regions Normal regions have identical features A given request either maps into a specific protection region or is considered to have hit the default protection region if no normal region is hit The protection regions can only be configured for a memory space that is powe...

Page 2007: ...st not be changed otherwise the result will be unpredictable and can create unexpected protection holes or denial of service Protection level is defined by the LEVEL bit L3_PM_ADDR_MATCH_k where n is greater than 2 Figure 9 5 represents the priority level with associated regions When an address hits two or more regions with different priority levels the highest priority region protections are appl...

Page 2008: ...0 4 Set up all region control registers with the new configuration The final programming must be the L3_PM_ADDR_MATCH_k register which includes the size parameter to enable the region 5 Disable the high priority region by setting its size to 0 This procedure must be used each time there is an overlap between the originally defined region and the newly defined region The use of a high priority regi...

Page 2009: ...rite permission are configured using two registers L3_PM_READ_PERMISSION_i L3_PM_WRITE_PERMISSION_i The L3_PM_READ_PERMISSION_i and L3_PM_WRITE_PERMISSION_i registers allow the setting of read and write permission to one or more initiators To grant read or write access set the bit associated with the initiator to 1 2009 SWPU177N December 2009 Revised November 2010 Interconnect Copyright 2009 2010 ...

Page 2010: ...d the Reqbit associated with it Table 9 22 MReqInfo Parameter Combinations Reqbit MReqInfo MReqSupervisor MReqDebug MReqType 0 User Functional Data 1 User Functional Code 2 User Debug Data 3 User Debug Code 4 Reserved for non GP devices 5 Reserved for non GP devices 6 Reserved for non GP devices 7 Reserved for non GP devices 8 Supervisor Functional Data 9 Supervisor Functional Code 10 Supervisor D...

Page 2011: ...ion Field Modifiability Comments Name Region 0 This region is the default region L3_PM_ADDR_MATCH_k ADDR_SPACE 2 0 Hard coded Corresponds to all the target The default setting k 0 memory space can be changed SIZE 7 3 Hard coded Corresponds to all the target only with correct memory space access according to L3 RT register Reserved Default region Level 0 BASE_ADDR 63 10 Hard coded Target dependent ...

Page 2012: ...tion See Table 9 1 REGION 6 4 Read only Log the region number targeted by the request that caused the protection violation INITIATOR_ID 15 8 Read only Log the InitiatorID request that caused the protection violation See Table 9 19 REQ_INFO 20 16 Read only Log the MReqInfo bits of the request that caused the protection violation See Table 9 22 CODE 27 24 Read write Log the error that occurred See T...

Page 2013: ...able 9 3 This error is nonspecific and further analysis is required to find its cause SError This out of band qualifier reports that the target is denied service due to an internal cause No further analysis can be done in the L3 itself Errors detected by the L3 interconnect Unsupported command This error repports that the initiator sent a command that cannot be processed because the target cannot ...

Page 2014: ...n violation TA request time out target core error Sideband interconnect FLAG_STATUS_0 FLAG_STATUS_1 Target module MPU SS DSP SS INTC EMU INTC EMU Functionnal flag Debug flag CONTROL_SEC_ ERR_STATUS SCM L3 AGENT_CONTROL ALL_INBAND_ ERROR_REP intc 023 Public Version L3 Interconnect www ti com transaction to allow traffic from other initiators to resume Burst close is logged in the interconnect TA wh...

Page 2015: ...errors request response and burst are persistent and require the software to reset both the module and the agent No request can be processed in the agent until the reset is performed Other errors affect only the current request Subsequent requests are treated normally Errors are logged however and the information about the error used for debugging is kept until the software acknowledges the error ...

Page 2016: ...t is addressed to the agent internal registers it is processed normally To recover from a time out error the software is assumed to reset first the faulty module using its internal soft reset bit and then the agent using software reset Table 9 27 L3 Timeout Register Target and Agent Programming REQ_TIMEOUT 2 0 BURST_TIMEOUT 2 0 and RESP_TIMEOUT 2 0 TIMEOUT_BASE 2 0 0 1 2 3 4 0 All L3 time out feat...

Page 2017: ...ping it to an interrupt controller All L3 out of band errors are ORed together and the result is transmitted to one or several interrupt controllers All out of band errors are active high and must be acknowledged through a register access to be deasserted Out of band errors are reported through error or flag signals asynchronously to any other data flow but synchronously to the clock All errors ar...

Page 2018: ...equest can be accepted depending on the module and on the error itself These signals are routed as flags internally to the L3 Table 9 28 lists the possible errors reported through an SError propagated externally to the L3 interconnect and aggregated to the L3 application error flag Table 9 28 L3 External Input Flags Target Flag Description Software Visible GPMC SError General purpose error occurs ...

Page 2019: ... are also reported asynchronously to the module Additionally all protection errors even posted writes are seen by the in band to out of band conversion logic in the IAs Therefore all protection errors feed into the L3 application error and L3 debug error composite flags and hence back to the MPU and IVA2 2 subsystems The SMS L4 Core L 4 Per and L4 Emu interconnects have internal firewalls that use...

Page 2020: ... 20 Reserved Reserved 52 Reserved 21 sDMA Wr IA Burst time out 53 Reserved 22 sDMA Wr IA Functional Inband 54 IVA2 2 TA Request time out error 23 Reserved 55 SGX TA Request time out 24 HS USB OTG IA Burst time out 56 SGX TA SError assertion 25 HS USB OTG IA Response time out 57 GPMC TA SError assertion 26 HS USB OTG IA Functional Inband 58 L4 Core TA Request time out error 27 HS USB Host IA Burst ...

Page 2021: ... At the release of power on reset the L3 firewall default configuration enables all accesses to target modules except for a section of the OCM ROM Generally software must configure the firewall properly to avoid poor use of the hardware resources L3 time out capabilities are also disabled at reset 9 2 4 3 Error Analysis The information required to analyze an error source is logged in several regis...

Page 2022: ...g a firewall must be checked No intc 012 Public Version L3 Interconnect www ti com Figure 9 10 Typical Error Analysis Sequence Errors that do not result from an in band to out of band conversion can be extracted immediately from the application or debug error flag by reading the STATUS field L3_SI_FLAG_STATUS_0 63 0 and L3_SI_FLAG_STATUS_1 63 0 register therefore they do not require the whole anal...

Page 2023: ...NDARY bit IA_IVA2 2 L3_IA_ERROR_LOG 30 Value 0x0 The error is functional MULTI bit IA_IVA2 2 L3_IA_ERROR_LOG 31 Value 0x0 No additional error has been detected REQ_INFO field IA_IVA2 2 L3_IA_ERROR_LOG 43 32 Value 0x12 Not applicable for an in band error There is no simple way to determine which target originated the in band error An SError assertion or a request time out would have been detected a...

Page 2024: ...AND_ERROR_PRIMARY In band secondary debug error INBAND_ERROR_SECONDARY Target Target asserts SError SERROR The procedure to clear protection errors depends on the system protection configuration Write a nonzero value simultaneously into CODE bit field L3_PM_ERROR_LOG 27 24 and the value currently stored in the MULTI bit L3_PM_ERROR_LOG 31 of the corresponding PM register block Alternately read eit...

Page 2025: ...ERMISSION_i i 0 0xFFFF PM_IVA2 2 L3_PM_READ_PERMISSION_i i 0 0x140E PM_IVA2 2 L3_PM_WRITE_PERMISSION_i i 0 0x140E Set Region 1 to cover the first 8K bytes of the protected region PM_IVA2 2 L3_PM_ADDR_MATCH_k k 1 0x22 start address 0x0 size 8K bytes address space 2 PM_IVA2 2 L3_PM_REQ_INFO_PERMISSION_i i 1 0x0300 PM_IVA2 2 L3_PM_READ_PERMISSION_i i 1 0x0406 IVA2 2 DMA and MMU and MPU are allowed PM...

Page 2026: ..._INFO_PERMISSION_i i 2 0x0300 PM_IVA2 2 L3_PM_READ_PERMISSION_i i 2 0x0406 IVA2 2 DMA and MMU and MPU are allowed PM_IVA2 2 L3_PM_WRITE_PERMISSION_i i 2 0x0002 only MPU is allowed to write Set Region 1 to mask the last 2K bytes PM_IVA2 2 L3_PM_ADDR_MATCH_k k 2 0x3812 start address 0x3800 size 2K bytes address space 2 PM_IVA2 2 L3_PM_REQ_INFO_PERMISSION_i i 1 0xFFFF PM_IVA2 2 L3_PM_READ_PERMISSION_...

Page 2027: ... 003 Public Version www ti com L3 Interconnect Figure 9 12 Firewall Configuration Solution 2 2027 SWPU177N December 2009 Revised November 2010 Interconnect Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2028: ...SS 0x6800 5400 1K byte IA_CAM 0x6800 5800 1K byte IA_DAP 0x6800 5C00 1K byte TA_IVA2 2 0x6800 6000 1K byte TA_SGX 0x6800 6400 1K byte TA_L4_CORE 0x6800 6800 1K byte TA_L4_PER 0x6800 6C00 1K byte TA_L4_EMU 0x6800 7000 1K byte PM_RT 0x6801 0000 1K byte PM_GPMC 0x6801 2400 1K byte PM_OCM_RAM 0x6801 2800 1K byte PM_OCM_ROM 0x6801 2C00 1K byte PM_IVA2 2 0x6801 4000 1K byte 9 2 5 1 L3 Initiator Agent L3...

Page 2029: ...4428 0x6800 3028 L3_IA_ERROR_LOG RW 64 0x058 0x6800 4058 0x6800 4458 0x6800 3058 L3_IA_ERROR_LOG_ADDR R 64 0x060 0x6800 4060 0x6800 4460 0x6800 3060 Table 9 36 Initiator Agent Common Register Summary Register Name Type Register Address IA_sDMA_RD IA_sDMA_WR Width Offset Physica Physical Bits Address Address L3_IA_COMPONENT R 64 0x000 0x6800 4C00 0x6800 5000 L3_IA_CORE R 64 0x018 0x6800 4C18 0x6800...

Page 2030: ...s Offset 0x018 Physical Address See Table 9 34 to Table 9 37 Description Core register of L3 IA block Type R 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Reserved VENDOR_CODE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CORE_CODE REV_CODE Bits Field Name Description Type Reset 63 48 Reserved Reserved R 0x00...

Page 2031: ... INBAND_ERROR_PRIMARY_REP Reporting of in band errors indicating application error RW 1 0x0 No special reporting 0x1 Report error 27 ALL_INBAND_ERROR_REP Reporting of all in band errors RW 1 0x0 Only report errors that cannnot be reported in band 0x1 Report all in band errors 26 BURST_TIMEOUT_REP Open burst and ReadEx Write timeout reporting RW 1 0x0 No special reporting 0x1 Report out of band 25 ...

Page 2032: ... control active Table 9 43 Register Call Summary for Register L3_IA_AGENT_CONTROL L3 Interconnect Error Steering 0 1 2 Time Out Handling 3 Acknowledging Errors 4 L3 Initiator Agent L3 IA 5 6 7 8 Table 9 44 L3_IA_AGENT_STATUS Address Offset 0x028 Physical Address See Table 9 34 to Table 9 37 Description Agent Status Register Type RW 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 ...

Page 2033: ...or all instances Reserved R 0x0000 except 14 SGX 23 17 Reserved Reserved R 0x0 16 BURST_TIMEOUT Status of open burst and R 0 15 12 TIMEBASE Observation of timebase signals for internal verification R 0x0 11 9 Reserved Reserved R 0x0 8 RESP_TIMEOUT Response timeout status R 0 Reserved for instances 3 6 to Reserved R 0 10 and 12 7 READEX Status of ReadEx Write R 0 6 BURST Status of open burst R 0 5 ...

Page 2034: ...Read 0x0 Multiple error not seen Write 0x1 Clear MULTI flag Read 0x1 Multiple error seen 30 SECONDARY Indicates whether error was primary or secondary RW 0 Write 0x0 Ignored Read 0x0 Primary Error Write 0x1 Reset SECONDARY field Read 0x1 Secondary Error 29 28 Reserved Reserved R 0x0 27 24 CODE Error code RW 0x0 23 16 Reserved Reserved R 0x00 15 8 INITID Initiator ID from which the command was laun...

Page 2035: ..._GPMC module On chip memory RAM TA_OCM_RAM module On chip memory ROM TA_OCM_ROM module Master D2D TA_MAD2D module IVA2 2 subsystem TA_IVA2 2 module SGX subsystem TA_SGX module L4 Core interconnect TA_L4_CORE module L4 Per interconnect TA_L4_PER module L4 Emu interconnect TA_L4_EMU module Table 9 50 through Table 9 53 lists all initiator target registers and their physical addresses depending on th...

Page 2036: ...mmary Register Name Type Register TA_L4_CORE TA_L4_PER TA_L4_EMU Width Bits Physical Physical Physical Address Address Address L3_TA_COMPONENT R 64 0x6800 6800 0x6800 6C00 0x6800 7000 L3_TA_CORE R 64 0x6800 6818 0x6800 6C18 0x6800 7018 L3_TA_AGENT_CONTROL RW 64 0x6800 6820 0x6800 6C20 0x6800 7020 L3_TA_AGENT_STATUS RW 64 0x6800 6828 0x6800 6C28 0x6800 7028 L3_TA_ERROR_LOG RW 64 0x6800 6858 0x6800 ...

Page 2037: ...ype Reset 63 48 Reserved Reserved R 0x0000 47 32 VEND_CODE Vendor Code R See 1 31 16 CORE_CODE Core code R See 1 15 0 REV_CODE Revision Code R See 1 1 TI Internal Data Table 9 57 Register Call Summary for Register L3_TA_CORE L3 Interconnect L3 Target Agent L3 TA 0 1 2 3 Table 9 58 L3_TA_AGENT_CONTROL Address Offset 0x020 Physical Address See Table 9 50 to Table 9 53 Description Agent control regis...

Page 2038: ... requests to this target 3 1 Reserved Reserved R 0x0 0 CORE_RESET Reset output on core RW 0 0x0 Inactive 0x1 Reset control active Table 9 59 Register Call Summary for Register L3_TA_AGENT_CONTROL L3 Interconnect Error Steering 0 1 Acknowledging Errors 2 L3 Target Agent L3 TA 3 4 5 6 Table 9 60 L3_TA_AGENT_STATUS Address Offset 0x028 Physical Address See Table 9 50 to Table 9 53 Description Agent S...

Page 2039: ...s outstanding R 0 Read 0x0 No responses outstanding Read 0x1 Response outstanding in the target 4 REQ_WAITING Requests waiting R 0 Read 0x0 No request waiting Read 0x1 Request waiting for acceptance by target 3 1 Reserved Reserved R 0x0 0 CORE_RESET Reset input from core interface R 0 Read 0x0 Reset inactive Read 0x1 Reset active Table 9 61 Register Call Summary for Register L3_TA_AGENT_STATUS L3 ...

Page 2040: ...R_LOG_ADDR Address Offset 0x060 Physical Address See Table 9 50 to Table 9 53 Description Error log address register of TA block Type RW 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Bits Field Name Description Type Reset 63 32 Reserved Reserved R 0x...

Page 2041: ...9 8 7 6 5 4 3 2 1 0 CODE REV Bits Field Name Description Type Reset 63 32 Reserved Reserved R 0x00000000 31 16 CODE Component Code R See 1 15 0 REV Revision of the component R See 1 1 TI Internal Data Table 9 68 Register Call Summary for Register L3_RT_COMPONENT L3 Interconnect Register Target RT 0 Table 9 69 L3_RT_NETWORK Address Offset 0x010 Physical Address 0x6800 0010 Instance RT Description T...

Page 2042: ...0000000000 7 0 INITID Returns initiator ID of core thread that initiated the read R 0x18 Table 9 72 Register Call Summary for Register L3_RT_INITID_READBACK L3 Interconnect Register Target RT 0 Table 9 73 L3_RT_NETWORK_CONTROL Address Offset 0x068 Physical Address 0x6800 0078 Instance RT Description It controls such interconnect wide functions as the timeout base scale and the disabling of fine gr...

Page 2043: ...module General purpose memory controller PM_GPMC module On chip RAM PM_OCM_RAM module On chip ROM PM_OCM_ROM module IVA2 2 subsystem PM_IVA2 2 module Table 9 75 and Table 9 77 list the protection registers and their physical addresses depending on the module instance Table 9 78 through Table 9 88 describe the individual common registers in the module instance Table 9 75 Protection Mechanism Common...

Page 2044: ...6801 4020 L3_PM_CONTROL RW 64 0x6801 3028 0x6801 4028 L3_PM_ERROR_CLEAR_SINGLE R 64 0x6801 3030 0x6801 4030 L3_PM_ERROR_CLEAR_MULTI R 64 0x6801 3038 0x6801 4038 L3_PM_REQ_INFO_PERMISSION_i 1 RW 64 0x6801 3048 0x20 i 0x6801 4048 0x20 i L3_PM_READ_PERMISSION_i 1 RW 64 0x6801 3050 0x20 i 0x6801 4050 0x20 i L3_PM_WRITE_PERMISSION_i 1 RW 64 0x6801 3058 0x20 i 0x6801 4058 0x20 i L3_PM_ADDR_MATCH_k 2 RW ...

Page 2045: ...Register L3_PM_ERROR_LOG L3 Interconnect L3 Firewall Error Logging Registers 0 Time Out Handling 1 2 3 4 Acknowledging Errors 5 6 7 Protection Mechanism PM 8 9 10 Table 9 80 L3_PM_CONTROL Address Offset 0x28 Physical Address See Table 9 75 to Table 9 77 Description This register controls protection mechanism functions such as error reporting Type RW 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ...

Page 2046: ...Field Name Description Type Reset 63 1 Reserved Reserved R 0x0000000000000000 0 CLEAR Clear single error from log R 0 Table 9 83 Register Call Summary for Register L3_PM_ERROR_CLEAR_SINGLE L3 Interconnect Acknowledging Errors 0 Protection Mechanism PM 1 2 3 Table 9 84 L3_PM_ERROR_CLEAR_MULTI Address Offset 0x38 Physical Address See Table 9 75 to Table 9 77 Description Read to clear multiple errors...

Page 2047: ...eserved R 0x000000000000 15 0 REQ_INFO Request info permission bits for region i see Table 9 22 for RW See Table 9 88 bitfield description Table 9 87 Register Call Summary for Register L3_PM_REQ_INFO_PERMISSION_i Interconnect Overview Terminology 0 L3 Interconnect REQ_INFO_PERMISSION Configuration 1 2 3 4 5 L3 Firewall Registers Overview 6 7 Typical Example of Firewall Programming Example 8 9 10 1...

Page 2048: ... the DAP RW See Table 9 93 11 CAM Read permission for the CAMERA SS RW See Table 9 93 10 IVA2_MMU Read permission for the IVA2 MMU RW See Table 9 93 9 USB_HS_Host Read permission for the USB_HS_Host RW See Table 9 93 8 DISPSS Write permission for the DISPLAY SS RW See Table 9 93 7 6 Reserved Reserved RW 0x0 5 SAD2D Read permission for the SAD2D RW See Table 9 93 4 USB_HS_OTG Read permission for th...

Page 2049: ... 9 93 10 IVA2_MMU Write permission for the IVA2 MMU RW See Table 9 93 9 USB_HS_Host Write permission for the USB_HS_Host RW See Table 9 93 8 DISPSS Write permission for the DISPLAY SS RW See Table 9 93 7 6 Reserved Reserved RW 0x0 5 SAD2D Write permission for the SAD2D RW See Table 9 93 4 USB_HS_OTG Write permission for the USB_HS_OTG RW See Table 9 93 3 SDMA Write permission for the system DMA RW...

Page 2050: ...0000000000 PM_GPMC region 0 to 7 1 1 1 1 1 N A 1 1 N A 1 1 0x0000000000001 PM_OCM_RAM region 0 1 1 1 1 1 1 1 1 1 1 1 0x0000000000001 to 7 PM_OCM_ROM region 0 1 N A N A N A N A N A N A N A N A 1 N A 0x0000000000000 to 1 ro 1 PM_MAD2D region 0 to 1 1 1 1 N A 1 1 1 1 1 1 0x0000000000001 7 PM_IVA2 2 region 0 to 3 1 1 1 N A N A N A N A 1 N A 1 N A 0x0000000000000 1 ROM is a read only memory therefore t...

Page 2051: ..._SPACE Bits Field Name Description Type Reset 63 20 Reserved Reserved R 0x00000000000 19 10 BASE_ADDR Protection region base address R see Table 9 96 9 LEVEL Protection region level R see Table 9 96 8 Reserved Reserved R 0 7 3 SIZE Protection region size R see Table 9 96 2 0 ADDR_SPACE Protection region address space R see Table 9 96 Table 9 95 Register Call Summary for Register L3_PM_ADDR_MATCH_k...

Page 2052: ...0 0x00 0x0 4 0x000 0x0 0x00 0x0 5 0x000 0x0 0x00 0x0 6 0x000 0x0 0x00 0x0 7 0x000 0x0 0x00 0x0 PM_IVA2 1 0x000 0x0 0x00 0x0 2 0x000 0x0 0x00 0x0 3 0x000 0x0 0x00 0x0 9 2 5 5 Sideband Interconnect SI This section describes the sideband interconnect register block Table 9 97 lists the SI registers and their physical addresses Table 9 98 through Table 9 102 describe the individual registers in the mo...

Page 2053: ...gating disabled 55 0 Reserved Reserved for future use R 0x00000000000000 Table 9 99 Register Call Summary for Register L3_SI_CONTROL L3 Interconnect Sideband Interconnect SI 0 Table 9 100 L3_SI_FLAG_STATUS_0 Address Offset 0x110 Physical Address 0x6800 0510 Instance SI Description They are used to observe the individual bits that make up a composite interconnect flag Type R 63 62 61 60 59 58 57 56...

Page 2054: ...3 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 STATUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STATUS Bits Field Name Description Type Reset 63 0 STATUS Status of sideband signals making up composite interconnect flag for R 0x0000000000000000 debug See Table 9 30 Table 9 103 Register Call Summary for Regis...

Page 2055: ...ngle or burst transactions Little endian Nonblocking with fair arbitration between threads Peripherals are not burst capable the system initiators can address bursts to them but the L4 interconnect breaks the bursts into single accesses Target interfaces Fully synchronous or divided synchronous Peak bandwidth of L4 interconnect is 1 MBps L4 frequency in MHz per L4 thread that is 100 MBps when the ...

Page 2056: ...L4 interconnects in the overall interconnect This architecture with only one initiator module the initiator subsystem distributing transactions to all target modules peripherals enables the firewall functions of the L4 interconnects to be centralized at the L4 initiator level The L4 firewall filters the accesses according to the configurable protection groups defined in the L4 address protection A...

Page 2057: ...memory controller SDIO 2 MMC3 Multimedia memory controller SDIO 3 HDQ 1 Wire Single wire serial link low rate MLB mailbox Mailbox MCSPI1 Serial peripheral interface 1 MCSPI2 Serial peripheral interface 2 MCSPI3 Serial peripheral interface 3 MCSPI4 Serial peripheral interface 4 SR1 SmartReflex1 SR2 SmartReflex2 sDMA System DMA controller L4 Wakeup L4 Wakeup interconnect CM Clock manager SCM System ...

Page 2058: ... Per targets For the list of initiators authorized to access the L4 Per peripherals see Table 9 14 For details on restricted access see Section 9 3 3 3 1 Protection Mechanism 9 3 1 3 L4 Emu Interconnect The L4 Emu interconnect handles only transfers to peripherals in the EMU power domain Table 9 106 lists the TAs Table 9 106 L4 Emu Target Agents Module Name Description L4 Wakeup L4 Wakeup intercon...

Page 2059: ...IMER1 General purpose timer 1 WDTIMER2 MPU subsystem watchdog timer 32KTIMER 32 kHz timer Initiators that can access the L4 Core or L4 Emu can access all the targets in the L4 Wakeup interconnect Table 9 109 lists the initiators that can access the L4 Wakeup interconnect For details on restricted access see Section 9 3 3 3 1 Protection Mechanism Table 9 109 L4 Wakeup Initiator Agents Module Name D...

Page 2060: ...eset and Clock Management Table 9 111 lists the hardware reset for the L4 Core interconnect Table 9 111 L4 Interconnect Hardware Reset Interconnect Reset Domain L4 Core interconnect CORE_RST L4 Per interconnect PER_RST L4 Wakeup interconnect WKUP_RST L4 Emu interconnect EMU_RST 9 3 2 1 2 2 Software Reset The L4 interconnects have hardware reset capabilities but do not have software reset capabilit...

Page 2061: ...h L4 interconnects are little endian only Any initiator accessing the L4 interconnect module must consider byte ordering and perform a conversion if necessary 9 3 3 3 L4 Protection and Firewalls 9 3 3 3 1 Protection Mechanism The following two parameters are used to set up access permission because of the large address spaces and the number of peripherals connected to the L4 interconnects Programm...

Page 2062: ...bit in this register determines the type of access allowed to the initiator See Section 9 2 3 3 4 REQ_INFO_PERMISSION Configuration for more information MReqInfo is used in L4 the same way it is used in the L3 firewall configuration NOTE Permissions are identical for read and write accesses in L4 interconnect targets Figure 9 15 shows an example of CONNID_BIT_VECTOR Figure 9 15 Example of CONNID_B...

Page 2063: ...ontains six protection groups By default most regions are set with PG5 which is configured for all access see Table 9 115 The AP is attached to PG0 The emulation organs are attached to PG3 9 3 3 3 3 Segments and Regions The protection mechanism for L4 interconnects is based on a hierarchical segmentation see Figure 9 16 By default some regions are attached to a specific protection group This speci...

Page 2064: ...onnects www ti com Figure 9 16 L4 Firewall Overview All interconnect address spaces are covered by regions Table 9 113 to Table 9 115 list the module mapping including the address region number and default protection group allocated to it By setting ENABLE bit L4_AP_REGION_y_H 0 to 0 the region becomes inactive and therefore inaccessible Setting the bit to 1 activates the region Table 9 113 Region...

Page 2065: ... interconnect 7 2 Reserved 0x4805 2000 Reserved sDMA 0x4805 6000 Module 9 7 0x4805 7000 L4 interconnect 10 7 0x4805 8000 0x4805 9000 Reserved 0x4805 A000 Reserved 0x4805 B000 0x4805 C000 Reserved 0x4805 D000 Reserved I2C3 0x4806 0000 Module 73 7 0x4806 1000 L4 interconnect 74 7 USBTLL 0x4806 2000 Module 100 7 0x4806 3000 L4 interconnect 101 7 USBHS Host 0x4806 4000 Module 15 7 0x4806 5000 L4 inter...

Page 2066: ...OTG 0x480A B000 Module 13 7 0x480A C000 L4 interconnect 14 7 MMC SD SDIO3 0x480A D000 Module 98 7 0x480A E000 L4 interconnect 99 7 0x480B 0000 Reserved Reserved 0x480B 1000 HDQ 1 Wire 0x480B 2000 Module 57 7 0x480B 3000 L4 interconnect 58 7 MMC SD SDIO2 0x480B 4000 Module 41 7 0x480B 5000 L4 interconnect 42 7 ICR 0x480B 6000 Module 88 7 0x480B 7000 L4 interconnect 89 7 MCSPI3 0x480B 8000 Module 66...

Page 2067: ...d 0x4900 2000 Reserved UART3 0x4902 0000 Module 3 7 Infrared 0x4902 1000 L4 interconnect 4 7 McBSP2 0x4902 2000 Module 5 7 Audio for codec 0x4902 3000 L4 interconnect 6 7 McBSP3 0x4902 4000 Module 7 7 Bluetooth voice data 0x4902 5000 L4 interconnect 8 7 McBSP4 digital base 0x4902 6000 Module 9 7 band voice data 0x4902 7000 L4 interconnect 10 7 McBSP2 Sidetone 0x4902 8000 Module 39 7 0x4902 9000 L4...

Page 2068: ...eserved Table 9 115 Region Allocation for L4 Emu Interconnect Device Name Start Address Description Region Number Default hex Protection Group Reserved 0x5400 0000 Reserved TEST Chip level TAP 0x5400 4000 Module 1 5 0x5400 5000 L4 interconnect 2 5 L4 Emu configuration 0x5400 6000 Address protection AP 3 0 0x5400 6800 Initiator port IP L4 Core 4 5 0x5400 7000 Link agent LA 5 5 0x5400 8000 Initiator...

Page 2069: ...ved 0x5472 2000 Reserved L4 Wakeup configuration WKUP 0x5472 8000 Address protection AP power domain 0x5472 8800 Initiator port IP L4 Core 24 5 0x5472 9000 Link agent LA 0x5472 A000 Initiator port IP L4 Emu Reserved 0x5472 A800 Reserved L4 Wakeup 0x5473 0000 L4 interconnect 25 5 9 3 3 3 4 L4 Firewall Address and Protection Registers Setting Table 9 116 lists the settings of the AP registers for an...

Page 2070: ...dered L4 Core L4 Per L4 Emu or L4 Wakeup L4_TA denotes the module name such as UART1 McBSP1 etc The L4 interconnects handle three types of errors No target core found or address hole Request protection violation Failure of the target to service a request before a time out expires 9 3 3 4 2 Error Logging 9 3 3 4 2 1 No Target Core Found Address Hole This error indicates that a request was addressed...

Page 2071: ...at broadcasts a set of four periodic pulse signals to all connected TAs These four signals are referred to as 1X time base 4X time base 16X time base and 64X time base The time base circuit offers four possible sets of time base signals Selection is done by programming TIMEOUT_BASE field L4_LA_NETWORK_CONTROL_L 10 8 Table 9 117 lists the values in the number of L4 clock cycles Table 9 117 L4 Time ...

Page 2072: ...ET bit L4_TA_AGENT_CONTROL_L 0 9 3 3 4 3 TA Software Reset Writing 1 to OCP_RESET bit L4_TA_AGENT_CONTROL_L 0 initiates the software reset period The software reset must be asserted for at least 16 cycles of the target module OCP clock which can be a divided clock with respect to the L4 clock During the software reset period the following occur Requests sent to the target module receive error resp...

Page 2073: ... 1 1 Surrounding Modules Global Initialization This section identifies the requirements for initializing the surrounding modules when the L4 interconnect module is to be used for the first time after a device reset This initialization of surrounding modules is based on the integration and environment of the L4 interconnect For more information see L4 Interconnect Integration Table 9 119 Global Ini...

Page 2074: ... 9 3 4 1 2 1 1 Main Sequence L4 Interconnect Error Analysis Mode The information required to analyze an error source is logged in several registers The number of registers to access depends on the error source Figure 9 18 and Figure 9 19 show the software sequence required in most cases Table 9 120 and Table 9 121 show the main sequence for error analysis mode and its subprocess call summary respe...

Page 2075: ...Public Version www ti com L4 Interconnects Figure 9 18 Typical Error Analysis Sequence 2075 SWPU177N December 2009 Revised November 2010 Interconnect Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2076: ...rocess Cross Reference L3 interconnect error analysis Section 9 2 3 4 Error Handling L4 interconnect protection violation error identification Section 9 3 4 1 2 1 2 Subsequence L4 Interconnect Protection Violation Error Identification L4 interconnect unsupported command address hole error Section 9 3 4 1 2 1 3 Subsequence L4 Interconnect identification Unsupported Command Address Hole Error Identi...

Page 2077: ...cribes the identification of unsupported command address hole error see Table 9 123 Table 9 123 Unsupported Command Address Hole Error Identification Step Register Bit Field Programming Model Value Read multiple errors detection L4_IA_ERROR_LOG_L 31 MULTI Read initiator error code L4_IA_ERROR_LOG_L 25 24 CODE Write 1 to clear multiple errors detection L4_IA_ERROR_LOG_L 31 MULTI 0x1 Write 1 to clea...

Page 2078: ...up 2 L4_AP_REGION_l_L 22 20 PROT_GROUP_ID xxx 1 Must be done for each protection group 2 Must be done for each region 9 3 5 L4 Interconnects Register Manual A summary of the hardware interface for the L4 Core L4 Per L4 Emu and L4 Wkup interconnects is given in Table 9 127 through Table 9 130 respectively Each module instance in the design is shown with the module register map and bit definitions f...

Page 2079: ...2K bytes PER_IA 0x4900 0800 2K bytes PER_LA 0x4900 1000 4K bytes PER_TA_UART3 0x4902 1000 512 bytes PER_TA_MCBSP2 0x4902 3000 1K byte PER_TA_MCBSP3 0x4902 5000 1K byte PER_TA_MCBSP4 0x4902 7000 1K byte PER_TA_MCBSP2_SIDETONE 0x4902 9000 4K bytes PER_TA_MCBSP3_SIDETONE 0x4902 B000 4K bytes PER_TA_WDTIMER3 0x4903 1000 2K bytes PER_TA_GPTIMER2 0x4903 3000 1K byte PER_TA_GPTIMER3 0x4903 5000 1K byte P...

Page 2080: ... instance is described seperatly in Table 9 131 to Table 9 132 The initiator OCP interface register block IA consists of the status control and error log registers that can be used to configure the interface of an initiator OCP There can be only one register block for each initiator OCP interface Table 9 131 L4 IA Register Summary 1 Register Name Type Register CORE_IA PER_IA EMU_IA_L3 Width Physic...

Page 2081: ... 9 132 Description COMPONENT register identifies the component to which this register block belongs The register contains a component code and revision which are used to identify the hardware of the component The COMPONENT register is read only Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CODE REV Bits Field Name Description Type Reset 31 16 CODE Int...

Page 2082: ...ct core code R See 1 15 0 CORE_REV Component revision code code R See 1 1 TI Internal data Table 9 138 Register Call Summary for Register L4_IA_CORE_L L4 Interconnects L4 Iniator Agent L4 IA 0 1 Table 9 139 L4_IA_CORE_H Address Offset 0x01C Physical Address SeeTable 9 131 to Table 9 132 Description Provide information about the core initiator Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 2083: ... INBAND_ERROR log bit of IA AGENT_STATUS register 26 25 Reserved Read returns 0 R 0x0 24 MERROR_REP Enable MError reporting R 0x0 23 0 Reserved Read returns 0 R 0x0000000 Table 9 142 Register Call Summary for Register L4_IA_AGENT_CONTROL_L L4 Interconnects Overview 0 Operational Modes Configuration 1 L4 Iniator Agent L4 IA 2 3 Table 9 143 L4_IA_AGENT_CONTROL_H Address Offset 0x024 Physical Address...

Page 2084: ...REP 0x0 No MError error present R 0x0 0x1 MErorr error present 23 0 Reserved Read returns 0 R 0x0000000 Table 9 146 Register Call Summary for Register L4_IA_AGENT_STATUS_L L4 Interconnects Error Logging 0 Operational Modes Configuration 1 2 3 4 5 L4 Iniator Agent L4 IA 6 7 Table 9 147 L4_IA_AGENT_STATUS_H Address Offset 0x02C Physical Address SeeTable 9 131 to Table 9 132 Description Stores status...

Page 2085: ...request RW 0x0 0x00 No errors 0x01 Reserved 0x10 Address hole 0x11 Protection violation The CODE field once set by hardware can only be cleared by writing a non zero value to it in conjunction with writing a 1 to the MULTI bit field 23 0 Reserved Read returns 0 R 0x000000 Table 9 150 Register Call Summary for Register L4_IA_ERROR_LOG_L L4 Interconnects Error Logging 0 1 2 Operational Modes Configu...

Page 2086: ...its Address Address Address L4_TA_COMPONENT_L R 32 0x4802 7000 0x4805 1000 0x4805 7000 L4_TA_COMPONENT_H R 32 0x4802 7004 0x4805 1004 0x4805 7004 L4_TA_CORE_L R 32 0x4802 7018 0x4805 1018 0x4805 7018 L4_TA_CORE_H R 32 0x4802 701C 0x4805 101C 0x4805 701C L4_TA_AGENT_CONTROL_L RW 32 0x4802 7020 0x4805 1020 0x4805 7020 L4_TA_AGENT_CONTROL_H RW 32 0x4802 7024 0x4805 1024 0x4805 7024 L4_TA_AGENT_STATUS...

Page 2087: ...TA Common Register Summary Register Name Type Register CORE_TA_UART2 CORE_TA_I2C1 CORE_TA_I2C2 Width Physical Physical Physical Bits Address Address Address L4_TA_COMPONENT_L R 32 0x4806 D000 0x4807 1000 0x4807 3000 L4_TA_COMPONENT_H R 32 0x4806 D004 0x4807 1004 0x4807 3004 L4_TA_CORE_L R 32 0x4806 D018 0x4807 1018 0x4807 3018 L4_TA_CORE_H R 32 0x4806 D01C 0x4807 101C 0x4807 301C L4_TA_AGENT_CONTR...

Page 2088: ...20 L4_TA_AGENT_CONTROL_H RW 32 0x4809 9024 0x4809 B024 0x4809 D024 L4_TA_AGENT_STATUS_L RW 32 0x4809 9028 0x4809 B028 0x4809 D028 L4_TA_AGENT_STATUS_H RW 32 0x4809 902C 0x4809 B02C 0x4809 D02C Table 9 162 CORE_TA Common Register Summary Register Name Type Register CORE_TA_USB_HS_OTG Width Bits Physical Address L4_TA_COMPONENT_L R 32 0x480A C000 L4_TA_COMPONENT_H R 32 0x480A C004 L4_TA_CORE_L R 32 ...

Page 2089: ...20 L4_TA_AGENT_CONTROL_H RW 32 0x480B B024 0x480C 0024 0x480C 8024 L4_TA_AGENT_STATUS_L RW 32 0x480B B028 0x480C 0028 0x480C 8028 L4_TA_AGENT_STATUS_H RW 32 0x480B B02C 0x480C 002C 0x480C 802C Table 9 166 CORE_TA Common Register Summary Register Name Type Register CORE_TA_SR1 CORE_TA_SR2 Width Physical Physical Bits Address Address L4_TA_COMPONENT_L R 32 0x480C A000 0x480C C000 L4_TA_COMPONENT_H R...

Page 2090: ...02 B024 L4_TA_AGENT_STATUS_L RW 32 0x4902 7028 0x4902 9028 0x4902 B028 L4_TA_AGENT_STATUS_H RW 32 0x4902 702C 0x4902 902C 0x4902 B02C Table 9 170 PER_TA Common Register Summary Register Name Type Register PER_TA_WDTIMER3 PER_TA_GPTIMER2 Width Physical Physical Bits Address Address L4_TA_COMPONENT_L R 32 0x4903 1000 0x4903 3000 L4_TA_COMPONENT_H R 32 0x4903 1004 0x4903 3004 L4_TA_CORE_L R 32 0x4903...

Page 2091: ...1024 0x4905 3024 L4_TA_AGENT_STATUS_L RW 32 0x4904 1028 0x4904 3028 0x4905 1028 0x4905 3028 L4_TA_AGENT_STATUS_H RW 32 0x4904 102C 0x4904 302C 0x4905 102C 0x4905 302C Table 9 174 PER_TA Common Register Summary Register Name Type Register PER_TA_GPIO4 PER_TA_GPIO5 PER_TA_GPIO6 Width Physical Physical Physical Bits Address Address Address L4_TA_COMPONENT_L R 32 0x4905 5000 0x4905 7000 0x4905 9000 L4...

Page 2092: ...er Name Type Register WKUP_TA_PRM WKUP_TA_GPIO1 WKUP_TA_WDTIMER2 Width Physical Physical Address Physical Address Bits Address L4_TA_COMPONENT_L R 32 0x4830 9000 0x4831 1000 0x4831 5000 L4_TA_COMPONENT_H R 32 0x4830 9004 0x4831 1004 0x4831 5004 L4_TA_CORE_L R 32 0x4830 9008 0x4831 1018 0x4831 5018 L4_TA_CORE_H R 32 0x4830 901C 0x4831 101C 0x4831 501C L4_TA_AGENT_CONTROL_L RW 32 0x4830 9020 0x4831 ...

Page 2093: ...tains a component code and revision Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Field Name Description Type Reset 31 0 Reserved Read returns 0 R 0x0000 000 Table 9 182 Register Call Summary for Register L4_TA_COMPONENT_H L4 Interconnects L4 Target Agent L4 TA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Table 9 1...

Page 2094: ...Register L4_TA_CORE_H L4 Interconnects L4 Target Agent L4 TA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Table 9 187 L4_TA_AGENT_CONTROL_L Address Offset 0x020 Physical Address SeeTable 9 153 to Table 9 178 Description Enable error reporting Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Reserved OCP_RESET SER...

Page 2095: ...ress SeeTable 9 153 to Table 9 178 Description Enable clock power management Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved EXT_CLOCK Bits Field Name Description Type Reset 31 9 Reserved Read returns 0 R 0x000000 8 EXT_CLOCK When set to 1 the ext_clk_off_i signal on a target agent indicates R 0 when the target agent should shut off 7...

Page 2096: ... 24 25 9 3 5 3 L4 Link Register Agent LA This section provides information on the L4 Core link agent LA register module Each of the registers within the module instance is described seperatly in Table 9 195 The LA register blockcontains the initiator subsystem information register and the composite sideband signal mask and status registers Table 9 195 L4 LA Register Summary Register Name Type Regi...

Page 2097: ...s Offset 0x004 Physical Address Please refer to Table 9 195 Description Contain a component code and revision which are used to identify the hardware of the component Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Field Name Description Type Reset 31 0 Reserved Read returns 0 R 0x0000 0000 Table 9 199 Register Call Summary for Register L4...

Page 2098: ...9 8 7 6 5 4 3 2 1 0 Reserved NUMBER_REGIONS Reserved SEGMENTS PROT_GROUPS Bits Field Name Description Type Reset 31 28 Reserved Read returns 0 R 0x0 27 24 PROT_GROUPS The number of protection groups The PROT_GROUPS field contains R see Table 9 206 read only configuration information for the address mapping and protection structure of the initiator subsystem If the PROT_GROUPS field is set to 0 the...

Page 2099: ...em connID width The CONNID_WIDTH field R see Table 9 209 contains read only configuration information for the initiator subsystem 11 Reserved Read returns 0 R 0 10 8 BYTE_DATA_ This field specifies the initiator subsystem data width 1 2 1 bytes R see Table 9 209 WIDTH_EXP specifies a 16 bit data width and 2 2 2 bytes specifies a 32 bit data width The BYTE_DATA_WIDTH_EXP field contains read only co...

Page 2100: ...connect clock cycles divided by 256 3 L4 interconnect clock cycles divided by 1024 4 L4 interconnect clock cycles divided by 4096 7 0 Reserved Read returns 0 R 0x00 Table 9 211 Register Call Summary for Register L4_LA_NETWORK_CONTROL_L L4 Interconnects Error Logging 0 1 Operational Modes Configuration 2 3 L4 Link Register Agent LA 4 Table 9 212 L4_LA_NETWORK_CONTROL_H Address Offset 0x024 Physical...

Page 2101: ... agent LA register module Each of the registers within the module instance is described seperatly in Table 9 214 The AP register block contains the segment address region and protection group registers that can be used to specify the addressing scheme or restrict the access of target address regions Table 9 214 L4 AP Register Summary Register Name Type Register CORE_AP PER_AP Width Physical Physic...

Page 2102: ...o 4 for PER_AP i 0 to 2 for EMU_AP i 0 to 1 for WKUP_AP 2 k 0 to 7 for CORE_AP and PER_AP k 0 to 5 for EMU_AP 3 k 0 to 7 for CORE_AP and PER_AP k 0 to 5 for EMU_AP 4 l 0 to 99 for CORE_AP l 0 to 42 for PER_AP l 0 to 25 for EMU_AP l 0 to 18 for WKUP_AP 9 3 5 4 1 L4 Address Protection AP Registers Description Table 9 216 L4_AP_COMPONENT_L Address Offset 0x000 Physical Address Please refer to Table 9...

Page 2103: ... to Table 9 214 Description Define the base address of each segments Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BASE Bits Field Name Description Type Reset 31 24 Reserved Read returns 0 R 0x00 23 0 BASE The base address of the segment with 0s from bit 0 to bit SIZE 1 R see Table 9 222 Table 9 221 Register Call Summary for Register L4_AP_S...

Page 2104: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SIZE Bits Field Name Description Type Reset 31 5 Reserved Read returns 0 R 0x0000000 4 0 SIZE Segment size is a power of 2 where 2 SIZE is the byte size of a R see Table 9 225 segment all segment registers use the same size Table 9 224 Register Call Summary for Register L4_AP_SEGMENT_i_H L4 Interconnects L4 Firewall Address and Protection Registers Setting 0...

Page 2105: ...al connIDs have their bits set to 0s Table 9 227 Register Call Summary for Register L4_AP_PROT_GROUP_MEMBERS_k_L L4 Interconnects L4 Firewall Address and Protection Registers Setting 0 Operational Modes Configuration 1 L4 Address Protection AP 2 3 Table 9 228 L4_AP_PROT_GROUP_MEMBERS_k_H Address Offset 0x204 0x08 k Index k 0 to 7 for CORE_ AP and PER_AP k 0 to 5 for EMU_AP Physical Address Please ...

Page 2106: ...H Address Offset 0x204 0x08 k Index k 0 to 7 for CORE_ AP and PER_AP k 0 to 5 for EMU_AP Physical Address Please refer to Table 9 214 Description Define connID bit vectors for a protection group Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Field Name Description Type Reset 31 0 Reserved Read returns 0 s R 0x0000 0000 Table 9 233 Registe...

Page 2107: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SEGMENT_ID Reserved SIZE ENABLE Reserved PROT_GROUP_ID BYTE_DATA_WIDTH_EXP Bits Field Name Description Type Reset 31 28 Reserved Read returns 0 R 0x0 27 24 SEGMENT_ID Identifies the segment to which the region is part of R See Table 9 238 to Table 9 241 23 Reserved Read returns 0 R 0 22 20 PROT_GROUP_ID The protecti...

Page 2108: ...0A 5 0x01 0800 1 2 2 0x0A 6 0x01 0C00 1 2 2 0x0A 7 0x01 1000 1 2 2 0X0C 8 0x00 0000 3 3 2 0x0C 9 0x01 6000 1 7 2 0x0C 10 0x01 7000 1 7 2 0x0C 11 0x01 8000 1 7 2 0x0C 12 0x01 C000 1 7 2 0x0C 13 0x02 B000 2 7 2 0x0C 14 0x02 C000 2 7 2 0x0C 15 0x01 E000 1 7 2 0x0C 16 0x01 F000 1 7 2 0x0C 17 0x02 A000 1 7 2 0x0C 18 0x02 B000 1 7 2 0x0C 19 0x02 C000 1 7 2 0X0C 20 0x02 D000 1 7 2 0x0C 21 0x03 0000 1 7 1...

Page 2109: ...0x0C 54 0x02 7000 2 1 2 0x0C 55 0x02 8000 2 1 2 0x0D 56 0x02 A000 2 1 2 0x0C 57 0x03 0000 2 7 2 0x0C 58 0x03 1000 2 7 2 0x0C 59 0x03 2000 2 7 2 0x0C 60 0x03 3000 2 7 2 0x0C 61 0x01 6000 2 7 2 0x0C 62 0x01 7000 2 7 2 0x0C 63 0x01 9000 1 7 2 0x0C 64 0x01 A000 1 7 2 0x0C 65 0x01 B000 1 7 2 0x0C 66 0x03 8000 2 7 2 0x0C 67 0x03 9000 2 7 2 0x0C 68 0x00 4000 0 7 2 0x0C 69 0x00 7000 0 7 2 0x0C 70 0x00 B00...

Page 2110: ...GION_l_L and L4_AP_REGION_l_H y BASE SEGMENT_ID PROT_GROUP_ID BYTE_DATA_WIDTH_EXP SIZE 0 0x00 0000 0 0 2 0x0B 1 0x00 0800 0 7 2 0x0B 2 0x00 1000 0 7 2 0x0C 3 0x00 0000 1 7 2 0x0C 4 0x00 1000 1 7 2 0X0C 5 0x00 2000 1 7 2 0X0C 6 0x00 3000 1 7 2 0X0C 7 0x00 4000 1 7 2 0X0C 8 0x00 5000 1 7 2 0x0C 9 0x00 6000 1 7 2 0x0C 10 0x00 7000 1 7 2 0x0C 11 0x00 0000 1 7 2 0x0C 12 0x00 1000 2 7 2 0x0C 13 0x00 200...

Page 2111: ...GION_l_L and L4_AP_REGION_l_H y BASE SEGMENT_ID PROT_GROUP_ID BYTE_DATA_WIDTH_EXP SIZE 0 0x00 0000 2 5 2 0x14 1 0x00 4000 0 5 2 0x0C 2 0x00 5000 0 5 2 0x0C 3 0x00 6000 0 5 0 0x0B 4 0x00 6800 0 5 2 0x0B 5 0x00 7000 0 5 2 0x0B 6 0x00 8000 0 5 2 0x0C 7 0x01 8000 0 3 2 0x0C 8 0x01 9000 0 3 2 0x0C 9 0x01 A000 0 3 2 0x0C 10 0x01 B000 0 3 2 0x0C 11 0x01 C000 0 3 2 0x0C 12 0x01 D000 0 3 2 0x0C 13 0x01 E00...

Page 2112: ... 4 0x00 D000 0 0 2 0x0C 5 0x01 8000 0 0 2 0x0C 6 0x01 9000 0 0 2 0x0C 7 0x01 4000 0 0 2 0x0C 8 0x01 5000 0 0 2 0x0C 9 0x00 9000 1 0 2 0x0C 10 0x00 4000 0 0 2 0x0C 11 0x00 5000 0 0 2 0x0C 12 0x00 8800 1 0 2 0x0B 13 0x00 8000 0 0 2 0x0B 14 0x01 0000 0 0 2 0x0C 15 0x01 1000 0 0 2 0x0C 16 0x00 0000 1 0 2 0x0C 17 0x00 1000 1 0 2 0x0C 18 0x00 A000 1 0 2 0x0C 2112 Interconnect SWPU177N December 2009 Revi...

Page 2113: ...is chapter describes the memory subsystem Topic Page 10 1 General Purpose Memory Controller 2114 10 2 SDRAM Controller SDRC Subsystem 2223 10 3 On Chip Memory Subsystem 2331 2113 SWPU177N December 2009 Revised November 2010 Memory Subsystem Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2114: ...ices Asynchronous SRAM like memories and application specific integrated circuit ASIC devices Asynchronous synchronous and page mode burst NOR flash devices NAND flash Pseudo SRAM devices Figure 10 1 shows the environment of the GPMC Figure 10 1 GPMC Environment 10 1 1 1 GPMC Features The GPMC is the device 16 bit external memory controller The GPMC data access engine provides a flexible programmi...

Page 2115: ...synchronous or synchronous 16 bit wide memory or device External 16 bit nonmultiplexed device with limited address range 2 Kbytes External 16 bit address data multiplexed NOR flash device External 8 bit and 16 bit NAND flash device External 16 bit pseudo static random access memory pSRAM device The GPMC supports up to eight chip select regions of programmable size and programmable base addresses i...

Page 2116: ...vide the A0 byte address line required for random byte addressable 8 bit wide device interfacing for multiplexed and nonmultiplexed protocol Hence an 8 bit device must be connected to the D 7 0 gpmc_d 7 0 data bus rather than D 15 8 gpmc_d 15 8 of the GPMC controller This limits the use of 8 bit wide device interfacing to byte alias accesses Table 10 1 lists the GPMC subsystem I O pins Table 10 1 ...

Page 2117: ...t used gpmc_a 7 A23 Not used Not used gpmc_a 6 A22 Not used Not used gpmc_a 5 A21 Not used Not used gpmc_a 4 A20 Not used Not used gpmc_a 3 A19 Not used Not used gpmc_a 2 A18 Not used Not used gpmc_a 1 A17 Not used Not used gpmc_d 15 A16 D15 D15 Not used gpmc_d 14 A15 D14 D14 Not used gpmc_d 13 A14 D13 D13 Not used gpmc_d 12 A13 D12 D12 Not used gpmc_d 11 A12 D11 D11 Not used gpmc_d 10 A11 D10 D10...

Page 2118: ...troller supports multiplexed address and data memory devices without adding logic externally Multiplexing mode can be selected through the GPMC GPMC_CONFIG1_i 9 MUXADDDATA bit i 0 to 7 Asynchronous page mode is not supported for multiplexed address and data devices 10 1 3 GPMC Integration 10 1 3 1 Description Figure 10 4 shows how the GPMC interacts with other modules in the device Figure 10 4 GPM...

Page 2119: ...are Reset GPMC modules can be reset under software control through the GPMC GPMC_SYSCONFIG 1 SOFTRESET bit When software reset bit is set all registers and the finite state machine FSM are reset immediately and unconditionally The GPMC_SYSSTATUS 0 RESETDONE bit can be polled to check reset status 10 1 3 2 4 Power Domain Power Saving and Reset Management GPMC power is supplied by the CORE power dom...

Page 2120: ... GPMC I O gpmc_d 15 8 CAUTION Before trying to access a chip select configured with a nonmultiplexed protocol set the LIMITEDADDRESS bit control 10 1 3 3 1 GPMC I O Configuration Setting in Default Pinout Mode 0 NOTE In this section the i in GPMC_CONFIG1_i stands for the GPMC chip select i where i 0 to 7 The address data nonmultiplexed device which is limited to a 2K byte address range is selected...

Page 2121: ...S0_MUX_DEVICE signal is propagated from the SCM Its value is fixed at 0x1 at IC reset causing the attached device to be address data multiplexed The waitselectpin input pin selects the WAIT signal at IC reset release time between WAIT0 input pin or WAIT1 input pin At IC reset release time these two pins have different polarity CAUTION Using the internal boot code the entire CS0 configuration can b...

Page 2122: ...attached device types and access schemes Based on the programmed configuration bit fields stored in the GPMC registers the GPMC is able to generate all control signals timing depending on the attached device and access type Given the chip select decoding and its associated configuration registers the GPMC selects the appropriate device type control signals timing 10 1 4 2 L3 Interconnect Interface...

Page 2123: ...ight sets of chip select configuration registers The GPMC configuration register file is memory mapped and can be read or written with byte 16 bit word or 32 bit word accesses The register file should be configured as a noncacheable nonbufferable region to prevent any desynchronization between host execution write request and the completion of register configuration write completed with register u...

Page 2124: ...multiple accesses External access profiles single multiple with optimized burst length native or emulated wrap are based on external device characteristics supported protocol bus width data buffer size native wrap support System burst read or write requests are synchronous burst multiple read or multiple write When neither burst nor page mode is supported by external memory or ASIC devices system ...

Page 2125: ...addresses are enabled concurrently access to these chip select regions is cancelled and a GPMC access error is posted The mask field is programmed through the GPMC_CONFIG7_i 11 8 MASKADDRESS bit field Figure 10 6 Chip Select Address Mapping and Decoding Mask NOTE GPMC can address up to 256MB on cs0 and cs1 support 128MB on cs2 to cs7 Chip select configuration base and mask address or any protocol ...

Page 2126: ...vice interfacing for both multiplexed and nonmultiplexed protocol It limits the use of 8 bit wide device interfacing to byte alias accesses This limitation is not applicable to NAND device interfacing 8 bit wide or 16 bit wide devices 10 1 5 2 3 Address Data Multiplexing Interface For random synchronous or asynchronous memory interfacing DEVICETYPE 0b00 an address and data multiplexing protocol ca...

Page 2127: ... controlled This is always a single request from the interconnect point of view Incrementing fixed length bursts of two words four words and eight words Wrapped critical word access first fixed length burst of two four or eight words To process a system request with the optimal protocol the READMULTIPLE and READTYPE and WRITEMULTIPLE and WRITETYPE parameters must be set according to the burstable ...

Page 2128: ...lways occurs on the eight words boundary As a consequence all words requested must be available from the memory data buffer when the buffer size is equal to or greater than the ATTACHEDDEVICEPAGELENGTH value This usually means that data can be read from or written to the buffer at a constant rate number of cycles between data without wait states between data accesses If the memory does not behave ...

Page 2129: ... this forced deassertion occurs when a pipelined request to the same chip select or to a different chip select is pending In such a case it is not necessary to deassert a control signal with deassertion time parameters equal to the cycle time parameter This exception to forced deassertion prevents any unnecessary glitchy transition This requirement also applies to BE signals thus avoiding an unnec...

Page 2130: ...ions If asserted CSEXTRADELAY applies to all parameters controlling nCS transitions The CSEXTRADELAY bit must be used carefully to avoid control signal overlap between successive accesses to different chip selects This implies the need to program the RDCYCLETIME and WRCYCLETIME bit fields to be greater than the nCS signal deassertion time including the extra half GPMC_FCLK period delay 10 1 5 3 3 ...

Page 2131: ...e used carefully to avoid control signal overlap between successive accesses to different chip selects This implies the need to program RDCYCLETIME and WRCYCLETIME to be greater than nOE RE signal deassertion time including the extra half GPMC_FCLK period delay nOE nRE is not asserted during a write cycle NOTE When the GPMC generates a read access to an address data multiplexed device it drives th...

Page 2132: ...d Control Signals Setup and Hold Control signal transition assertion and deassertion setup and hold values with respect to the GPMC_CLK edge can be controlled in the following ways For the GPMC_CLK signal the GPMC GPMC_CONFIG1_i 26 25 CLKACTIVATIONTIME field i 0 to 7 allows setup and hold control of control signal assertion time The use of a divided GPMC_CLK allows setup and hold control of contro...

Page 2133: ...MC_CLK rising edge used by the memory device for the first data capture The external WAIT signal can be used in conjunction with WRACCESSTIME to control the effective memory device data capture GPMC_CLK edge for a synchronous write access For details about wait monitoring see Section 10 1 5 4 10 1 5 3 9 Page Burst Access Time PAGEBURSTACCESSTIME PAGEBURSTACCESSTIME is programmed in the GPMC GPMC_C...

Page 2134: ...sses or not The GPMC GPMC_CONFIG1_i 21 WAITWRITEMONITORING bit defines whether the wait pin should be monitored during write accesses or not The GPMC access engine can be configured to monitor the wait pin of the external memory device asynchronously or synchronously with the GPMC_CLK clock depending on the access type synchronous or asynchronous the GPMC GPMC_CONFIG1_i 29 READTYPE and GPMC GPMC_C...

Page 2135: ...observed between wait pin deactivation time and data valid time including the required GPMC and the device data setup time an extra delay can be added between wait pin deassertion time detection and effective data capture time and the effective unlock of the CYCLETIME counter This extra delay can be programmed in the GPMC GPMC_CONFIG1_i 19 18 WAITMONITORINGTIME field i 0 to 7 NOTE The WAITMONITORI...

Page 2136: ...ill GPMC_CONFIG1_i 1 0 GPMCFCLKDIVIDER is used as a divider for the GPMC clock and so it must be programmed to define the correct WAITMONITORINGTIME delay 10 1 5 4 3 Wait Monitoring During a Synchronous Read Access During synchronous accesses with wait pin monitoring enabled the wait pin is captured synchronously with GPMC_CLK using the rising edge of this clock The WAIT signal can be programmed t...

Page 2137: ...he burst The data bus is considered valid and data are captured during this clock cycle In a single access or if this was the last access in a multiple access cycle all signals are controlled according to their relative control timing value and the CYCLETIME counter status Figure 10 9 shows wait behavior during a synchronous read burst access Figure 10 9 Wait Behavior During a Synchronous Read Bur...

Page 2138: ...us Turnaround BUSTURNAROUND To prevent data bus contention an access that follows a read access to a slow memory device that is control the nCS nOE de assertion to data bus in high impedance delay must be delayed The bus turnaround is a time out counter starting after nCS or nOE de assertion time whichever occurs first and delays the next access start cycle time It is programmed trhough the GPMC G...

Page 2139: ...DOFFTIME CSWROFFTIME completion All control signals are kept inactive during the idle GPMC_FCLK cycles NOTE CYCLE2CYCLESAMECSEN and CYCLE2CYCLEDIFFCSEN should be set in the GPMC_CONFIG6_i registers to insert idle cycles between accesses on this chip select and after accesses to a different chip select respectively The CYCLE2CYCLEDELAY delay runs in parallel with the BUSTURNAROUND delay BUSTURNAROU...

Page 2140: ...e time For read accesses the gpmc_io_dir pin goes from OUT to IN at nOE assertion time and stays IN until BUSTURNAROUND is enabled The gpmc_io_dir pin goes from IN to OUT at end cycle time plus programmable bus turnaround time BUSTURNAROUND is disabled After an asynchronous read access the gpmc_io_dir pin goes from IN to OUT at RDACCESSTIME 1 GPMC_FCLK cycle or when RDCYCLETIME completes whichever...

Page 2141: ...ccording to the incoming system request from access start to access completion for asynchronous and synchronous single accesses Asserted low from access start to access completion for asynchronous and synchronous multiple read accesses Valid asserted or nonasserted according to the incoming system request synchronously to each written data for synchronous multiple write accesses 10 1 5 9 Asynchron...

Page 2142: ... enable signal nOE nOE assertion indicates a read cycle nOE assertion time is controlled by the GPMC_CONFIG4_i 3 0 OEONTIME field nOE deassertion time is controlled by the GPMC_CONFIG4_i 12 8 OEOFFTIME field Read data is latched when RDACCESSTIME completes Access time is defined in the GPMC GPMC_CONFIG5_i 20 16 RDACCESSTIME field The end of the access is defined by the RDCYCLETIME parameter The re...

Page 2143: ... 15 0 from an external device perspective are placed on the address data bus and the remaining address bits 25 16 are placed on the address bus The address phase ends at nOE assertion when the DIR signal goes from OUT to IN The nCS nADV nOE and DIR signals are controlled in the same way as nonmultiplexed accesses 2143 SWPU177N December 2009 Revised November 2010 Memory Subsystem Copyright 2009 201...

Page 2144: ...bit at 0 write asynchronous MUXADDDATA bit at 0 nonaddress data multiplexed device Chip select signal nCS nCS assertion time is controlled by the GPMC GPMC_CONFIG2_i 3 0 CSONTIME field and ensures address setup time to nCS assertion nCS deassertion time is controlled by the GPMC GPMC_CONFIG2_i 20 16 CSWROFFTIME field and ensures address hold time to nCS deassertion Address valid signal nADV nADV a...

Page 2145: ...mmed with GPMC GPMC_CONFIG6_i 7 CYCLE2CYCLESAMECSEN enabled The CSWROFFTIME and CSONTIME parameters also allow a chip select pulse but this affects all other types of access 10 1 5 9 2 2 Asynchronous Single Write Operation on an Address Data Multiplexed Device Figure 10 13 shows an asynchronous single write operation on an address data multiplexed device Figure 10 13 Asynchronous Single Write on a...

Page 2146: ...sses single asynchronous accesses 10 1 5 9 3 Asynchronous Multiple Page Mode Read Figure 10 14 shows an asynchronous multiple read operation Figure 10 14 Asynchronous Multiple Page Mode Read NOTE The WAIT signal is active low In the following section i stands for the chip select number i 0 to 7 For read access with GPMC GPMC_CONFIG1_i register settings READMULTIPLE bit at 1 read multiple access RE...

Page 2147: ...e with a new burst access meaning a new initial access phase is initiated Total access time RDCYCLETIME corresponds to RDACCESSTIME plus the address hold time starting from the nCS deassertion plus the time from RDACCESSTIME to CSRDOFFTIME The read cycle time is defined in the GPMC GPMC_CONFIG5_i 4 0 RDCYCLETIME field In Figure 10 14 the RDCYCLETIME programmed value equals RDCYCLETIME0 before page...

Page 2148: ... nBE0 nCS nADV nOE gpmc_a 11 1 gpmc_d 15 0 connected to A 9 0 on memory side connected to D 15 0 on memory side gpmc 015 Public Version General Purpose Memory Controller www ti com Figure 10 15 Synchronous Single Read GPMCFCLKDIVIDER 0 2148 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2149: ...the GPMC GPMC_CONFIG2_i 3 0 CSONTIME field and ensures address setup time to nCS assertion nCS deassertion time is controlled by the GPMC GPMC_CONFIG2_i 12 8 CSRDOFFTIME field and ensures address hold time to nCS deassertion Address valid signal nADV nADV assertion time is controlled by the GPMC GPMC_CONFIG3_i 3 0 ADVONTIME field nADV deassertion time is controlled by the GPMC GPMC_CONFIG3_i 12 8 ...

Page 2150: ... 10 1 5 10 2 Synchronous Single Write Figure 10 17 Synchronous Single Write on an Address Data Multiplexed Device NOTE The WAIT signal is active low When the GPMC generates a write access to an address data multiplexed device it drives the data bus until WRDATAONADMUXBUS time GPMC_CONFIG6_i 19 16 The GPMC GPMC_CONFIG1_i register settings i 0 to 7 are as follows WRITEMULTIPLE bit at 0 write single ...

Page 2151: ...nected to D 15 0 on memory side gpmc 018 Valid Address Public Version www ti com General Purpose Memory Controller 10 1 5 10 3 Synchronous Multiple Burst Read 4 8 16 Word16 Burst With Wraparound Capability Figure 10 18 and Figure 10 19 show a synchronous multiple read operation with GPMCFCLKDivider equal to 0 and 1 respectively Figure 10 18 Synchronous Multiple Burst Read GPMCFCLKDIVIDER 0 NOTE Th...

Page 2152: ...ing data transactions Chip select signal nCS nCS assertion time is controlled by the GPMC GPMC_CONFIG2_i 3 0 CSONTIME field and ensures address setup time to nCS assertion nCS deassertion time is controlled by the GPMC GPMC_CONFIG2_i 12 8 CSRDOFFTIME field and ensures address hold time to nCS deassertion Address valid signal nADV nADV assertion time is controlled by the GPMC GPMC_CONFIG3_i 3 0 ADV...

Page 2153: ...RDOFFTIME RDCYCLETIME is defined in the GPMC GPMC_CONFIG5_i register In Figure 10 19 the RDCYCLETIME programmed value equals RDCYCLETIME0 RDCYCLETIME1 Direction signal DIR DIR goes from OUT to IN at the same time as nOE assertion After a read operation if no other access read or write is pending the data bus is driven with the previous read value See Section 10 1 5 3 10 Bus Keeping Support Burst w...

Page 2154: ...e time when the burst first data is driven in the address data bus because some new devices require the nWE signal at low during the address phase First write data is driven by the GPMC at WRDATAONADMUXBUS GPMC_CONFIG6_i 19 16 when in address data mux configuration The next write data of the burst is driven on the bus at WRACCESSTIME 1 during PAGEBURSTACCESSTIME GPMC_FCLK cycles The last data of t...

Page 2155: ...Asynchronous single read Asynchronous page read Asynchronous single write Synchronous single read and write Synchronous burst read Synchronous burst write pSRAM devices must be powered up and initialized in a predefined manner according to the specifications of the attached device pSRAM devices can be programmed to use either mode fixed or variable latency pSRAM devices can either automatically sc...

Page 2156: ...hip select with the appropriate asynchronous configuration settings As for any other type of memory compatible with the GPMC interface accesses to a chip select allocated to a NAND device can be interleaved with accesses to chip selects allocated to other external devices This interleaved capability limits the system to chip enable dont care NAND devices since the chip select allocated to the NAND...

Page 2157: ...PE GPMC_CONFIG1_i 27 0 Asynchronous mode CLKACTIVATIONTIME GPMC_CONFIG1_i 26 25 00 ATTACHEDDEVICEPAGELENGTH GPMC_CONFIG1_i 24 23 Don t Single access mode care WAITREADMONITORING GPMC_CONFIG1_i 22 0 Wait not monitored by GPMC access engine WAITWRITEMONITORING GPMC_CONFIG1_i 21 0 Wait not monitored by GPMC access engine WAITMONITORINGTIME GPMC_CONFIG1_i 19 18 Don t Wait not monitored by GPMC access ...

Page 2158: ...ite buffer GPMC GPMC_NAND_COMMAND_i and GPMC GPMC_NAND_ADDRESS_i i 0 to 7 are Word32 locations which means any Word32 or Word16 access is split into 4 or 2 byte accesses if an 8 bit wide NAND device is attached For multiple command phase or multiple address phase the software driver can use Word32 or Word16 access to these registers but it must account for the splitting and little endian ordering ...

Page 2159: ...1 must not toggle because it is shared with CLE NAND flash memories do not use byte enable signals 10 1 5 14 1 4 Address Latch Cycle Writing data at the GPMC GPMC_NAND_ADDRESS_i location i 0 to 7 places the data as the NAND partial address value on the bus using a regular asynchronous write access nCS is controlled by the CSONTIME and CSWROFFTIME timing parameters ALE is controlled by the ADVONTIM...

Page 2160: ...data from the GPMC GPMC_NAND_DATA_i location or from any location in the associated chip select memory region activates an asynchronous read access nCS is controlled by the CSONTIME and CSRDOFFTIME timing parameters nRE is controlled by the OEONTIME and OEOFFTIME timing parameters To take advantage of nRE high to data invalid minimum timing value the RDACCESSTIME can be set so that data are effect...

Page 2161: ...e especially for device status read accesses following status read command programming write access If such write to read transactions are used a minimum nCS high pulse width must be set For this CYCLE2CYCLESAMECSEN and CYCLE2CYCLEDELAY must be set according to the appropriate timing requirement to prevent any timing violation NAND devices usually have an important nRE high to data bus in tristate...

Page 2162: ...he ready pin is sampled inactive can stall GPMC access and eventually cause a system time out NOTE If a read access to a NAND flash is done using the wait monitoring mode the device is blocked during a page opening and so is the GPMC If the correct settings are used other chip selects can be used while the memory processes the page opening command To avoid a time out caused by a block page opening...

Page 2163: ...o the memory device in stream mode There is no automatic error detection or correction and it is the software NAND driver responsibility to read the multiple ECC calculation results compare them to the expected code value and take the appropriate corrective actions according to the error handling strategy ECC storage in spare byte error correction on read block invalidation The ECC engine includes...

Page 2164: ...omputing the ECC on the NAND spare byte For example with a 2 Kbyte data page 8 bit wide NAND device eight ECCs accumulated on 256 bytes can be computed and added to one extra ECC computed on the 24 spare bytes area where the eight ECC results used for comparison and correction with the computed data page ECC are stored The GPMC then provides nine GPMC GPMC_ECCj_RESULT registers j 1 to 9 to store t...

Page 2165: ...2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 0 Row 1 Row 2 Row 3 Row 252 Row 253 Row 254 Row 255 P1o P2o P2o P1o P1o P1o bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit...

Page 2166: ...t3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 0 Row 1 Row 2 Row 3 Row 252 Row 253 Row 254 Row 255 P1o P2o P2o P1o P1o P1o P8e P8e P8e P8e P16e P16e gpmc 027 bit7 bit6 bit5 bit4 bit3 bi...

Page 2167: ...s no error is detected and the read data is correct If every second bit in the parity result is a 1 one bit is corrupted and is located at bit address P2048o P1024o P512o P256o P128o P64o P32o P16o P8o P4o P2o P1o The software must correct the corresponding bit If only one bit in the parity result is 1 it is an ECC error and the read data is correct 10 1 5 14 3 1 5 ECC Calculation Based on 8 Bit W...

Page 2168: ...t5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P1o P1e P1o P1e P1o P1e P1o P1e P2o P2e P2o P2e P4o P4e bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit15 bit14 bit13 bit12 ...

Page 2169: ... to hold the BCH ECC that is to have at least a message of 13 bytes available per 512 byte sector of data The zone of unused spare area by the ECC may or may not be protected by the same ECC scheme by extending the BCH message beyond 512 bytes maximum codeword is 1023 byte long ECC included which leaves a lot of space to cover some spares bytes 10 1 5 14 3 2 2 Memory Mapping of the BCH Codeword BC...

Page 2170: ...ata vectors are aligned that is their boundaries coincide with the RAMs data word boundaries Table 10 7 Aligned Message Byte Mapping in 8 bit NAND Byte Offset 8 Bit Word 0x000 msb Byte 511 0x1FF 0x001 Byte 510 0x1FE 0x1FF Byte 0 0x0 lsb Table 10 8 Aligned Message Byte Mapping in 16 bit NAND Byte Offset 16 Bit Word MSB 16 Bit Word LSB 0x000 Byte 510 0x1FE msb Byte 511 0x1FF 0x002 Byte 508 0x1FC Byt...

Page 2171: ...s significant Nibble 0 Nibble S 3 Nibble S 4 msb Nibble S 1 Nibble S 2 2 Nibble S 7 Nibble S 8 Nibble S 5 Nibble S 6 S 1 2 4 Nibble 4 Nibble 3 Nibble 6 Nibble 5 S 1 2 2 Nibble 0 lsb Nibble 2 Nibble 1 Table 10 13 Misaligned Nibble Mapping of Message in 16 bit NAND 2 Unused Nibbles Byte Offset 16 Bit Word 4 Bit Most Significant Nibble 4 Bit Less Significant Nibble 0 Nibble S 3 Nibble S 4 msb Nibble ...

Page 2172: ...of sections as data is being fed into the module For each section the BCH core can be enabled in which case the data is fed to the BCH divider or not in which case the BCH simply counts to the end of the section When enabled the data is added to the ongoing calculation for a given sector number for example number 0 Wrapping modes are described below To get a better understanding and see the real l...

Page 2173: ...cessing ON size1 nibbles spare processing OFF Checksum Spare area size nibbles S size0 size1 10 1 5 14 3 2 2 6 Mode 0xA 10 Page processing sequence Repeat with buffer 0 to S 1 512 byte data processing ON Repeat with buffer 0 to S 1 size0 nibbles spare processing ON 1 nibble pad spare processing OFF size1 nibbles spare processing OFF Checksum Spare area size nibbles S size0 1 size1 10 1 5 14 3 2 2 ...

Page 2174: ...0 to S 1 512 byte data processing ON One time with buffer 0 size0 nibbles spare processing ON Repeat with buffer 0 to S 1 1 nibble padding spare processing OFF size1 nibbles spare processing ON Checksum Spare area size nibbles size0 S 1 size1 10 1 5 14 3 2 2 11 Mode 0x4 Page processing sequence Repeat with buffer 0 to S 1 512 byte data processing ON One time no buffer used size0 nibbles spare proc...

Page 2175: ... buffer 0 to S 1 512 byte data processing ON Repeat with buffer 0 to S 1 size0 nibbles spare processing ON Repeat S times no buffer used size1 nibbles spare processing OFF Checksum Spare area size nibbles S size0 size1 10 1 5 14 3 2 3 Supported NAND Page Mappings and ECC Schemes The following rules apply throughout the entire mapping description Main data area sectors size is hardcoded to 512 byte...

Page 2176: ...a page size of 1kByte spares that is S 2 sectors of 512 bytes The same principles can be extended to larger pages by adding more sectors The actual BCH codeword size is used during the error location work to restrict the search range by definition errors can only happen in the codeword that was actually written to the NAND and not in the mathematical codeword of n 213 1 8191 bits That codeword hig...

Page 2177: ...ECC ECC not right aligned Per sector spares Spares not covered by ECC ECC right aligned per sector Sector spares Sector spares Sector spares Sector spares size0 Data0 Data1 Prot0 Ecc0 Prot1 Ecc1 Sector spares Sector spares 0 1 0 1 0 0 inactive inactive 1 1 Write Read 1 10 Mode Size0 Size1 P 1 E P E Per sector spares Spares covered by sector ECC per sector left padded ECC Pad Pad i Sector data Sect...

Page 2178: ...ta0 Data1 Protected pooled Ecc0 Ecc1 Pooled page spares 0 1 0 1 0 1 inactive 0 Write Read 7 8 P 1 E P E Mode Size0 Size1 Pooled spares Spares covered by ECC0 All ECC at the end left padded Pad Pad 0 i i Ecc0 Ecc1 Pad Pad Sector data Sector data Sector data Sector data Sector data Sector data Sector data Sector data M5 M6 M7 M8 0 1 Write 6 0 U S 1 E inactive 0 1 Write 6 0 U S E gpmc 034 Public Vers...

Page 2179: ...res separate ECC Spares not covered by ECC All ECC at the end left padded ECC Unprot0 Unprot1 inactive Ecc0 Ecc1 Pad Pad 1 1 size1 size1 1 0 i i Sector data Sector data Sector data Sector data Sector data Sector data Sector data M9 M 10 M 11 M 12 0 1 inactive Write 6 0 U 1 E 0 1 Write 6 0 U E gpmc_035 Public Version www ti com General Purpose Memory Controller Figure 10 35 NAND Page Mapping and EC...

Page 2180: ...refetch and write posting engine is dedicated to data stream access as opposed to random data access The engine does not include an address generator and the request is limited to chip select target identification The prefetch write posting engine read or write request is routed to the access engine with the chip select destination ID After the required arbitration phase the access engine processe...

Page 2181: ... the prefetch engine starts requesting data as soon as the STARTENGINE bit is set If using this configuration the host must monitor the NAND device ready pin so that it only sets the STARTENGINE bit when the NAND device is in a ready state meaning data is valid for prefetching When the GPMC GPMC_PREFETCH_CONFIG1 3 SYNCHROMODE bit is set the prefetch engine starts requesting data when an active to ...

Page 2182: ...remaining data to be requested according to the TRANSFERCOUNT value An interrupt can be triggered by the GPMC when the prefetch process is complete that is COUNTVALUE equals 0 if the GPMC GPMC_IRQENABLE 1 TERMINALCOUNTEVENTENABLE bit is set At prefetch completion thehe TERMINALCOUNT interrupt event is also logged and the GPMC GPMC_IRQSTATUS 1 TERMINALCOUNTSTATUS bit is set To clear the interrupt t...

Page 2183: ...s not empty If the STARTENGINE bit is set after the NAND address phase page program command the STARTENGINE setting is effective only after the actual NAND command completion To prevent GPMC stall during this NAND command phase set the STARTENGINE bit field before the NAND address completion and ensure that the associated DMA channel is enabled after the NAND address phase The posting engine issue...

Page 2184: ...he MPU must clear the TERMINALCOUNTSTATUS bit The TERMINALCOUNTSTATUS bit must always be cleared prior to asserting the TERMINALCOUNTEVENTENABLE bit to clear any out of date logged interrupt event NOTE The COUNTVALUE value is valid only if the write posting engine is active and started and an interrupt is issued only when COUNTVALUE reaches 0 that is when the posting engine automatically goes from...

Page 2185: ...TIME timing parameters Figure 10 36 highlights that in the case of back to back accesses to the NAND flash through the prefetch engine CYCLE2CYCLESAMECSEN is forced to 0 when using optimized accesses The first access uses the regular timing settings for this chip select All accesses after this one use settings reduced by x clock cycles x being defined by the GPMC_PREFETCH_CONFIG1 30 28 CYCLEOPTIMI...

Page 2186: ...he GPMC Module As discussed in the introduction to this chapter the GPMC module supports the following external memory types Asynchronous or synchronous 8 bit or 16 bit width memory or device 16 bit address data multiplexed or not multiplexed NOR flash device 8 or 16 bit NAND flash device The following examples show how to calculate GPMC timing parameters by showing a typical parameter setup for t...

Page 2187: ...nchronous burst read Asynchronous read Asynchronous single write 10 1 6 1 2 1 GPMC Configuration for Synchronous Burst Read Access The clock runs at 104 MHz f 104 MHz T 9 615 ns Table 10 18 shows the timing parameters on the memory side that determine the parameters on the GPMC side Table 10 19 shows how to calculate timings for the GPMC using the memory parameters Figure 10 38 shows the synchrono...

Page 2188: ...d nOE must be released at the end of an access These signals are held to allow the access to complete Read cycle time GPMC side Read access time access completion Write cycle time for burst access Not supported for NOR flash memory Table 10 19 Calculating GPMC Timing Parameters Parameter Formula Duration ns Number of GPMC Register Name on GPMC Clock Cycles Configurations Side F 104 MHz ClkActivati...

Page 2189: ... time 6 tCAS nCS setup time to nADV 0 tOE Output enable to output valid 6 tOEZ Output enable to High Z 7 Use the following formula to calculate the RdCycleTime parameter for this typical access RdCycleTime RdAccessTime AccessCompletion RdAccessTime 1 clock cycle tOEZ First on the memory side the external memory makes the data available to the output bus This is the memory side read access time def...

Page 2190: ... 615 10 CSRDOFFTIME 0x0A AdvOnTime tAAVDS 3 1 ADVONTIME 0X1 AdvRdOffTime tAAVDS tAVDP 9 1 ADVRDOFFTIME 0x01 OeOnTime OeOnTime AdvRdOffTime 3 for instance OEONTIME 0x3 multiplexed mode OeOffTime AccessTime 1cycle 89 615 10 OEOFFTIME 0x0A Figure 10 39 Asynchronous Single Read Access Timing Parameters in Clock Cycles 10 1 6 1 2 3 GPMC Configuration for Asynchronous Single Write Access The clock runs ...

Page 2191: ... Asynchronous Single Write Parameter Name on Formula Duration ns Number of GPMC Registers GPMC side Clock Cycles Configuration F 104 MHz ClkActivationTime n a asynchronous mode AccessTime Applicable only to WAITMONITORING the value is the same as for read access PageBurstAccessTime n a single access WrCycleTime WeOffTime 57 615 6 WRCYCLETIME 0x06 AccessCompletion CsOnTime tCAS 0 0 CSONTIME 0x0 CsW...

Page 2192: ...GPMC memories Table 10 24 Supported Memory Interfaces 16 Bit Address Data Muxed Function OneNAND 16 bit NAND 8 bit NAND pSRAM or NOR Flash 1 gpmc_a11 A27 gpmc_a10 A26 gpmc_a9 A25 gpmc_a8 A24 gpmc_a7 A23 gpmc_a6 A22 gpmc_a5 A21 gpmc_a4 A20 gpmc_a3 A19 gpmc_a2 A18 gpmc_a1 A17 gpmc_d15 D15 or A16 IO15 gpmc_d14 D14 or A15 IO14 gpmc_d13 D13 or A14 IO13 gpmc_d12 D12 or A13 IO12 gpmc_d11 D11 or A12 IO11 ...

Page 2193: ...ty NAND is a good storage solution for many applications where mobility low power and speed are key factors Low pin count and simple interface are other advantages of NAND Table 10 25 summarizes the level of the NAND interface signals applied to external devices or memories Table 10 25 NAND Interface Bus Operations Summary Bus operation CLE ALE nCE nWE 1 nRE 1 nWP Read cmd input H L L RE H x Read ...

Page 2194: ...lso has synchronous write capability 10 1 6 2 1 5 Supported Protocols The GPMC supports the following interface protocols when communicating with external memory or external devices Asynchronous read write access Asynchronous read page access 4 8 16 Word16 Synchronous read write access Synchronous read burst access without wrap capability 4 8 16 Word16 Synchronous read burst access with wrap capab...

Page 2195: ...0000 0030 i GPMC_CONFIG6_i 1 RW 32 0x0000 0074 0x0000 0030 i 0x6E00 0074 0x0000 0030 i GPMC_CONFIG7_i 1 RW 32 0x0000 0078 0x0000 0030 i 0x6E00 0078 0x0000 0030 i GPMC_NAND_COMMAND_i 1 W 32 0x0000 007C 0x0000 0030 i 0x6E00 007C 0x0000 0030 i GPMC_NAND_ADDRESS_i 1 W 32 0x0000 0080 0x0000 0030 i 0x6E00 0080 0x0000 0030 i GPMC_NAND_DATA_i 1 RW 32 0x0000 0084 0x0000 0030 i 0x6E00 0084 0x0000 0030 i GPM...

Page 2196: ...1 for 2 1 1 TI internal data Table 10 30 Register Call Summary for Register GPMC_REVISION General Purpose Memory Controller GPMC Register Summary 0 Table 10 31 GPMC_SYSCONFIG Address Offset 0x0000 0010 Physical Address 0x6E00 0010 Instance GPMC Description This register controls the various parameters of the Interconnect Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 2197: ..._SYSSTATUS Address Offset 0x0000 0014 Physical Address 0x6E00 0014 Instance GPMC Description This register provides status information about the module excluding the interrupt status information Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESETDONE Bits Field Name Description Type Reset 31 8 RESERVED Reads returns 0 R 0x000000 7 1 ...

Page 2198: ...ion on WAIT2 input pin has not been detected Write 0x0 WAIT2EDGEDETECTIONSTATUS bit unchanged Read 0x1 A transition on WAIT2 input pin has been detected Write 0x1 WAIT2EDGEDETECTIONSTATUS bit is reset 9 WAIT1EDGEDETECTION Status of the Wait1 Edge Detection interrupt RW 0x0 STATUS Read 0x0 A transition on WAIT1 input pin has not been detected Write 0x0 WAIT1EDGEDETECTIONSTATUS bit unchanged Read 0x...

Page 2199: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED FIFOEVENTENABLE WAIT3EDGEDETECTIONENABLE WAIT2EDGEDETECTIONENABLE WAIT1EDGEDETECTIONENABLE WAIT0EDGEDETECTIONENABLE TERMINALCOUNTEVENTENABLE Bits Field Name Description Type Reset 31 12 RESERVED Write 0s for future compatibility Read returns 0s RW 0x00000 11 WAIT3EDGEDETECTION Enables the Wait3 Edge Detection interrupt RW 0x0 ENABLE 0x0 Wait3EdgeD...

Page 2200: ... allows the user to set the start value of the timeout counter Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TIMEOUTSTARTVALUE RESERVED TIMEOUTENABLE Bits Field Name Description Type Reset 31 13 RESERVED Write 0s for future compatibility Read returns 0s RW 0x00000 12 4 TIMEOUTSTARTVALUE Start value of the time out counter RW 0x1FF 0x000 Zero...

Page 2201: ... 43 GPMC_ERR_TYPE Address Offset 0x0000 0048 Physical Address 0x6E00 0048 Instance GPMC Description The GPMC_ERR_TYPE register stores the type of error when an error occurs Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED ERRORVALID ILLEGALMCMD ERRORTIMEOUT ERRORNOTSUPPADD ERRORNOTSUPPMCMD Bits Field Name Description Type Rese...

Page 2202: ...GPMC Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED WRITEPROTECT LIMITEDADDRESS WAIT3PINPOLARITY WAIT2PINPOLARITY WAIT1PINPOLARITY WAIT0PINPOLARITY NANDFORCEPOSTEDWRITE Bits Field Name Description Type Reset 31 12 RESERVED Write 0s for future compatibility Read returns 0s RW 0x00000 11 WAIT3PINPOLARITY Selects the polarity o...

Page 2203: ...ess Description 5 6 NAND Device Basic Programming Model 7 8 GPMC Register Summary 9 Table 10 47 GPMC_STATUS Address Offset 0x0000 0054 Physical Address 0x6E00 0054 Instance GPMC Description The status register provides global status bits of the GPMC Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED WAIT3STATUS WAIT2STATUS WAIT1STATUS WA...

Page 2204: ...00 0030 i Instance GPMC Description The configuration register 1 sets signal control parameters per chip select Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED READTYPE RESERVED RESERVED RESERVED WRITETYPE DEVICESIZE DEVICETYPE WRAPBURST MUXADDDATA READMULTIPLE WAITPINSELECT WRITEMULTIPLE GPMCFCLKDIVIDER CLKACTIVATIONTIME WAITMONITORINGTIME WA...

Page 2205: ...0x1 Wait pin is monitored for read accesses 21 WAITWRITEMONITORING Selects the Wait monitoring configuration for Write accesses RW 0x0 0x0 Wait pin is not monitored for write accesses 0x1 Wait pin is monitored for write accesses 20 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 19 18 WAITMONITORINGTIME Selects input pin Wait monitoring time RW 0x0 0x0 Wait pin is monitored with v...

Page 2206: ...FCLK clock RW 0x0 0x0 GPMC_CLK frequency GPMC_FCLK frequency 0x1 GPMC_CLK frequency GPMC_FCLK frequency 2 0x2 GPMC_CLK frequency GPMC_FCLK frequency 3 0x3 GPMC_CLK frequency GPMC_FCLK frequency 4 Table 10 50 Register Call Summary for Register GPMC_CONFIG1_i General Purpose Memory Controller GPMC Environment 0 Clocking Reset and Power Management Scheme 1 GPMC Address and Data Bus 2 3 4 5 6 7 8 9 10...

Page 2207: ...ol signal is not delayed 0x1 CS i Timing control signal is delayed of half GPMC_FCLK clock cycle 6 4 RESERVED Write 0s for future compatibility Read returns 0s RW 0x0 3 0 CSONTIME CS i assertion time from start cycle time RW 0x1 0x0 0 GPMC_FCLK cycle 0x1 1 GPMC_FCLK cycle 0xF 15 GPMC_FCLK cycles Table 10 52 Register Call Summary for Register GPMC_CONFIG2_i General Purpose Memory Controller Timing ...

Page 2208: ... 54 Register Call Summary for Register GPMC_CONFIG3_i General Purpose Memory Controller Timing Setting 0 1 2 3 Asynchronous Access Description 4 5 6 7 8 9 Synchronous Access 10 11 12 13 14 15 GPMC Register Summary 16 Table 10 55 GPMC_CONFIG4_i Address Offset 0x0000 006C 0x0000 0030 i Index i 0 to 7 Physical Address 0x6E00 006C 0x0000 0030 i Instance GPMC Description nWE and nOE signals timing para...

Page 2209: ... GPMC_FCLK cycles Table 10 56 Register Call Summary for Register GPMC_CONFIG4_i General Purpose Memory Controller Timing Setting 0 1 2 3 4 5 Asynchronous Access Description 6 7 8 9 10 11 Synchronous Access 12 13 14 15 16 17 NAND Device Basic Programming Model 18 GPMC Register Summary 19 Table 10 57 GPMC_CONFIG5_i Address Offset 0x0000 0070 0x0000 0030 i Index i 0 to 7 Physical Address 0x6E00 0070 ...

Page 2210: ...PMC Register Summary 17 Table 10 59 GPMC_CONFIG6_i Address Offset 0x0000 0074 0x0000 0030 i Index i 0 to 7 Physical Address 0x6E00 0074 0x0000 0030 i Instance GPMC Description WrAccessTime WrDataOnADmuxBus Cycle2Cycle and BusTurnAround parameters configuration Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRACCESSTIME RESERVED RESERVED RESERVED RESER...

Page 2211: ... 5 4 RESERVED Write 0s for future compatibility RW 0x0 Reads returns 0 3 0 BUSTURNAROUND Bus turn around latency between successive accesses to RW 0x0 the same CS read to write or to a different CS read to read and read to write 0x0 0 GPMC_FCLK cycle 0x1 1 GPMC_FCLK cycle 0xF 15 GPMC_FCLK cycles Table 10 60 Register Call Summary for Register GPMC_CONFIG6_i General Purpose Memory Controller Timing ...

Page 2212: ...on 0 1 2 NAND Device Basic Programming Model 3 GPMC Register Summary 4 Table 10 63 GPMC_NAND_COMMAND_i Address Offset 0x0000 007C 0x0000 0030 i Index i 0 to 7 Physical Address 0x6E00 007C 0x0000 0030 i Instance GPMC Description This register is not a true register just an address location Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPMC_NAND_COMMAND...

Page 2213: ...ts Field Name Description Type Reset 31 0 GPMC_NAND_DATA This register is not a true register just an address location W n a Table 10 68 Register Call Summary for Register GPMC_NAND_DATA_i General Purpose Memory Controller NAND Device Basic Programming Model 0 1 2 3 4 5 GPMC Register Summary 6 GPMC Register Description 7 8 Table 10 69 GPMC_PREFETCH_CONFIG1 Address Offset 0x0000 01E0 Physical Addre...

Page 2214: ...lways serviced If the PFPWEnRoundRobin is enabled 0x0 the next access is granted to the PFPW engine 0x1 the two next accesses are granted to the PFPW engine 0xF the 16 next accesses are granted to the PFPW engine 15 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 14 8 FIFOTHRESHOLD Selects the maximum number of bytes read from the RW 0x40 FIFO or written to the FIFO by the host on...

Page 2215: ...Offset 0x0000 01E4 Physical Address 0x6E00 01E4 Instance GPMC Description Prefetch engine configuration 2 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TRANSFERCOUNT Bits Field Name Description Type Reset 31 14 RESERVED Write 0s for future compatibility Read returns 0s RW 0x00000 13 0 TRANSFERCOUNT Selects the number of bytes to be read or w...

Page 2216: ...Description Type Reset 31 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 30 24 FIFOPOINTER Number of available bytes to be read or number of free R 0x00 empty byte places to be written 0x00 0 byte available to be read or 0 free empty place to be written 0x40 64 bytes available to be read or 64 empty places to be written 23 17 RESERVED Write 0s for future compatibility Read return...

Page 2217: ...rns 0s RW 0x0 12 ECCBCHT8 Error correction capability used for BCH RW 0x1 0x0 Up to 4 bits error correction t 4 0x1 Up to 8 bits error correction t 8 11 8 ECCWRAPMODE Spare area organization definition for the BCH algorithm See the RW 0x0 BCH syndrome parity calculator module functional specification for more details 7 ECC16B Selects an ECC calculated on 16 columns RW 0x0 0x0 ECC calculated on 8 c...

Page 2218: ...for future compatibility Read returns 0s RW 0x0 3 0 ECCPOINTER Selects ECC result register Reads to this field give the dynamic RW 0x0 position of the ECC pointer Writes to this field select the ECC result register where the first ECC computation will be stored Other enums writing other values disables the ECC engine ECCENABLE bit of GPMC_ECC_CONFIG set to 0 0x0 Writing 0x0 disables the ECC engine...

Page 2219: ... Bytes 0x02 6 Bytes 0x03 8 Bytes 0xFF 512 Bytes 11 9 RESERVED Write 0s for future compatibility Read returns 0s RW 0x0 8 ECC9RESULTSIZE Selects ECC size for ECC 9 result register RW 0x0 0x0 ECCSIZE0 selected 0x1 ECCSIZE1 selected 7 ECC8RESULTSIZE Selects ECC size for ECC 8 result register RW 0x0 0x0 ECCSIZE0 selected 0x1 ECCSIZE1 selected 6 ECC7RESULTSIZE Selects ECC size for ECC 7 result register...

Page 2220: ...28 RESERVED Write 0s for future compatibility Read returns 0s RW 0x0 27 P2048o Odd row parity bit 2048 only used for ECC computed on 512 Bytes R 0x0 26 P1024o Odd row parity bit 1024 R 0x0 25 P512o Odd row parity bit 512 R 0x0 24 P256o Odd row parity bit 256 R 0x0 23 P128o Odd row parity bit 128 R 0x0 22 P64o Odd row parity bit 64 R 0x0 21 P32o Odd row parity bit 32 R 0x0 20 P16o Odd row parity bi...

Page 2221: ...H_RESULT_0 BCH ECC result bits 0 to 31 RW 0x00000000 Table 10 86 Register Call Summary for Register GPMC_BCH_RESULT0_i General Purpose Memory Controller NAND Device Basic Programming Model 0 GPMC Register Summary 1 Table 10 87 GPMC_BCH_RESULT1_i Address Offset 0x0000 0244 0x0000 0010 i Index i 0 to 7 Physical Address 0x6E00 0244 0x0000 0010 i Instance GPMC Description BCH ECC result bits 32 to 63 ...

Page 2222: ...D BCH_RESULT_3 Bits Field Name Description Type Reset 31 8 RESERVED Write 0s for future compatibility Read returns 0s R 0x000000 7 0 BCH_RESULT_3 BCH ECC result bits 96 to 103 RW 0x00 Table 10 92 Register Call Summary for Register GPMC_BCH_RESULT3_i General Purpose Memory Controller NAND Device Basic Programming Model 0 GPMC Register Summary 1 Table 10 93 GPMC_BCH_SWDATA Address Offset 0x0000 02D0...

Page 2223: ...y components The module includes support for low power double data rate SDRAM LPDDR1 The SDRC subsystem provides a high performance interface to a variety of fast memory devices It comprises two submodules The SDRAM memory scheduler SMS consisting of scheduler and virtual rotated frame buffer VRFB modules The SDRC CAUTION DDR SDRAM and SDR SDRAM memory types cannot be connected simultaneously to t...

Page 2224: ...n accessing graphics buffer in nonnatural raster scan order Supports rotations of 0 90 180 and 270 degrees Transparent to software applications 12 concurrent rotation contexts Memory access scheduler Optimizes latency and bandwidth usage between initiators Per system initiator group quality of service QoS control 8 8 64 request queue FIFO for optimal scheduling Programmable arbitration scheme Focu...

Page 2225: ...Burst support Memory burst support System burst for SDR SDRAM system burst translated into memory burst of 2 System burst for mobile DDR SDRAM system burst translated into memory burst size of 4 Read interrupt by read write interrupt by write CAS latency support 1 2 3 4 5 Fully programmable ac timing parameters on a per parameter basis Parameters are set according to the memory interface clock fre...

Page 2226: ..._cke1 sdrc 002 sdrc_d 31 16 DQ 31 16 Public Version SDRAM Controller SDRC Subsystem www ti com 10 2 2 SDRC Subsystem Environment 10 2 2 1 SDRC Subsystem Description Figure 10 42 shows the SDRC subsystem interfacing with one 16 and one 32 bit SDR external memories Figure 10 43 shows the SDRC subsystem interfacing with one 16 and one 32 bit DDR memories Figure 10 42 SDRC Subsystem Connections to SDR...

Page 2227: ...QS 1 0 DM 3 0 sdrc_cke1 nCLK sdrc 003 Public Version www ti com SDRAM Controller SDRC Subsystem Figure 10 43 SDRC Subsystem Connections to DDR SDRAM CAUTION Both memory types SRD DDR SDRAM cannot be connected simultaneously to the SDRC memory interface Table 10 95 lists SDRC subsystem I O pins Table 10 95 SDRC Subsystem I O Description Pin Type Description sdrc_d 31 0 I O 32 bit wide data bus sdrc...

Page 2228: ... ac parameters and their quantification are summarized in Section 10 2 5 3 1 Chip Select Configuration 10 2 2 2 3 Address Multiplexing A flexible address scheme has been added to support any new type of address scheme and SDRAM density This new address muxing scheme lets users choose a different bank mapping allocation by configuring the order of the bank and row address decoding column address al...

Page 2229: ... 64M x 16 BA0 BA1 2 A0 A9 A11 11 A0 A12 13 MUX12 1024 2 64M x 8 BA0 1 64M x 16 Table 10 97 SDRC Address Multiplexing Scheme Selection vs SDRAM Configurations x32 Memory Interface x32 Memory Interface Banks Column Row MUX Total Size Number of Device Address Address Scheme MBits Devices Organization BA0 1 A0 A7 8 A0 A11 12 MUX5 64 2 2M x 16 1 2M x 32 BA1 2 A0 A7 8 A0 A10 11 MUX3 64 1 2M x 32 BA0 BA1...

Page 2230: ... MUX16 2048 2 64M x 16 BA0 1 64M x 32 BA1 2 A0 A9 A11 11 A0 A12 13 MUX15 2048 4 64M x 8 BA0 2 64M x 16 1 64M x 32 Table 10 96 is valid per CS in the table the total size in Mbits corresponds to a single CS Both chips must use the same address scheme but can use different address multiplexing configurations Figure 10 44 through Figure 10 46 show all the SDRAM MUX schemes including the mapping of th...

Page 2231: ...tem address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address mapping b1 b0 Memory address 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 MUX7 MUX8 System address System address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address...

Page 2232: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address mapping Address mapping Address mapping Address mapping b1 b0 b1 b0 b1 b0 b1 b0 Memory address Memory address Memory address Memory addr...

Page 2233: ... 8 7 6 5 4 3 2 1 0 Address mapping Address mapping Address mapping b1 b0 b1 b0 b1 b0 Memory address Memory address Memory address 12 11 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 13 14 14 bit row 12 0 9 bit row 1...

Page 2234: ...3 1 Clocking Reset and Power Management Scheme 10 2 3 1 1 Clocking 10 2 3 1 1 1 SMS The SMS is a single clock domain module The same clock is used for the interconnect system interface the SDRC interface and all internal operations SMS_CLK comes internally from the PRCM module and runs at the L3 interconnect frequency It is also used as a functional clock for the SMS module The source of the SMS_C...

Page 2235: ...condition under control of the chip top level power manager SDRC_POWERON 1 when SDRC_GLOBALRESET is applied the SDRC registers and the FSM are not reset but the external SDRAM memory can be optionally placed in self refresh mode depending on the configuration of the SDRC SDRC_POWER_REG 7 SRFRONRESET bit 10 2 3 1 3 Software Reset The SMS and SDRC modules can be reset under software control through ...

Page 2236: ...0 2 4 SDRC Subsystem Functional Description The SMS optimizes the SDRAM memory usage to provide The QoS level required by each of the initiators in the system A VRFB module also called the 2D rotation engine that minimizes the SDRAM page miss penalty when accessing rotated that is nonsequentially addressed lines in a graphic frame buffer 10 2 4 1 SDRAM Memory Scheduler The SMS module is split into...

Page 2237: ...e Rotation settings Rotation settings Active context queue in band reponse qualifier field posted write Response sdrc 008 2D rotation engine VRFB Arbitration settings Debug port SDRC interface Pixel repack L3 interconnect interface Public Version www ti com SDRAM Controller SDRC Subsystem Figure 10 48 SMS Top Level Diagram 2237 SWPU177N December 2009 Revised November 2010 Memory Subsystem Copyrigh...

Page 2238: ... severely when the average memory access latency increases These initiators also generally have some significant bandwidth requirements All CPU cores are class 1 initiators Class 2 For all other devices possibly with high bandwidth requirements but without being too latency sensitive Associated initiators may also have significant requirements in terms of bandwidth but if the bandwidth budget requ...

Page 2239: ...complete burst is buffered into the FIFO The behavior is programmable on a per group basis using the BURST COMPLETE field of the SMS_CLASS_ARBITER0 SMS_CLASS_ARBITER1 and SMS_CLASS_ARBITER2 registers A per FIFO counter tracks the number of complete bursts in a FIFO 10 2 4 1 2 3 ExtendedGrant Feature EXTENDEDGRANT Field in SMS_CLASS_ARBITER0 SMS_CLASS_ARBITER1 and SMS_CLASS_ARBITER2 EXTENDEDGRANT i...

Page 2240: ...counter is reloaded with its programmed value when it reaches 0 10 2 4 1 3 Internal Class Arbitration Class 0 class 1 and class 2 internal arbitrations are performed according to the following rules Within a class a standard least recently used LRU policy is applied The LRU thread if not empty is granted when an arbitration decision occurs LRU is applied taking into account the ExtendedGrant NOfSe...

Page 2241: ...s attributes The read permission is initiator based and is controlled using the SMS SMS_RG_RDPERMi register The write permission is initiator based and is controlled using the SMS SMS_RG_WRPERMi register The REQINFO bits taken into account are the incoming MReqInfo attributes Debug privilege and attribute along with the host parameter decoded in the SMS module see the SMS SMS_RG_ATTi 31 0 REQINFO ...

Page 2242: ... an access to the external memory Compute the Region ID based on the transaction address Generate a violation if overlapping of firewall regions is detected From the Region ID get the attributes for the region that has been hit Check the transaction REQINFO attributes with respect to the region attributes debug privilege type and host Reject the transaction if the attributes are not compatible Fro...

Page 2243: ... to the concerned region occurs This violation is reported in the error log register Priority level handling is done in the hardware it does not involve any specific software development All transactions are checked including those the RE has processed When detecting a violation on an incoming request the SMS respects the response ordering within the faulty thread A violation flag is raised intern...

Page 2244: ...ature which decouples the system from the actual storage physical organization of the graphics data in the external memory The VRFB can be abstracted as a 3 port module Interconnect input port Interconnect output port Configuration port all programmable control registers are part of the SMS register file which is described in Section 10 2 4 1 5 3 VRFB Configuration Port 10 2 4 1 5 1 VRFB Input Por...

Page 2245: ...spaces It can manage up to 12 concurrent rotation settings The VRFB configuration port includes all the settings required to control the 12 rotation contexts This is an input only port All settings are provided from the SMS control register file For each of the 12 contexts the buffer physical base address image height and width and pixel size can be configured through the following registers where...

Page 2246: ...S_POW_CTRL 7 0 IDLEDELAY bit field When there is new activity on the interconnect interface the interconnect clock is restarted without any latency penalty It is recommended to enable this mode to reduce power consumption There is an internal interface clock gating strategy within the SDRC controller This power saving feature is always active 10 2 4 3 System Power Management The SMS can be configu...

Page 2247: ...Start Address CS1 start address is programmable The default base address for CS1 after reset is defined in the register description The SDRC 1G byte 8G bit address space is segmented so that 7 possible CS1 start address locations 8 in total minus 1 reserved for CS0 are defined by the SDRC SDRC_CS_CFG 3 0 CS1STARTHIGH field as shown in Figure 10 51 Each 128M byte address space is also segmented int...

Page 2248: ...llowed The SDRAM data bus width on each CS is determined by the SDRC SDRC_SHARING 11 9 CS0MUXCFG and SDRC SDRC_SHARING 14 12 CS1MUXCFG fields of the memory sharing registers 10 2 4 4 2 Bank Tracking The main state machine controls all the accesses to external memories The SDRC contains hardware for tracking open pages on a per bank basis Up to four open pages are tracked per CS for a maximum of ei...

Page 2249: ...SDRC SDRC_MCFG_p 26 24 RASWIDTH and SDRC SDRC_MCFG_p 22 20 CASWIDTH fields For more information about fixed address multiplexing configurations for SDRAM components see Section 10 2 2 2 3 Address Multiplexing 10 2 4 4 4 Bank Allocation Setting 10 2 4 4 4 1 System Address Decoding The SDRC has a 64 bit slave interface connected to the L3 main system interconnect The regular allocation is to see the...

Page 2250: ...resh sequence An active command to a row of a bank for which another row is already active can be issued only after the previous row has been closed The precharge command is used to deactivate the open row in a particular bank The bank is available for a subsequent row access some time after the row precharge command is issued A minimum time is needed to close and open a new row A subsequent activ...

Page 2251: ... column and row decoding of the incoming system address The BANKALLOCATION bit field can be set on a CS basis In the usual allocation the system address bus is seen as a concatenation of bank row column The system address received from the interconnect into the SDRC is composed of 2 system address bits used as the bank address going to SDRC controller sdrc_ba 1 0 pins 13 system address bits used a...

Page 2252: ...ernal SDRAM memory at the same time With this kind of scenario a lot of penalties are added because of rows opening and closing The BANKALLOCATION setting improves the latency for reading and writing operations by optimizing memory accesses through the reduction of deactivate sequence use thereby reducing time penalties The bank1 row bank0 column allocation is a good compromise between the legacy ...

Page 2253: ...ants to access It takes 6 tCK When one initiator wants to access a page this time in another bank there can be less page opening and closing For instance if the initiator wants to open a page in another bank where no page is open it takes only 3 tCK rather than 6 tCK if it was another page in the same bank 10 2 4 4 5 Data Multiplexing During Write Operations 10 2 4 4 5 1 External Bus Combinations ...

Page 2254: ...e highest memory address and Data 63 48 32 is written at the lowest memory address Figure 10 55 shows the data multiplexing scheme Figure 10 55 Data Multiplexing Scheme 10 2 4 4 6 Data Demultiplexing During Read Operations 10 2 4 4 6 1 External Bus Combinations The SDRC pin allocation scenarios are shown in Table 10 102 These scenarios are defined on a per CS basis for maximum flexibility The pin ...

Page 2255: ...Data 15 31 0 is read from the lowest memory address and Data 63 48 32 is read from the highest memory address For a 64 bit interconnect big endian read transaction on a 16 32 bit memory Data 15 31 0 is read from the highest memory address and Data 63 48 32 is read from the lowest memory address To preserve data integrity in all situations that is regardless of the effective scalar size of the tran...

Page 2256: ...ter within the SDRC generates a periodic event that triggers either a single refresh or a burst of consecutive refresh commands This is the standard refresh mode used when the system is active while the running applications regularly access the SDRAM An autorefresh command can also be applied using the SDRC SDRC_MANUAL_p register see Section 10 2 5 3 4 DLL CDL Configuration This method can be used...

Page 2257: ...or write request to another page in the same bank Autorefresh request a precharge all command is issued first Self refresh entry request a precharge all command is issued first Manual precharge all command 10 2 4 4 9 2 Dynamic Low Power Operating Modes The dynamic low power operating modes of the SDRC are designed to Control the external SDRAM clock s Control the internal clock gating of the SDRC ...

Page 2258: ...4 CLKCTRL bits Table 10 103 Dynamic Power Saving Configurations CLKCTRL EXTCLKDIS PWDENA CKE External SDRC CLK 1 SDRAM State Latency When Exiting Power Mode 0 0 0 Always high Always on Keep previous state 0 0 1 Low when no Always on Power down Zero latency penalty access 0 1 0 Always high Off when no access Keep previous state 0 1 1 Low when no Off when no access Power down One cycle penalty acces...

Page 2259: ...l SDRAM clock can be switched off by setting the SDRC SDRC_POWER_REG 3 EXTCLKDIS control bit to 1 Self refresh can be exited automatically if an access is initiated onto the CS Only DPD must be exited manually Possibility to put the memory in deep power down mode if supported by the SDRAM using the manual command register Each CS can be controlled independently The external SDRAM clock can be swit...

Page 2260: ...o need to use the DLL CDL for the SDR DRAM because data is strobed every clock cycle The DQS signals are left unconnected for SDR SDRAM memories DQS is propagated with the data thus reducing the impact of the propagation delay and is used by the receiver to sample the data The DLL CDL combination minimizes the negative effects caused by skews and jitters of clock signals The delay introduced by th...

Page 2261: ... read DQS signals are used to sample incoming data internally and hence must be delayed to create data setup and data hold time at the synchronization flip flop inputs as shown in the bottom waveforms of Figure 10 58 This is the goal of the DLL CDL module Figure 10 58 Required Synchronization DFF Input Signals 10 2 4 4 11 2 DLL CDL Module Architecture Figure 10 59 shows how the DLL CDL interacts w...

Page 2262: ...LL write CLK used in DDR mode to launch write data sdrc 016 Public Version SDRAM Controller SDRC Subsystem www ti com Figure 10 59 DLL CDL Architecture Figure 10 60 shows a simplified block diagram of the DLL CDL module 2262 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2263: ...rameters Write burst mode SDRC SDRC_MR_p 9 WBST bit where p 0 or 1 for SDRC CS0 or CS1 CAS latency SDRC SDRC_MR_p 6 4 CASL field Serial interleaved mode SDRC SDRC_MR_p 3 SIL bit Burst length SDRC SDRC_MR_p 2 0 BL field MR is accessible through SDRC SDRC_MR_p where p 0 or 1 for SDRC CS0 or CS1 Writing to SDRC SDRC_MR_p initiates an implicit load mode register command qualified by BA1 BA0 0 0 10 2 4...

Page 2264: ...must be enlarged To avoid deactivating region A and exposing its content to unwanted leakage region 1 can be used to mask this whole area during reprogramming When region A is correctly reprogrammed region 1 can be deactivated When all the required regions are programmed the locking mechanism allows freezing the configuration thus ensuring no further reprogramming 10 2 5 1 2 VRFB Context Configura...

Page 2265: ...SMS_ROT_SIZEn 10 0 IMAGEWIDTH 0x1A0 where n 1 Image height 304 SMS SMS_ROT_SIZEn 26 16 IMAGEHEIGHT 0x130 Configure the control parameters Pixel size example 2 bytes 21 bytes SMS SMS_ROT_CONTROLn 1 0 PS 0x1 where n 1 Page page size example 1024 bytes 64 bytes 16 bytes Page height example 16 rows 24 rows SMS SMS_ROT_CONTROLn 10 8 PH 0x4 Page width example 64 bytes 26 bytes SMS SMS_ROT_CONTROLn 6 4 P...

Page 2266: ...s are SMS SMS_CLASS_ARBITER0 through SMS SMS_CLASS_ARBITER2 One high priority FIFO queue in the class HIGHPRIOVECTOR field Number of consecutive transactions to perform EXTENDEDGRANT field Burst transaction submitted for arbitration immediately or after the burst has been buffered BURST COMPLETE field 10 2 5 1 4 Error Logging All data transfers in the SMS are full handshake The SMS uses this capab...

Page 2267: ...nd register A software controlled reset is also available by using the SDRC SDRC_SYSCONFIG 1 SOFTRESET bit set this bit to 1 to activate the reset The completion of the reset can be determined by reading the SDRC SDRC_SYSSTATUS 0 RESETDONE bit When the SDRC is reset due to the presence of either a soft or cold reset all SDRC flops are reset NOTE SDRC Requirement at First Power Up to Have sdrc_cke ...

Page 2268: ...e physical RAM address space in terms of 2M byte chunks B32NOT16 External device data bus width DEEPPD Set this bit if the memory supports deep power down mode This bit is only a flag for software It does not affect any SDRC function DDRTYPE Mobile DDR RAMTYPE Single Data Rate or Double Data Rate SDRAM NOTE Exported Register Reset Values and Lock Bit The reset values of SDRC SDRC_MCFG_p and SDRC S...

Page 2269: ... command period 3 tDQSS Write command to first DQS latching 1 0 75 1 25 CK transition tRPRE Read preamble 1 0 9 1 1 CK DQS is held low for read when driving on the same cycle as the read command is stopped NOTE The SDRC uses tXSR only when exiting self refresh mode regardless of the first command issued The SDRC systematically inserts an autorefresh command before it serves the first request 10 2 ...

Page 2270: ... by using any of the following scenarios Internal signals handshaking protocol with PRCM module Warm reset event DLLIDLE mode Power down mode The ENADLL bit controls the PWRDN mode of the DLL module The LOCKDLL bit sets the DLL in TrackedDelay lock or ModeFixedDelay unlock mode ModeFixedDelay mode is supported up to 83 MHz See Section 10 2 4 4 11 for more information on the CDL DLL module DLLMODEO...

Page 2271: ...ration This group contains two SDRC SDRC_RFR_CTRL_p registers that are defined on a per CS basis and contain the following bit fields SDRC SDRC_RFR_CTRL_p 1 0 ARE where p SDRC CS value 0 or 1 SDRC SDRC_RFR_CTRL_p 23 8 ARCV where p SDRC CS value 0 or 1 These bit fields can enable and disable autorefresh Autorefresh bursts of 1 4 and 8 are programmed using these fields The autorefresh burst starts w...

Page 2272: ...oder so that nRAS nCAS nWE and all the address inputs are ignored Command nCS nRAS nCAS nWE Inhibit H X X X NOP 0 H H H Precharge all CMDCODE 0x1 When the SDRC SDRC_MANUAL_p 3 0 CMDCODE field is programmed with 0x1 the SDRC issues a precharge all command The following table lists the status of the SDRC memory port signals During the command address A10 remains high and bank information BA0 and BA1...

Page 2273: ...e Exit self refresh CMDCODE 0x6 When the SDRC SDRC_MANUAL_p 3 0 CMDCODE field is programmed with 0x6 the SDRC executes the self refresh exit command and after meeting the tXSR timing parameter executes one autorefresh command to adhere to the memory protocol It is an exit self refresh command when CKE is detected high with a NOP command Self refresh is exited by restarting the external clock and t...

Page 2274: ...lease the force on these sdrc_cke signals by clearing the corresponding MUXMODE bit fields in CONTROL CONTROL_PADCONF_SAD2D_SBUSFLAG 18 16 and CONTROL CONTROL_PADCONF_SDRC_CKE1 2 0 bit fields for sdrc_cke0 and sdrc_cke1 respectively See Section 10 2 5 2 2 for more information on reset behavior 10 2 5 4 2 Read Write Access The commands required for a normal read write access are automatically gener...

Page 2275: ... 2 Program the CMDCODE field of the relevant manual command register to 0111 This sets the relevant CKE high 3 Program the CMDCODE field of the relevant manual command register to 0000 This executes a NOP command 4 Program the CMDCODE field of the relevant manual command register to 0001 This ensures that all banks are idle by executing a precharge The length of time the SDRC spends in power down ...

Page 2276: ...sh mode CMDCODE 0x5 There is no need for the software to disable the autorefresh in the SDRC SDRC_RFR_CTRL_p register before entering self refresh The autorefresh counter is reset in hardware so that an autorefresh cycle is automatically generated immediately after a self refresh exit and before any other command Self Refresh Exit Exit self refresh mode CMDCODE 0x6 If needed reconfigure SDRC regis...

Page 2277: ..._ERR_TYPE register to clear the active error status Executes error recovery from software 10 2 6 SDRC Use Cases and Tips 10 2 6 1 How to Program the VRFB 10 2 6 1 1 VRFB Rotation Mechanism An inherent limitation of SDRAM technology is high memory latency caused by page miss penalties incurred when downloading to a memory cache For example switching from one page to another in external memory can c...

Page 2278: ...iews With multiple views of the image the RE can change addresses and issue multiple requests to the SDRC so that a maximum of consecutive accesses is performed thus decreasing the number of page miss penalties The RE cannot reorder requests to the SDRAM A VRFB context defines the configuration used to access a picture in external SDRAM For each VRFB context a set of registers in the SMS describes...

Page 2279: ...ize used in the YUV standard is spread onto a 32 bit data structure This 32 bit data structure represents a packet of two pixels P0 and P1 Each element Y0 Y1 U and V is coded in 8 bits P0 Y0 U V and P1 Y1 U V There are 24 bits of information per pixel Y U and V however because the chrominance elements U and V are common to both P0 and P1 pixels only 16 bits are used to store a pixel in YUV format ...

Page 2280: ...he YUV pixel data Is spread onto a 32 bit word representing 2 pixels Is the programmed image size bigger than the actual image Initiator programs its DMA engine an additional offset to the base address may be required Yes Indicate the physical base address of the picture in SDRAM Set the SMS_ROT_PHYSICAL_BAi 30 0 PHYSICALBA field No End configuration of VRFB context i Once the VRFB context has bee...

Page 2281: ...RFB context 1 Once the VRFB context1 is configured all data accesses to a virtual address space is automatically translated VRFB virtual address spaces for context 1 0 degree view 0x7400 0000 0x74FF FFFF 90 degree view 0x7500 0000 0x75FF FFFF 180 degree view 0x7600 0000 0x76FF FFFF 270 degree view 0x7700 0000 0x77FF FFFF Standard used Image width pixels SMS_ROT_SIZE1 10 0 IMAGEWIDTH 120 Image heig...

Page 2282: ...n pixels 1 Working on a page basis the image size must be a multiple of the page size 2 Depending on the page dimensions and the image size the programmed image size 256 is larger than the actual image size 240 To use VRFB rotation each initiator must configure its DMA engine correctly an additional offset to the base address may be required For details see Chapter 7 Display Subsystem 10 2 6 1 3 A...

Page 2283: ...tem Display subsystem External DDR VRFB The following conditions exist for this application QVGA image size is 320 240 width height Pixel format is YUV4 2 2 YUV2 in little endian The rotation view is 90 degrees The VRFB context is VRFB context 1 The camera module writes QVGA images to external DRAM at 15 fps The display subsystem reads QVGA images from external DDR32 at 60 fps and displays them on...

Page 2284: ...tation Page arrangement Usually the recommendation is to have a square page If this is not possible the longest page side should correspond to the access direction that requires the maximum bandwidth set the longest page side to optimize the page break Using a 1024 byte page size a 32 32 byte page arrangement is used as an example With a 2K byte page organized as a 32 64 byte page depending on the...

Page 2285: ...ups Transaction A full burst request Arbitration grant Authorization of a service requested by an initiator The arbitration policy operates on two interdependent mechanisms The arbitration decision which establishes priority for processing requests The question Which request is processed next occurs on a transaction boundary Arbitration granularity which determines the length of an arbitration gra...

Page 2286: ...rviced 10 2 6 2 2 1 Burst Complete Mechanism The burst complete mechanism applies granularity to the arbitration scheme Access cannot be granted to a group within a class until a complete burst has been stored in the FIFO Example There is no ongoing transaction on Class 0 The initiator requests a 4 64 bit burst on Group 3 of Class 2 SMS_CLASS_ARBITER2 27 BURST COMPLETE 0x1 Only 2 64 bit requests a...

Page 2287: ...64 bits requests to be stored before processing the complete burst transaction Then check the incoming requests and wait for the arbitration decision to apply Request for transaction on class 0 occurs during transaction of class 2 group 3 sdrc 025 Public Version www ti com SDRAM Controller SDRC Subsystem Figure 10 68 BURST COMPLETE On Class 2 Group 3 2287 SWPU177N December 2009 Revised November 20...

Page 2288: ...s serviced for M cycles and is directly followed by service to Class 2 for N cycles If Class 2 is serviced first for N cycles then Class 1 is granted for M cycles Arbitration is given more importance Class 1 2 is favored over Class 2 1 As shown in Figure 10 69 two arbitration schemes can appear Class 0 is serviced first followed by Class 1 and then Class 2 C0 C1 C2 Class 0 is serviced first follow...

Page 2289: ...as not been received the arbitration grant is moved so that a request from another thread is serviced Figure 10 70 Idle Cycle Mechanism Within A Burst Two bursts must be serviced at the burst boundary One idle cycle after servicing these two bursts the arbitration grant is moved 10 2 6 2 3 2 Extended Grant Mechanism The extended grant mechanism gives additional granularity to the arbitration An ex...

Page 2290: ...he SMS module is based on several mechanisms giving even more importance to the arbitration Wen we need to grant the access on a transaction boundary we recall that the question we have to answer is What will be the next request to be serviced and for how long Thus the two important concepts regarding the SMS mode of operation are The arbitration decision we choose the next request to be serviced ...

Page 2291: ...SS_ARBITER 7 0 CLASS1PRIO field defines the number M of transactions dedicated to class 1 SMS_INTERCLASS_ARBITER 23 16 CLASS2PRIO field defines the number N of transactions dedicated to class 2 A The arbitration decision PWM Arbitration sdrc 029 Public Version www ti com SDRAM Controller SDRC Subsystem Figure 10 72 Arbitration Between Classes 2291 SWPU177N December 2009 Revised November 2010 Memor...

Page 2292: ... 0 Win Read the HIGHPRIOVECTOR field Group 0 Win Group 1 Win Group 0 higher priority Group 1 higher priority Group 1 empty No Yes Yes No Request is part of burst and BURSTCOMPLETE 1 and The full burst is not available No Yes Yes Group 1 Win No For class 1 group 0 read the SMS_CLASS_ARBITER1 24 BURSTCOMPLETE bit For class 1 group 1 read the SMS_CLASS_ARBITER1 25 BURSTCOMPLETE bit For class 1 group ...

Page 2293: ...PRIOVECTOR B B Yes LRU policy No 4 reqs HIGHPRIOVECTOR B B Yes LRU policy No At this time it is ensure that for each group containing a req The request is part of the burst the BURSTCOMPLETE ttribute is set and the full burst is not available Class 0 class 1 a simultaneous decision can occur between 2 groups 1 group or none Class 2 a simultaneous decision can occur between 4 reqs stored in the 4 g...

Page 2294: ...erted after RdEx and before its associated unlocking WNP Per group define the number of consecutive transactions this group can be granted The priority can be given to a group within a class until the complete burst that is to proceed has been stored into the FIFO A burst transaction should always be completed sdrc 032 Only if BURSTCOMPLETE is active for the request which has access Public Version...

Page 2295: ...ches 1 768G bytes 1G byte of CS memory space CS0 and CS1 memory spaces the SDRC controller automatically accesses the two external memory devices through direct accesses addresses are simply translated 768M bytes of virtual address space address space 0 and address space 1 the SDRC controller automatically accesses the two external memory devices trough re organized access requests are modified ac...

Page 2296: ...00 0000 5 0xE400 0000 0xE500 0000 0xE600 0000 0xE700 0000 6 0xE800 0000 0xE900 0000 0xEA00 0000 0xEB00 0000 7 0xEC00 0000 0xED00 0000 0xEE00 0000 0xEF00 0000 8 0xF000 0000 0xF100 0000 0xF200 0000 0xF300 0000 9 0xF400 0000 0xF500 0000 0xF600 0000 0xF700 0000 10 0xF800 0000 0xF900 0000 0xFA00 0000 0xFB00 0000 11 0xFC00 0000 0xFD00 0000 0xFE00 0000 0xFF00 0000 The physical address of a page is calcul...

Page 2297: ...is SDRAM may or may not be supported by the SDRC 10 2 6 3 2 2 CS Size Each chip select has its programmable size The CS size is expressed in SDRC_MCFG_p 17 8 RAMSIZE p 0 or 1 for CS0 or CS1 as a number of 2M byte chunks For instance when connecting a 256M bit SDRAM memory see the mux scheme MUX7 in Table 10 96 to the SDRC controller RAMSIZE must be set with the value 0x010 32M bytes 2MB 16 10 2 6 ...

Page 2298: ...given 128M byte address space to one of the four 32M byte address spaces 0x00 for the first up to 0x11 for the fourth Therefore for a start address of 0x2000 0000 SDRC point of view when connecting a 2048 Mbit SDRAM memory 64M 32 such as in MUX25 Table 10 97 the SDRC_CS_CFG 9 8 CS1STARTLOW bit field must be set to 0x00 the first 32M byte address space as shown in Figure 10 77 and the SDRC_CS_CFG 3...

Page 2299: ...e single data rate M SDR SDRAMs or up to two low power double data rate LPDDR SDRAMs Operating voltage VDD VDDQ 1 7 V to 1 9 V VSS VSSQ 0 0 V and LVCMOS 1 8 V I Os Temperature range 25 C to 85 C ambient Maximum supported operating Frequency 200 MHz condition single device optimized board layout Maximum supported memory size 128M bytes per external SDRAM bank 256M and 512M byte SDRAM may be support...

Page 2300: ...Low power DDR yes Operating voltage VDD VDDQ 1 7V to 1 9V VSS VSSQ 0 8xVDDQ High level VDDQ yes 0 0V and LVCMOS 1 8V I Os 0 3V 0 3V Low level 0 2 VDDQ 1 8V I O power 1 95V Max operating frequency 200 MHz 200 MHz DDR400 yes Memory size Min 16 Mbits max 1024M bits 2048 and 512 Mbits yes 4096M bits may be supported Number of banks 2 16 and 32 Mb or 4 other 4 yes Data path SDRC SDRAM 16 and 32 bit 32 ...

Page 2301: ...0 0060 where k j 1 3 0x0000 0020 k 0x0000 0020 k SMS_RG_ENDj 2 RW 32 0x0000 0064 0x6C00 0064 where k j 1 3 0x0000 0020 k 0x0000 0020 k SMS_CLASS_ARBITER0 RW 32 0x0000 0150 0x6C00 0150 SMS_CLASS_ARBITER1 RW 32 0x0000 0154 0x6C00 0154 SMS_CLASS_ARBITER2 RW 32 0x0000 0158 0x6C00 0158 SMS_INTERCLASS_ARBITER RW 32 0x0000 0160 0x6C00 0160 SMS_CLASS_ROTATIONm 4 RW 32 0x0000 0164 0x6C00 0164 0x0000 0004 m...

Page 2302: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AUTOIDLE RESERVED RESERVED RESERVED SIDLEMODE SOFTRESET Bits Field Name Description Type Reset 31 9 RESERVED Write 0s for future compatibility Read returns 0s RW 0x000000 8 RESERVED Write 0s for future compatibility Read returns 0s RW 0x0 7 5 RESERVED Write 0s for future compatibility Read returns 0s RW 0x0 4 3 SIDLEMODE Power management Req Ack Control...

Page 2303: ... returns 0s 0 RESETDONE Internal reset monitoring R 0x 0x0 Internal module reset is ongoing 0x1 Reset complete The module is ready to be used Table 10 118 Register Call Summary for Register SMS_SYSSTATUS SDRAM Controller SDRC Subsystem SMS Register Summary 0 Table 10 119 SMS_RG_ATTi Address Offset 0x0000 0048 0x0000 0020 i Index i 0 to 7 Physical Address 0x6C00 0048 0x0000 0020 i Instance SMS Desc...

Page 2304: ...Table 10 122 Register Call Summary for Register SMS_RG_RDPERMi SDRAM Controller SDRC Subsystem Firewalls 0 SMS Firewall Usage 1 SMS Register Summary 2 Table 10 123 SMS_RG_WRPERMi Address Offset 0x0000 0058 0x0000 0020 i Index i 0 to 7 Physical Address 0x6C00 0058 0x0000 0020 i Instance SMS Description This register provides the list of all initiators that have permission for writing to that memory...

Page 2305: ...AM Controller SDRC Subsystem SMS Firewall Usage 0 1 SMS Register Summary 2 Table 10 127 SMS_RG_ENDj Address Offset 0x0000 0064 0x0000 0020 K Index j 1 to 7 and k 0 to 8 Physical Address 0x6C00 0064 0x0000 0020 K Instance SMS Description This register provides the region j end address lowest address outside the region with a 64 KB granularity Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 2306: ...umber of consecutive services a group is granted 2 bits per group ExtendedGrant 2 k 1 2 k k 6 to 7 EXTENDEDGRANT 21 20 is for group number 6 EXTENDEDGRANT 23 22 is for group number 7 0x1 1 service for group k when granted 0x2 2 services for group k when granted 0x3 3 services for group k when granted 19 8 RESERVED Write 0s for future compatibility Read returns 0s RW 0x000 7 6 HIGHPRIOVECTOR High p...

Page 2307: ...W 0x000 11 8 EXTENDEDGRANT Extended grant service inside a class RW 0x5 Vector specifying the number of consecutive services a group is granted 2 bits per group ExtendedGrant 2 k 1 2 k k 0 to 1 EXTENDEDGRANT 9 8 is for group number 0 EXTENDEDGRANT 11 10 is for group number 1 0x1 1 service for group k when granted 0x2 2 services for group k when granted 0x3 3 services for group k when granted 7 2 R...

Page 2308: ...er of consecutive services a group is RW 0x55 granted 2 bits per group ExtendedGrant 2 k 1 2 k k 2 to 5 EXTENDEDGRANT 19 18 is for group number 5 EXTENDEDGRANT 17 16 is for group number 4 EXTENDEDGRANT 15 14 is for group number 3 EXTENDEDGRANT 13 12 is for group number 2 0x1 1 service for group k when granted 0x2 2 services for group k when granted 0x3 3 services for group k when granted 11 6 RESE...

Page 2309: ...CLASS_ARBITER SDRAM Controller SDRC Subsystem Arbitration Decision 0 1 SMS Register Summary 2 Table 10 137 SMS_CLASS_ROTATIONm Address Offset 0x0000 0164 0x0000 0004 m Index m 0 to 2 Physical Address 0x6C00 0164 0x0000 0004 m Instance SMS Description This register controls the number of consecutive services that is allocated to a thread whose transactions have been split by the rotation engine Typ...

Page 2310: ... Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ILLEGALCMD ERRORVALID ERRORMCMD ERRORCONNID ERRORREGIONID UNEXPECTEDADD UNEXPECTEDREQ ERRORSECOVERLAP Bits Field Name Description Type Reset 31 27 RESERVED Write 0s for future compatibility Read returns 0s RW 0x00 26 24 ERRORREGIONID ID of the region ...

Page 2311: ...d on the L3 interface RW 0x0 Read 0x0 No illegal command received Write 0x0 No effect Read 0x1 Illegal command has been received Write 0x1 Clear ILLEGALCMD bit field 7 4 RESERVED Write 0s for future compatibility RW 0x0 Read returns 0s 3 ERRORSECOVERLAP Protection region overlapping error RW 0x0 Read 0x0 No overlap violation detected Write 0x0 No effect Read 0x1 A protection region overlap violati...

Page 2312: ...80 0x0000 0010 n Instance SMS Description This register configures the virtual rotated frame buffer module for context n Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PH PW PS RESERVED RESERVED Bits Field Name Description Type Reset 31 11 RESERVED Write 0s for future compatibility Read returns 0s RW 0x000000 10 8 PH Exponent based 2 value 2p...

Page 2313: ...ve Use Case and Tips 5 6 SMS Register Summary 7 Table 10 149 SMS_ROT_PHYSICAL_BAn Address Offset 0x0000 0188 0x0000 0010 n Index n 0 to 11 Physical Address 0x6C00 0188 0x0000 0010 n Instance SMS Description This register allows to configure the physical base address for context n Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHYSICALBA RESERVED Bits ...

Page 2314: ...80 0x6D00 0080 0x0000 0030 p 0x0000 0030 p SDRC_MR_p 1 RW 32 0x0000 0084 0x6D00 0084 0x0000 0030 p 0x0000 0030 p SDRC_EMR2_p 1 RW 32 0x0000 008C 0x6D00 008C 0x0000 0030 p 0x0000 0030 p SDRC_ACTIM_CTRLA_p 1 RW 32 0x0000 009C 0x6D00 009C 0x0000 0028 p 0x0000 0028 p SDRC_ACTIM_CTRLB_p 1 RW 32 0x0000 00A0 0x6D00 00A0 0x0000 0028 p 0x0000 0028 p SDRC_RFR_CTRL_p 1 RW 32 0x0000 00A4 0x6D00 00A4 0x0000 00...

Page 2315: ...NOMEMORYMRS No external memory MRS command RW 0x0 0x0 When set to 0 the SDRC internal SDRC_MR_p and SDRC_EMR2_p registers both CS are written and MR EMR2 commands are performed to the corresponding registers of the external SDRAM 0x1 When set to 1 only SDRC internal SDRC_MR_p and SDRC_EMR2_p registers both CS are written no MR or EMR2 commands are performed to SDRAM 7 5 RESERVED Write 0s for futur...

Page 2316: ...RVED Reserved for interconnect socket status information R 0x00 Read returns 0 0 RESETDONE Internal reset monitoring R 0x 0x0 Internal module reset is ongoing 0x1 Reset completed The module is ready to be used Table 10 158 Register Call Summary for Register SDRC_SYSSTATUS SDRAM Controller SDRC Subsystem Reset Behavior 0 SDRC Register Summary 1 Table 10 159 SDRC_CS_CFG Address Offset 0x0000 0040 Ph...

Page 2317: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED LOCK RESERVED CS1MUXCFG CS0MUXCFG SDRCTRISTATE Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility RW 0x0 Read returns 0 30 LOCK Read only access lock bit RW See 1 0x0 This register is fully writable 0x1 When this bit is set the register can not be unset until next re...

Page 2318: ...ING SDRAM Controller SDRC Subsystem CS0 CS1 Memory Spaces 0 1 Data Multiplexing During Write Operations 2 3 4 Data Demultiplexing During Read Operations 5 6 Memory Configuration 7 8 SDRC Register Summary 9 Table 10 163 SDRC_ERR_ADDR Address Offset 0x0000 0048 Physical Address 0x6D00 0048 Instance SDRC Description This register captures the address of the last illegal access received on the interco...

Page 2319: ...m request was to an address outside the memory space Write 0x0 Clear ErrorAdd bit field Read 0x1 The system request was to an address outside the register space Write 0x1 No effect Read 0x2 No Err Add Not an address error Write 0x2 No effect Read 0x3 No Err Add Not an address error Write 0x3 No effect 1 ERRORDPD Transaction error while the memory is in deep power down mode RW 0x0 Read 0x0 The memo...

Page 2320: ...VED Write 0s for future compatibility Read returns 0 RW 0x00 7 RESERVED Reserved RW 0x0 6 5 DLLMODEONIDLEREQ Selects the DLL mode upon hardware idle request RW 0x0 0x0 DLL in Power down mode upon hardware idle request 0x1 DLL in DLL idle mode upon hardware idle request 0x2 No action upon hardware idle request Input clock frequency must not be changed 0x3 Reserved for future use no action upon hard...

Page 2321: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED LOCKSTATUS Bits Field Name Description Type Reset 31 3 RESERVED Reads return zeros R 0x00000000 2 LOCKSTATUS DLL lock status R 0x0 0x0 The DLL is not locked 0x1 The DLL is locked 1 RESERVED Reads return zero R 0x0 0 RESERVED Reads return zero R 0x0 Table 10 170 Register Call Summary for Register...

Page 2322: ...hen on hardware idle request RW 0x0 0x0 Feature disabled 0x1 Feature enabled 5 4 CLKCTRL Clock control feature defines clock gating and self refresh RW 0x0 0x0 No auto clk feature turned on 0x1 Enable internal clock gating on timeout of Auto_cnt 0x2 Enable self refresh on timeout of Auto_cnt 0x3 Reserved 3 EXTCLKDIS Disable the clock provided to the external memories RW 0x0 0x0 Enable clock 0x1 Di...

Page 2323: ...S address width RW See 1 0x0 RAS width 11 bits 0x1 RAS width 12 bits 0x2 RAS width 13 bits 0x3 RAS width 14 bits 0x4 RAS width 15 bits 0x5 RAS width 16 bits Must not be used 0x6 RAS width 17 bits Must not be used 0x7 RAS width 18 bits Must not be used 23 RESERVED Write 0s for future compatibility Read returns 0 RW See 1 22 20 CASWIDTH CAS address width RW See 1 0x0 CAS width 5 bits 0x1 CAS width 6...

Page 2324: ... See the note in Section 10 2 5 3 2 and Section 13 4 9 SDRC Registers in Chapter 13 System Control Module Table 10 174 Register Call Summary for Register SDRC_MCFG_p SDRAM Controller SDRC Subsystem Address Multiplexing 0 1 2 CS0 CS1 Memory Spaces 3 4 Address Multiplexing 5 6 7 8 Bank Allocation Setting 9 10 11 Chip Select Configuration 13 14 15 Memory Configuration 16 17 18 CS Memory Spaces 19 20 ...

Page 2325: ...1B Address mux scheme 28 0x1C Address mux scheme 29 19 ADDRMUXLEGACY Selects the fixed address muxing scheme or the flexible RW 0x address muxing scheme 0x0 Fixed address mux scheme 0x1 Flexible address mux scheme 18 RESERVED Write 0s for future compatibility Read returns 0 RW 0x 17 8 RAMSIZE RAM address space size number of 2 MB chunks RW 0x 7 6 BANKALLOCATION SDRAM banks mapping Selects the posi...

Page 2326: ... 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CASL BL SIL WBST ZERO_1 ZERO_0 Bits Field Name Description Type Reset 31 12 RESERVED Write 0s for future compatibility Read returns 0s RW 0x00000 11 10 ZERO_1 Write 0s as required by memory specifications Read returns 0 RW 0x0 9 WBST Write burst support must be zero RW 0x0 0x0 Write burst equals read burst 0x1 Write burst disable single write access only 8 7 ZER...

Page 2327: ...ad access is performed at that address Load into memory on interconnect write access using MRS command with BA1 BA0 1 0 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ZERO DS TCSR PASR Bits Field Name Description Type Reset 31 12 RESERVED Write 0s for future compatibility Read returns 0s RW 0x00000 11 7 ZERO Write 0s as required by memory spe...

Page 2328: ...21 18 TRAS Row active time RW 0x0 17 15 TRP Row precharge time RW 0x0 14 12 TRCD Row to column delay time RW 0x0 11 9 TRRD Active to active command period RW 0x0 8 6 TDPL Data in to precharge command write recovery time tWR RW 0x0 5 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 4 0 TDAL Data in to active command RW 0x00 Table 10 180 Register Call Summary for Register SDRC_ACTIM_...

Page 2329: ...roller SDRC Subsystem SDRAM AC Timing Parameters 0 SDRC Register Summary 1 Table 10 183 SDRC_RFR_CTRL_p Address Offset 0x0000 00A4 0x0000 0030 p Index p 0 to 1 Physical Address 0x6D00 00A4 0x0000 0030 p Instance SDRC Description SDRAM memory autorefresh control Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ARCV RESERVED ARE Bits Field Name D...

Page 2330: ...0 15 4 RESERVED Write 0s for future compatibility Read returns 0s RW 0x000 3 0 CMDCODE Memory command opcode other values reserved for future RW 0x0 implementations 0x0 NOP command no parameter 0x1 Precharge all command no parameter 0x2 Autorefresh command no parameter 0x3 Enter deep power down no parameter 0x4 Exit deep power down no parameter 0x5 Enter self refresh no parameter 0x6 Exit self ref...

Page 2331: ...eparate on chip memory controllers one connected to an on chip ROM OCM_ROM and the other connected to an on chip RAM OCM_RAM Each memory controller has its own dedicated interface to the L3 interconnect Figure 10 78 is an overview of the OCM subsystem Figure 10 78 OCM Subsystem Overview Multiple L3 initiators such as remote devices have access to the RAM through 2D 3D graphics the MPU subsystem sD...

Page 2332: ... clock OCM_CLK comes from the PRCM module and runs at the L3 interconnect frequency The OCM_CLK source is PRCM CORE_L3_ICLK output This clock is also used as the functional clock for the OCM module For the OCM subsystem no register enables the gating of OCM_CLK However OCM does support the handshaking protocol with the PRCM module It is not programmable by software The following signals support th...

Page 2333: ...clock frequency The COM_ROM needs three cycles for initial access and one cycle per subsequent access The memory space of the embedded ROM starts at 0x4001 4000 and ends at 0x4001 BFFF 10 3 3 2 OCM_RAM By default only 2K bytes are available after reset however the configuration can then be changed to adapt to booting flashing normal boot or to any application requirement The device embedded RAM ha...

Page 2335: ...y access SDMA module Topic Page 11 1 SDMA Overview 2336 11 2 SDMA Environment 2338 11 3 SDMA Integration 2340 11 4 SDMA Functional Description 2346 11 5 SDMA Basic Programming Model 2368 11 6 SDMA Register Manual 2374 2335 SWPU177N December 2009 Revised November 2010 SDMA Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2336: ...ta transfer support in either direction between Memory and memory Memory and peripheral device 32 logical DMA channels supporting Multiple concurrent transfers Independent transfer profile for each channel 8 bit 16 bit or 32 bit data element transfer size Software triggered or hardware synchronized transfers Flexible source and destination address generation Burst read and write Chained multiple c...

Page 2337: ...odule has three ports one read one write and one configuration port and provides multiple logical channel support A dynamically allocated FIFO queue memory pool provides buffering between the read and write ports Read and write ports are multithreaded two threads for the write port and four threads for the read port this means that each transaction is flagged by a thread ID 0 1 2 or 3 in the reque...

Page 2338: ...active low 1 sys_ndmareq1 I External DMA request signal active low 1 sys_ndmareq2 I External DMA request signal active low 1 sys_ndmareq3 I External DMA request signal active low 1 1 I Input O Output NOTE External SDMA requests can be configured to be either edge or transition level sensitive by the system control module For more information see Section 11 2 3 SDMA Request Scheme 11 2 2 External S...

Page 2339: ...default after cold reset See Chapter 13 System Control Module for instructions on multiplexing out the four signal lines to pins 11 2 3 SDMA Request Scheme The hardware DMA request line schemes can be either edge sensitive or transition sensitive The sensitivity selection of the sys_ndmareq 3 0 lines can be configured in the system control module through the following register bits CONTROL_DEVCONF...

Page 2340: ...E_L3_ICLK When the deassertion time is less than one clock cycle the SDMA might not detect the deassertion When the channel is enabled one cycle after a DMA request is disabled the channel detects the DMA request and starts the corresponding transfer When the channel is enabled two cycles after the DMA request is disabled the channel does not detect the DMA request Figure 11 4 Transition Sensitive...

Page 2341: ...on 11 3 1 Clocking Reset and Power Management Scheme 11 3 1 1 Power Domain The SDMA controller is part of the CORE power domain 11 3 1 2 Clocking The SDMA controller uses two clock domains CORE_L4_ICLK supports the configuration port CORE_L3_ICLK is both a functional clock for all internal logic and an interface clock for the two master read and write ports The SDMA controller supports a software ...

Page 2342: ... goes into standby mode Smart standby mode MIDLEMODE 0x2 The module enters standby mode when All DMA channels are disabled OR No no synchronous channels are enabled and if hardware synchronous channels are enabled then there should not be any hardware request asserted and there should not be any pending request in DMA4 module 11 3 1 4 3 Idle Mode The module can be configured using the DMA4_OCP_SYS...

Page 2343: ...t Read the DMA4_IRQSTATUS_Lj LCHi LCH0 to LCH31 If LCHi 1 channel i is the originator of the interrupt Identify the interrupt event Read the LCHi DMA4_CSRi For example if the drop event the DMA4_CSRi 1 DROP bit is 1 there will be a request collision The interrupt event status bit in the DMA4_CSRi register is immediately reset after it is written to 1 The interrupt status bit in the DMA4_IRQSTATUS_...

Page 2344: ... request S_DMA_31 MCBSP1_DMA_RX MCBSP module 1 receive request S_DMA_32 MCBSP2_DMA_TX MCBSP module 2 transmit request S_DMA_33 MCBSP2_DMA_RX MCBSP module 2 receive request S_DMA_34 SPI1_DMA_TX0 McSPI module 1 transmit request channel 0 S_DMA_35 SPI1_DMA_RX0 McSPI module 1 receive request channel 0 S_DMA_36 SPI1_DMA_TX1 McSPI module 1 transmit request channel 1 S_DMA_37 SPI1_DMA_RX1 McSPI module 1 ...

Page 2345: ...erved Reserved S_DMA_69 SPI4_DMA_TX0 McSPI module 4 transmit request channel 0 S_DMA_70 SPI4_DMA_RX0 McSPI module 4 receive request channel 0 S_DMA_71 DSS_DMA0 Display subsystem DMA request 0 DSI S_DMA_72 DSS_DMA1 Display subsystem DMA request 1 DSI S_DMA_73 DSS_DMA2 Display subsystem DMA request 2 DSI S_DMA_74 DSS_DMA3 Display subsystem DMA request 3 DSI or RFBI S_DMA_75 Reserved Reserved S_DMA_7...

Page 2346: ...lly tailored to the requirements of the application Figure 11 6 shows the SDMA controller top level block diagram Figure 11 6 SDMA Controller Top Level Block Diagram 11 4 1 Logical Channel Transfer Overview As Figure 11 6 shows the SDMA module has one read port and one write port operating independently of each other Buffering is provided between the read and write ports through a FIFO queue memor...

Page 2347: ... scheduling policy When either the read or write port becomes available the port access scheduler selects the next logical channel for which to perform a DMA transaction from either the high or low priority queue When the current DMA transaction single or burst access is complete and the full DMA transfer is not finished the logical channel returns to the tail of the queue Because the port access ...

Page 2348: ...r both the source and destination However the way in which the data is represented addressing profile mode is independently programmable for the source and destination devices using one of these four addressing modes Constant The address remains the same for consecutive element accesses Post increment The address increases by the element size ES even across consecutive frames Single index The addr...

Page 2349: ... elements between the start of the current element n to the start of next element n 1 Element counter A counter that is re initiated with the number of elements per frame or per transfer Decreased by 1 for each element transferred The initial value is configured in the register DMA channel element number DMA4_CENi F is in bytes specified in a configuration register 2147483648 FI 2147483647 Stride ...

Page 2350: ...rt address Address pointer after element 0 frame 0 Address pointer after adding element index of 5 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 Element 0 Frame 0 Element 1 Frame 0 Element 0 Frame 1 Address pointer after element 1 frame 0 Address pointer after adding frame index of 5 dma 009 Public Version SDMA Functional Description www ti com Figure 11 7 Example Showing Double Inde...

Page 2351: ... for Rotation 90 Rotation 180 Rotation 270 Rotation Double indexing on destination Base address ES y 1 ES x y 1 ES y x 1 write Element index EI ES y 1 1 1 2 ES 1 ES y 1 Frame index FI 1 ES x 1 y 2 1 2 ES 1 ES x 1 y Double indexing on source read Base address ES x y 1 ES x y 1 ES x 1 Element index EI 1 ES x 1 1 2 ES ES x 1 1 Frame index FI 1 ES y 1 x 1 2 ES 1 ES y 1 x 2 Table 11 6 and Figure 11 11 ...

Page 2352: ...ment SW 1 SH 1 38241 elements Start address 0x100000 0x200000 SH 1 x ES 0x20027C EN SW SW EI Stride EI 1 ES 1 1 Stride EI 1 ES 1 637 FN SH SH FI Stride FI 1 ES 1 1 Stride FI 1 ES 1 152967 Figure 11 11 Example of a 90 Clockwise Image Rotation 11 4 4 Packed Accesses When the logical channel ES is less than the DMA module read write port size and the addressing profile supports it that is post increm...

Page 2353: ...ecified as little endian or big endian through the DMA4_CSDPi register for the particular logical channel If the endianism of the source and destination differ and the logical channel ES is less than the SDMA module read write port size an endianism conversion is applied to the data before it is written to the destination When transferring data between a source and a destination with different end...

Page 2354: ... size of the buffer Packet transfer must be used only where the source or destination is addressed in constant addressing mode because FI registers are reused to specify size of the packet To support the burst mode the logical channel must also be configured to use the target port packed access mode The packet size is configured based on the source destination synchronization select bit in the DMA...

Page 2355: ...er 0x2 However in a packet synchronization mode the last transaction of each packet in the transfer is WNP only if buffering disable is on even if the write mode is specified as WLNP Regardless of whether buffering disable is enabled or disabled the packet interrupt is not generated in the packet source synchronized mode CAUTION The BUFFERING_DISABLE bit field of the DMA4_CCRi register must be fil...

Page 2356: ...d ThreadID 0 is reserved for high priority channels DMA4_GCR 13 12 0x2 Read ThreadID 0 and Read ThreadID 1 are reserved for high priority channels DMA4_GCR 13 12 0x3 Read ThreadID 0 Read ThreadID 1 and Read ThreadID 2 are reserved for high priority channels Write port priority thread reservation DMA4_GCR 13 12 0x0 No ThreadID is reserved for high priority channels DMA4_GCR 13 12 0x1 Write ThreadID...

Page 2357: ...a separate DMA4 channel configured to transfer each field in the header Channels can be chained through each channel DMA4_CLNK_CTRLi register When the transfer for the first channel completes the next channel in the chain is enabled The number of channels in the chain that are configured for hardware synchronized transfers is flexible although typically it might be all none or just the first one T...

Page 2358: ...ware DMA request is generated To associate a frame synchronization to each DMA request is possible but this limits the maximum transfer size Indeed the maximum transfer size is proportional to the FIFO depth of the peripheral maximum_transfer_size peripheral_FIFO_depth x number_of_frame_in_block The packet synchronization allows to dissociate the transfer size from the FIFO depth of the peripheral...

Page 2359: ...ock x Number_of_Element_in_Frame x Element_Size If the DMA channel packet burst access is across packet boundary DMA hardware automatically splits this packing burst access into multiple smaller accesses which will be aligned on packet boundary Otherwise the DMA transfers data as usual packing burst access 11 4 14 Graphics Acceleration Support The SDMA supports two graphic acceleration features Tr...

Page 2360: ...l was hardware source synchronized with buffering Enabled DMA4_CCRi 25 BUFFERING_DISABLE 0 In that case the fifo will be drained in order to avoid losing data See Section 11 4 18 for details on this feature 11 4 18 FIFO Draining Mechanism When a source synchronized channel is disabled during a transfer then the current hardware request element packet frame block service is completed and the channe...

Page 2361: ...mes and each frame includes EN elements In a super block The block size FN x EN x ES can be changed in the linked list by loading an updated transfer descriptor The end of the super block is signaled in the last descriptor associated with the last block Generally for a given link list transfer the logical channel is set at the beginning of the transfer and the logical channel configurations for th...

Page 2362: ... load or data load B Corresponds to the end of block enable bit BLOCK_IE of the DMA4_CICRi register Valid only for type 3 This value is don t care for descriptor types 1 and 2 where DMA4_CICRi is fully specified Nxt_Dv Nxt_Sv Mapped in the DMA4_CDPi register They indicate one of the following possibilities Next descriptor contains an updated destination or source address Next descriptor does not u...

Page 2363: ...oaded This descriptor enables 2D addressing linked list transfer for example a multimedia application where 2D objects are moved in a link Table 11 10 shows a type 2 descriptor with source and destination address updates Table 11 11 shows a type 2 descriptor with one source or destination address update Table 11 10 Type 2 With Source and Destination Address Updates 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 ...

Page 2364: ...tion update Table 11 12 Type 3 With Source and Destination Address Updates 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Ptr Destination_Start_Address 0xC Ptr Source_Start_Address 0x8 Ptr N_type B Dv Sv Element_number 0x4 Ptr Next_descriptor_address_pointer R P sv Table 11 13 Type 3 With Source or Destination Address Update 3 3 2 2 2 2 ...

Page 2365: ...ecution if descriptor types 1 and 2 are used The use of an interrupt event in a link execution can be difficult because the link can progress in parallel with interrupt service routine ISR execution This makes it difficult to synchronize them unless system assumptions are used The most appropriate synchronization model is to get an interrupt only on linked list completion when the last transfer bl...

Page 2366: ...er occurs during the descriptor load phase the channel aborts 11 4 19 4 7 Status Bit Behavior This section describes the behavior of the DMA4_CSRi 6 SYNC DMA4_CCRi 9 RD_ACTIVE and DMA4_CCRi 10 WR_ACTIVE status bits For a hardware synchronized channel in linked list mode the DMA4_CSRi 6 SYNC bit becomes active DMA4_CSRi 6 SYNC 1 when the first data load transaction is scheduled and remains active u...

Page 2367: ...CHx DataN 1 CHz CHz Data1 CHz DES1 CHz DESM CHz DataM 1 It is also possible to link CHx to CHz during the CHx transfer and before the end of super block The user must set the DMA4_CLNK_CTRLi 15 ENABLE_LNK bit to 1 and the DMA4_CLNK_CTRLi 4 0 NEXTLCH_ID bit to z through descriptor p CHx DESp using a type 1 descriptor The sequence is CHx CHx Data1 CHx DES1 CHx DESp CHx Data p 1 CHz Data1 CHz DES1 Th...

Page 2368: ...CSFi DMA4_CDEi and DMA4_CDFi Source and destination element and frame indexes depending on addressing mode 2 Start the transfer through the enable bit in the channel DMA4_CCRi register and DMA register bit DMA4_CCRi 7 The example below perform a DMA transfer on channel 10 of a 240 160 picture from RAM to RAM 0x80C00000 to 0x80F00000 UWORD32 RegVal 0 DMA4_t DMA4 DMA4 DMA4_t malloc sizeof DMA4_t Ini...

Page 2369: ...when the source triggers on the DMA request and DMA4_CCRi 24 SEL_SRC_DST_SYNC to 0 when the Destination triggers on the DMA request Note User must take care when setting the DMA4_CCRi 23 PREFETCH bit it is in conjunction with DMA4_CCRi 24 SEL_SRC_DST_SYNC bit To configure an LCh to transfer one element per DMA request 1 Set the number of DMA request associated to the current LCH in the DMA4_CCRi 2...

Page 2370: ...ld 2 Set the data type also referenced as element size ES in the DMA4_CSDPi 1 0 DATA_TYPE bit field 3 Set the number of elements per packet to transfer If the packet requestor is in the source set DMA4_CCR 24 SEL_SRC_DST_SYNC to 1 and set the packet element number in the DMA4_CSFIi register and set the addressing mode of source to constant addressing in DMA4_CCRi 13 12 SRC_AMODE bit field else if ...

Page 2371: ...on for priority channel 4 and channel 5 Reserve one thread Read ThreadID 0 on the read port Set DMA4_GCR 13 12 0x1 Reserve one thread Write ThreadID 0 on the write port Set DMA4_GCR 13 12 0x1 2 Specify channel priority Channel 4 is a write high priority channel Set DMA4_CCRi 26 1 Channel 5 is a read high priority channel Set DMA4_CCRi 6 1 11 5 6 Chained Transfer A chained DMA transfer can be progr...

Page 2372: ...ource frame index 1 DMA4_CDEi destination EI 637 DMA4_CDFi destination frame index 152967 2 Start the transfer via the enable bit in the channel DMA4_CCRi register Below are the parameters to perform this rotation from 0x80C00000 RAM address to 0x80F00000 with the same code as in Section 11 5 2 Init parameters DMA4 DataType 0x2 DMA4_CSDPi 1 0 DMA4 ReadPortAccessType 0x3 DMA4_CSDPi 8 7 DMA4 WritePo...

Page 2373: ... field to 0 3 Set the value of key the color in the DMA4_COLORi 15 0 solid_color bit field To perform this graphic operation the following lines can be added to the example of Section 11 5 2 DMA4_CCR_CH10 0x1 17 DMA4_CCR_CH10 0x1 16 DMA4_COLOR_CH10 0x00000003 2373 SWPU177N December 2009 Revised November 2010 SDMA Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2374: ...4 0x4805 6064 DMA4_CAPS_2 R 32 0x0000 006C 0x4805 606C DMA4_CAPS_3 R 32 0x0000 0070 0x4805 6070 DMA4_CAPS_4 R 32 0x0000 0074 0x4805 6074 DMA4_GCR RW 32 0x0000 0078 0x4805 6078 DMA4_CCRi RW 32 0x0000 0080 i 0x60 0x4805 6080 i 0x60 DMA4_CLNK_CTRLi RW 32 0x0000 0084 i 0x60 0x4805 6084 i 0x60 DMA4_CICRi RW 32 0x0000 0088 i 0x60 0x4805 6088 i 0x60 DMA4_CSRi RW 32 0x0000 008C i 0x60 0x4805 608C i 0x60 D...

Page 2375: ...2 1 0 RESERVED REV Bits Field Name Description Type Reset 31 8 RESERVED Reserved Write 0s for future compatibility Read returns RW 0x000000 0 7 0 REV 7 4 DMA4 major revision code R TI internal data 3 0 DMA4 minor revision code Table 11 17 Register Call Summary for Register DMA4_REVISION SDMA Register Manual SDMA Register Summary 0 Table 11 18 DMA4_IRQSTATUS_Lj Address Offset 0x0000 0008 j 0x4 Inde...

Page 2376: ...ask Unmask RW 0x00000000 a channel i interrupt on Lj the user writes 0 1 on the bit field i 0x0 Channel Interrupt Lj is masked 0x1 Channel Interrupt Lj generates an interrupt when it occurs Table 11 21 Register Call Summary for Register DMA4_IRQENABLE_Lj SDMA Integration SDMA Interrupts 0 1 2 3 SDMA Functional Description Interrupt Generation 4 SDMA Basic Programming Model Setup Configuration 5 SD...

Page 2377: ...ement standby wait control RW 0x0 0x0 Force standby MStandby is asserted only when all the DMA channels are disabled 0x1 No Standby MStandby is never asserted 0x2 Smart Standby MStandby is asserted if at least one of the following two conditions is satisfied 1 All the channels are disabled OR 2 There is no non synchronized channel enabled AND if hardware synchronized channel is enabled then no DMA...

Page 2378: ...OCP clock is free running 0x1 Automatic OCP clock gating strategy is applied based on the OCP interface activity Table 11 25 Register Call Summary for Register DMA4_OCP_SYSCONFIG SDMA Integration Power Management 0 1 2 SDMA Register Manual SDMA Register Summary 3 Table 11 26 DMA4_CAPS_0 Address Offset 0x0000 0064 Physical Address 0x4805 6064 Instance SDMA Description DMA Capabilities Register 0 LS...

Page 2379: ...ption DMA Capabilities Register 2 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DST_CONST_ADRS_CPBLTY SRC_CONST_ADRS_CPBLTY DST_SINGLE_INDEX_ADRS_CPBLTY SRC_SINGLE_INDEX_ADRS_CPBLTY DST_DOUBLE_INDEX_ADRS_CPBLTY SRC_DOUBLE_INDEX_ADRS_CPBLTY DST_POST_INCRMNT_ADRS_CPBLTY SRC_POST_INCREMENT_ADRS_CPBLTY SEPARATE_SRC_AND_DST_INDEX_CPBLTY Bits Field...

Page 2380: ... address mode on the source port 0x1 Supports double index address mode on the source port 2 SRC_SINGLE_INDEX_ Source_single_index_address_capability R 0x1 ADRS_CPBLTY 0x0 Does not support single index address mode on the source port 0x1 Supports single index address mode in the source port 1 SRC_POST_INCREMENT_ Source_post_increment_address_capability R 0x1 ADRS_CPBLTY 0x0 Does not supports post ...

Page 2381: ...n transfer on packet boundary 5 CHANNEL_CHAINING_ Channel_Chaining_capability R 0x1 CPBLTY 0x0 Does not support Channel Chaining capability 0x1 Supports Channel Chaining capability 4 CHANNEL_INTERLEAVE_ Channel_interleave_capability R 0x1 CPBLTY 0x0 Does not support Channel interleave capability 0x1 Supports Channel_interleave capability 3 2 RESERVED RW 0x0 1 FRAME_SYNCHR_CPBLTY Frame_synchronizat...

Page 2382: ...served R 1 12 DRAIN_END_INTERRUPT_CPB Drain End detection capability R 1 LTY 11 MISALIGNED_ADRS_ERR_INT Misaligned error detection capability R 1 ERRUPT_CPBLTY 10 SUPERVISOR_ERR_INTERRUP Supervisor error detection capability R 1 T_CPBLTY 9 RESERVED Reserved for non GP devices R 1 8 TRANS_ERR_INTERRUPT_CPB Transaction error detection capability R 1 LTY 7 PKT_INTERRUPT_CPBLTY End of Packet detection...

Page 2383: ... 0 RESERVED Reserved Write 0 s for future compatibility Read returns RW 0 0 Table 11 33 Register Call Summary for Register DMA4_CAPS_4 SDMA Register Manual SDMA Register Summary 0 Table 11 34 DMA4_GCR Address Offset 0x0000 0078 Physical Address 0x4805 6078 Instance SDMA Description FIFO sharing between high and low priority channel The Maximum per channel FIFO depth is bounded by the low and high ...

Page 2384: ...nnels 0x2 Read port ThreadID 0 and ThreadID 1 are reserved for high priority channels Write Port ThreadID 0 is reserved for high priority channels 0x3 Read PortThreadID 0 ThreadID 1 and ThreadID 2 are reserved for high priority channels Write Port ThreadID 0 is reserved for high priority channels 11 8 RESERVED Reserved Write 0s for future compatibility Read returns RW 0x0 0 7 0 MAX_CHANNEL_ Maximu...

Page 2385: ...ross element packet when source is synchronized to element packet frame or blocks 0x1 buffering is disabled across element packet when source is synchronized to element packet frame or blocks 24 SEL_SRC_DST_SYNC Specifies that element packet frame or block transfer RW 0x depending on CCR bs and CCR fs is triggered by the source or the destination on the DMA request 0x0 Transfer is triggered by the...

Page 2386: ...rved Write 0s for future compatibility Read returns RW 0x0 0 10 WR_ACTIVE Indicates if the channel write context is active or not R 0x0 0x0 Channel is not active on the write port 0x1 Channel is active on the write port 9 RD_ACTIVE Indicates if the channel read context is active or not R 0x0 0x0 Channel is not active on the read port 0x1 Channel is currently active on the read port 8 SUSPEND_SENSI...

Page 2387: ...must be set to 0x2 DMA request number 1 Table 11 37 Register Call Summary for Register DMA4_CCRi SDMA Functional Description Logical Channel Transfer Overview 0 1 2 Addressing Modes 3 Software Synchronization 4 5 6 Hardware Synchronization 7 8 9 10 11 12 13 14 15 16 17 18 Thread Budget Allocation 19 20 Reprogramming an Active Channel 21 22 23 24 Interrupt Generation 25 Packet Synchronization 26 27...

Page 2388: ...served Write 0s for future compatibility Read returns RW 0x000 0 4 0 NEXTLCH_ID Defines the NextLCh_ID which is used to build logical RW 0x channel chaining queue Table 11 39 Register Call Summary for Register DMA4_CLNK_CTRLi SDMA Functional Description Chained Logical Channel Transfers 0 1 FIFO Draining Mechanism 2 Descriptors 3 Linked List Control and Monitoring 4 5 6 7 SDMA Basic Programming Mo...

Page 2389: ...upt RW 0x 0x0 Disables the transaction error event interrupt 0x1 Enables the transaction error event interrupt 7 PKT_IE Enables the end of Packet interrupt RW 0x 0x0 Disables the end of Packet transfer interrupt 0x1 Enables the end of Packet transfer interrupt 6 RESERVED Reserved Write 0s for future compatibility Read returns RW 0x0 0 5 BLOCK_IE Enables the end of block interrupt RW 0x 0x0 Disable...

Page 2390: ...UPER_BLOCK SUPERVISOR_ERR MISALIGNED_ADRS_ERR Bits Field Name Description Type Reset 31 15 RESERVED Reserved Write 0s for future compatibility Read returns RW 0x0000 0 14 SUPER_BLOCK End of super block event RW 0x0 Read 0x0 The current Super block transfer has not been finished Write 0x0 Status bit unchanged Read 0x1 The current Super block has been transferred Write 0x1 Status bit is reset 13 RES...

Page 2391: ...te 0x0 Status bit unchanged Read 0x1 Logical channel is servicing a synchronized DMA request Write 0x1 Status bit unchanged 5 BLOCK End of block event RW 0x0 Read 0x0 The current block transfer has not been finished Write 0x0 Status bit unchanged Read 0x1 The current block has been transferred Write 0x1 Status bit is reset 4 LAST Last frame start of last frame RW 0x0 Read 0x0 The start of the last...

Page 2392: ...ysical Address 0x4805 6090 i 0x60 Instance SDMA Description Channel Source Destination Parameters Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED DATA_TYPE DST_ENDIAN SRC_ENDIAN DST_PACKED WRITE_MODE SRC_PACKED DST_BURST_EN SRC_BURST_EN DST_ENDIAN_LOCK SRC_ENDIAN_LOCK Bits Field Name Description Type Reset 31 22 RESERVED Rese...

Page 2393: ...med burst size is also allowed 0x0 Single access 0x1 16 bytes or 4x32 bit 2x64 bit burst access 0x2 32 bytes or 8x32 bit 4x64 bit burst access 0x3 64 bytes or 16x32 bit 8x64 bit burst access 6 SRC_PACKED Source provides packed data RW 0x 0x0 The source target is nonpacked 0x1 The source target is packed 5 2 RESERVED Reserved Write 0s for future compatibility Read returns RW 0x 0 1 0 DATA_TYPE Defi...

Page 2394: ...ockwise Image Rotation 6 SDMA Register Manual SDMA Register Summary 7 Table 11 48 DMA4_CFNi Address Offset 0x0000 0098 i 0x60 Index i 0 to 31 Physical Address 0x4805 6098 i 0x60 Instance SDMA Description Channel Frame Number Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CHANNEL_FRAME_NBR Bits Field Name Description Type Reset 31 16 RESERVED ...

Page 2395: ...wise Image Rotation 6 SDMA Register Manual SDMA Register Summary 7 Table 11 52 DMA4_CDSAi Address Offset 0x0000 00A0 i 0x60 Index i 0 to 31 Physical Address 0x4805 60A0 i 0x60 Instance SDMA Description Channel Destination Start Address Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DST_START_ADRS Bits Field Name Description Type Reset 31 0 DST_START_A...

Page 2396: ...to 31 Physical Address 0x4805 60A8 i 0x60 Instance SDMA Description Channel Source Frame Index Signed or 16 bit Packet size Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR Bits Field Name Description Type Reset 31 0 CH_SRC_FRM_INDEX_OR_ Channel source frame index value if source address is in RW 0x 16BIT_PKT_ELNT_...

Page 2397: ...to 31 Physical Address 0x4805 60B0 i 0x60 Instance SDMA Description Channel Destination Frame Index Signed or 16 bit Packet size Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR Bits Field Name Description Type Reset 31 0 CH_DST_FRM_IDX_OR_ Channel destination frame index value if destination RW 0x 16BIT_PKT_ELNT_NBR...

Page 2398: ... in 8 bit or 16bit data may be corrupted Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DST_ELMNT_ADRS Bits Field Name Description Type Reset 31 0 DST_ELMNT_ADRS Current destination address counter value RW 0x Table 11 65 Register Call Summary for Register DMA4_CDACi SDMA Functional Description Hardware Synchronization 0 SDMA Basic Programming Model H...

Page 2399: ...rupted Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CURRENT_FRAME_NBR Bits Field Name Description Type Reset 31 16 RESERVED Reserved Write 0s for future compatibility Read returns RW 0x0000 0 15 0 CURRENT_FRAME_NBR Channel current transferred frame number in the current RW 0x transfer Table 11 69 Register Call Summary for Register DMA4_CCFN...

Page 2400: ...e SDMA 0x4805 60D0 i 0x60 Description This register controls the various parameters of the link list mechanism Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FAST SRC_VALID DEST_VALID PAUSE_LINK_LIST TRANSFER_MODE NEXT_DESCRIPTOR_TYPE Bits Field Name Description Type Reset 31 11 RESERVED Write 0 s for future compatibility Reads return 0 RW 0x...

Page 2401: ... the next descriptor transfer 0x2 The destination start address is not present in the next descriptor But will reload the one from configuration memory which belongs to the previous descriptor 0x3 Undefined addressing mode Table 11 73 Register Call Summary for Register DMA4_CDPi SDMA Functional Description Link List Transfer Profile 0 Descriptors 1 2 Linked List Control and Monitoring 3 4 5 6 7 8 ...

Page 2402: ...is read write to allow user initialization Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CURRENT_DESCRIPTOR_NBR Bits Field Name Description Type Reset 31 16 RESERVED Write 0 s for future compatibility Reads return 0 RW 0x0000 15 0 CURRENT_DESCRIPTOR_NBR Current active descriptor number in the link list RW 0x Table 11 77 Register Call Summary...

Page 2403: ...INTC module Topic Page 12 1 Interrupt Controller Overview 2404 12 2 Interrupt Controller Environment 2406 12 3 MPU Subsystem INTCPS Integration 2407 12 4 Interrupt Controller Functional Description 2410 12 5 Interrupt Controller Basic Programming Model 2415 12 6 Interrupt Controller Register Manual 2422 2403 SWPU177N December 2009 Revised November 2010 Interrupt Controller Copyright 2009 2010 Texa...

Page 2404: ...s not described in detail in this chapter For detailed information about this INTC see Chapter 5 IVA2 2 Subsystem Modem INTC This module is an L4 mapped INTC that allows the regrouping of all the interrupts sent to the modem subsystem in stacked mode It is seen as a level 2 INTC by the MPU and IVA2 2 subsystems This modem INTC is integrated in the stand alone device but it is used only with the st...

Page 2405: ...K IVA2_IRQ 47 0 MD_IRQ_ 31 0 MODEM_INTC_FCLK MODEM_INTC_MPU_IRQ MODEM_INTC_DSP_FIQ Peripheral modules sad2d_frint M_IRQ_88 M_IRQ_ 95 0 C64x DSP IVA2_IRQ 40 sad2d_spint sad2d_armnirq sad2d_umanfiq MD_IRQ_24 MD_IRQ_25 d2d_fw_debug 1 d2d_fw_debug 0 128 intc 001 M_IRQ_7 and MD_IRQ_0 MAD2D Public Version www ti com Interrupt Controller Overview Figure 12 1 Interrupt Controllers Highlight 2405 SWPU177N ...

Page 2406: ... MPU INTC and the modem INTC in the CORE domain have no effect The CORE power domain does not wake up and the interrupt is not signaled to the MPU modem GPIO interrupt inputs External devices can also use GPIO modules to generate interrupts to the MPU and the modem There are six dedicated interrupt lines to the MPU INTC and four dedicated interrupt inputs to the modem INTC One interrupt line is as...

Page 2407: ... by the MPU 12 3 1 Clocking Reset and Power Management Scheme 12 3 1 1 MPU Subsystem INTC Clocks The MPU subsystem INTCPS runs at half the rate of the MPU functional clock see Chapter 4 MPU Subsystem The interface clock used for register access runs at the rate of the interconnect bus clock equal to the rate of the MPU interface clock see Chapter 3 Power Reset and Clock Management The synchronizer...

Page 2408: ...5 0 See Table 12 4 Inputs to INTCPS module source from various modules Interrupt request 2 MPU_INTC_FIQ MPU_INTC_FIQ Outgoing to MPU Fast Interrupt outputs MPU_INTC_IRQ MPU_INTC_IRQ Outgoing to MPU Normal Interrupt NOTE Interrupt request signals are active at low level CAUTION A single interrupt source can be physically mapped to multiple INTCs MPU subsystem IVA2 2 subsystem and modem With multipl...

Page 2409: ...U_IRQ GPIO module 2 4 5 M_IRQ_31 GPIO3_MPU_IRQ GPIO module 3 4 5 M_IRQ_32 GPIO4_MPU_IRQ GPIO module 4 4 5 M_IRQ_33 GPIO5_MPU_IRQ GPIO module 5 4 M_IRQ_34 GPIO6_MPU_IRQ GPIO module 6 4 M_IRQ_35 Reserved Reserved M_IRQ_36 WDT3_IRQ Watchdog timer module 3 overflow M_IRQ_37 GPT1_IRQ General purpose timer module 1 M_IRQ_38 GPT2_IRQ General purpose timer module 2 M_IRQ_39 GPT3_IRQ General purpose timer ...

Page 2410: ...RQ_76 OHCI_IRQ OHCI controller HSUSB MP Host Interrupt M_IRQ_77 EHCI_IRQ EHCI controller HSUSB MP Host Interrupt M_IRQ_78 TLL_IRQ HSUSB MP TLL Interrupt M_IRQ_79 Reserved Reserved M_IRQ_80 UART4_IRQ UART module 4 M_IRQ_81 MCBSP5_IRQ_TX McBSP module 5 transmit 6 M_IRQ_82 MCBSP5_IRQ_RX McBSP module 5 receive 6 M_IRQ_83 MMC1_IRQ MMC SD module 1 M_IRQ_84 Reserved Reserved M_IRQ_85 Reserved Reserved M_...

Page 2411: ...ority threshold register Atomic bit set and clear capability for interrupt mask and software interrupt registers Power management and wake up support Auto idle power saving support The INTCPS processes incoming interrupts by masking and priority sorting then it generates the interrupt requests to the MPU Figure 12 4 shows the top level view of the interrupt processing 2411 SWPU177N December 2009 R...

Page 2412: ...or Interrupt priority and FIQ IRQ steering Active interrupt Nb spurious flag and priority Priority comparator If INT priority threshold Priority threshold THRESHOLD intc 004 NEWFIQAGR NEWIRQAGR FIQ_PRIORITY New agreement bits IRQ_PRIORITY Public Version Interrupt Controller Functional Description www ti com Figure 12 4 Top Level Block Diagram 2412 Interrupt Controller SWPU177N December 2009 Revise...

Page 2413: ...THRESHOLD field This priority threshold allows preemption by higher priority interrupts all interrupts of lower or equal priority than the threshold are masked However priority 0 can never be masked by this threshold a priority threshold of 0 is treated the same way as priority 1 PRIORITY and PRIORITYTHRESHOLD fields values can be set between 0x0 and 0x3F 0x0 is the highest priority and 0x3F is th...

Page 2414: ...synchronized before they are masked The synchronizer input clock has an auto idle power saving mode enabled if the MPU_INTC INTCPS_IDLE 1 TURBO bit is set to 1 If the auto idle mode is enabled the standby power is reduced but the IRQ or FIQ interrupt latency increases from four to six functional clock cycles This feature can be enabled dynamically according to the requirements of the device After ...

Page 2415: ...INTCPS_ILRm 0 FIQNIRQ bit is set to 0 the MPU_INTC_IRQ output signal is generated If the FIQNIRQ bit is set to 1 the MPU_INTC_FIQ output signal is generated 3 The INTC performs the priority sorting and updates the MPU_INTC INTCPS_SIR_IRQ 6 0 ACTIVEIRQ MPU_INTC INTCPS_SIR_FIQ 6 0 ACTIVEFIQ field with the current interrupt number 4 During priority sorting if the IRQ FIQ is enabled at the host proces...

Page 2416: ...NEWFIQAGR bit to enable the processing of subsequent pending IRQs FIQs and to restore ARM context in the following code Because the writes are posted on an Interconnect bus to be sure that the preceding writes are done before enabling IRQs FIQs a Data Synchronization Barrier is used This operation ensure that the IRQ FIQ line is de asserted before IRQ FIQ enabling After that the INTC processes any...

Page 2417: ... number 1 Execution of the instruction number N Hardware Step 1 Step 2 Main program Execution of the instruction number N 1 Return peripheral module side If the IRQ_n is not masked and configured as an IRQ FIQ the MPU_INTC_IRQ MPU_INT_FIQ line is asserted ISR in IRQ FIQ mode Step 5 Revelant subroutine handler in IRQ FIQ mode Step 6 Disable IRQs and FIQs at ARM side ISR in IRQ FIQ mode Step 7 Publi...

Page 2418: ...orking registers MRS R11 SPSR Save the SPSR into R11 Step 2 Save the INTCPS_THRESHOLD register into R12 LDR R0 INTCPS_THRESHOLD_ADDR LDR R12 R0 Step 3 Get the priority of the highest priority active IRQ LDR R1 INTCPS_IRQ_PRIORITY_ADDR INTCPS_FIQ_PRIORITY_ADDR LDR R1 R1 Get the INTCPS_IRQ_PRIORITY INTCPS_FIQ_PRIORITY register AND R1 R1 ACTIVEPRIO_MASK Apply the mask to get the priority of the IRQ S...

Page 2419: ...mpatible with ARM architecture V6 and V7 This code is developed for the Texas Instruments Code Composer Studio tool set It is a draft version only tested on an emulated environment IRQ_ISR_end Step 1 Read modify write the CPSR to disable IRQs FIQs at ARM side MRS R0 CPSR Read the CPSR ORR R0 R0 0x80 0x40 Set the I F bit MSR CPSR R0 Write it back to disable IRQs Step 2 Restore the INTCPS_THRESHOLD ...

Page 2420: ...store ARM critical context Branch ARM host processor Restore the whole CPSR Restore the PC Branch Branch Return Main Program Execution of the instruction number 1 Execution of the instruction number N Step 1 Step 2 Main Program Execution of the instruction number N 1 Return Software Hardware intc 006 If the IRQ_n is not masked and configured as an IRQ FIQ the MPU_INTC_IRQ MPU_INT_FIQ line is asser...

Page 2421: ...an be masked before its turn in the sort The resulting values of the following registers become invalid MPU_INTC INTCPS_SIR_IRQ MPU_INTC INTCPS_SIR_FIQ MPU_INTC INTCPS_IRQ_PRIORITY MPU_INTC INTCPS_FIQ_PRIORITY This condition is detected for both IRQ and FIQ and the invalid status is flagged across the SPURIOUSIRQFLAG see Note 1 and SPURIOUSFIQFLAG see Note 2 bit fields in the SIR and PRIORITY regi...

Page 2422: ...0014 0x4820 0014 INTCPS_SIR_IRQ R 32 0x0000 0040 0x4820 0040 INTCPS_SIR_FIQ R 32 0x0000 0044 0x4820 0044 INTCPS_CONTROL RW 32 0x0000 0048 0x4820 0048 INTCPS_PROTECTION RW 32 0x0000 004C 0x4820 004C INTCPS_IDLE RW 32 0x0000 0050 0x4820 0050 INTCPS_IRQ_PRIORITY RW 32 0x0000 0060 0x4820 0060 INTCPS_FIQ_PRIORITY RW 32 0x0000 0064 0x4820 0064 INTCPS_THRESHOLD RW 32 0x0000 0068 0x4820 0068 INTCPS_ITRn 1...

Page 2423: ...I internal data Table 12 9 Register Call Summary for Register INTCPS_REVISION Interrupt Controller Register Manual Register Summary 0 Table 12 10 INTCPS_SYSCONFIG Address Offset 0x010 Physical Address 0x4820 0010 Instance MPU INTC 0x480C 8010 Modem INTC Description This register controls various parameters of the module interface Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ...

Page 2424: ...8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RESETDONE Bits Field Name Description Type Reset 31 1 Reserved Read returns reset value R 0x00000000 0 RESETDONE Internal reset monitoring R Read Internal module reset is ongoing 0x0 Read Reset complete 0x1 Table 12 13 Register Call Summary for Register INTCPS_SYSSTATUS Interrupt Controller Register Manual Register Summary 0 Table 12 14 INTCPS...

Page 2425: ...ACTIVEFIQ Bits Field Name Description Type Reset 31 7 SPURIOUSFIQFLAG Spurious FIQ flag R 0x1FFFFFF 6 0 ACTIVEFIQ Active FIQ number R 0x00 Table 12 17 Register Call Summary for Register INTCPS_SIR_FIQ Interrupt Controller Functional Description Priority Sorting 0 Interrupt Latency 1 2 Interrupt Basic Programming Model MPU INTC Processing Sequence 3 MPU INTC Preemptive Processing Sequence 4 MPU INT...

Page 2426: ...fset 0x04C Physical Address 0x4820 004C Instance MPU INTC Description This register controls protection of the other registers It can be accessed only in supervisor mode regardless of the current value of the protection bit Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PROTECTION Bits Field Name Description Type Reset 31 1 Reserved Write 0s ...

Page 2427: ...lock idle mode RW 0 0x0 Functional clock gating strategy is applied default 0x1 Functional clock is free running Table 12 23 Register Call Summary for Register INTCPS_IDLE Interrupt Controller Functional Description Module Power Saving 0 1 2 Interrupt Latency 3 4 Interrupt Basic Programming Model Initialization Sequence 5 Interrupt Controller Register Manual Register Summary 6 Table 12 24 INTCPS_I...

Page 2428: ...TC Preemptive Processing Sequence 0 MPU INTC Spurious Interrupt Handling 1 2 Interrupt Controller Register Manual Register Summary 3 Table 12 28 INTCPS_THRESHOLD Address Offset 0x068 Physical Address 0x4820 0068 Instance MPU INTC Description This register sets the priority threshold Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PRIORITYTHRES...

Page 2429: ... 1 2 Table 12 32 INTCPS_MIRn Address Offset 0x084 0x20 n Index n 0 to 2 Physical Address 0x4820 0084 0x20 n Instance MPU INTC Description This register contains the interrupt mask Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIR Bits Field Name Description Type Reset 31 0 MIR Interrupt mask RW 0xFFFFFFFF 0x1 The interrupt is masked 0x0 The interrupt...

Page 2430: ...ce 0 Interrupt Controller Register Manual Register Summary 1 Table 12 36 INTCPS_MIR_SETn Address Offset 0x08C 0x20 n Index n 0 to 2 Physical Address 0x4820 008C 0x20 n Instance MPU INTC Description This register is used to set the interrupt mask bits Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIRSET Bits Field Name Description Type Reset 31 0 MIRSE...

Page 2431: ...Interrupt Controller Functional Description Input Selection 0 Interrupt Controller Register Manual Register Summary 1 Table 12 40 INTCPS_ISR_CLEARn Address Offset 0x094 0x20 n Index n 0 to 2 Physical Address 0x4820 0094 0x20 n Instance MPU INTC Description This register is used to clear the software interrupt bits Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 2432: ...09C 0x20 n Instance MPU INTC Description This register contains the FIQ status after masking Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PENDINGFIQ Bits Field Name Description Type Reset 31 0 PENDINGFIQ FIQ status after masking R 0x00000000 Table 12 45 Register Call Summary for Register INTCPS_PENDING_FIQn Interrupt Controller Functional Description...

Page 2433: ...ful modem INTC registers Table 12 48 INTC_SYSCONFIG Address Offset 0x010 Physical Address 0x480C 7010 Instance Modem INTC Description This register controls various parameters of the module interface Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved AUTOIDLE SOFTRESET Bits Field Name Description Type Reset 31 2 Reserved Write 0s for future compa...

Page 2434: ...rved Write 0s for future compatibility Read returns reset R 0x00000000 value 1 TURBO Input synchronizer clock auto gating RW 0 0x0 Input synchronizer clock is free running default 0x1 Input synchronizer clock is auto gated based on interrupt input activity 0 FUNCIDLE Functional clock idle mode RW 0 0x0 Functional clock gating strategy is applied default 0x1 Functional clock is free running Table 1...

Page 2435: ... control module SCM Topic Page 13 1 SCM Overview 2436 13 2 SCM Environment 2436 13 3 SCM Integration 2438 13 4 SCM Functional Description 2442 13 5 SCM Programming Model 2530 13 6 SCM Register Manual 2545 2435 SWPU177N December 2009 Revised November 2010 System Control Module Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2436: ...bility I O multiplexing Save and restore pad configuration Figure 13 1 provides an overview of the SCM Figure 13 1 SCM Overview The SCM primarily implements a bank of registers accessible by the software Some are read only registers that carry status information and others are fully accessible read write The read write registers are divided into the following classes Pad functional multiplexing an...

Page 2437: ...l sensitive active low or edge sensitive falling edge through the correct setting of the SENSDMAREQN bit where N is between 0 and 3 The sys_boot 5 0 pins are read accessible in a status register SYSBOOT field CONTROL CONTROL_STATUS 5 0 following a POR The SCM does not use sys_boot 6 for more information see Chapter 3 Power Reset and Clock Management With the correct pad configuration the SCM maps ...

Page 2438: ...CM input and output configured to observe device module debug signals Table 13 1 SCM I O Description Signal Name I O 1 Description Reset Value hw_dbg 17 0 O Debug signals 0 to 17 N A sys_boot 5 0 I Boot configuration mode bits 0 to 5 per boot mode selection 1 I Input O Output 13 3 SCM Integration This section describes the integration of the SCM within the device Figure 13 4 shows the SCM integrat...

Page 2439: ...VICE_TYPE BOOT_WAIT_ENABLE Public Version www ti com SCM Integration Figure 13 4 SCM Integration The SCM is split into two blocks the core control module in the CORE power domain and the wake up control module in the WKUP power domain The wake up control module contains the save and restore memory some observability multiplexing and pad configurations For more information about the wake up control...

Page 2440: ...F 2 WKUPCTRLCLOCKDIV bit Only this wake up interface clock WKUP_ICLK is propagated to the wake up control module 13 3 1 2 Resets The SCM responds only to the internal POR and to the device type The CONTROL CONTROL_SYSCONFIG 1 SOFTRESET bit has no effect the SCM is not affected by a warm reset The internal POR is not a direct image of the POR input pin SYS_NRESPWRON The PRCM module generates an int...

Page 2441: ... The PRCM CM_IDLEST1_CORE 6 ST_OMAPCTRL bit 0b0 active 0b1 idle can check the SCM idle state The SCM idle mode is a function of the PRCM CM_ICLKEN1_CORE 6 EN_OMAPCTRL bit configuration and can be controlled automatically with hardware depending on the PRCM CM_AUTOIDLE1_CORE 6 AUTO_OMAPCTRL bit configuration 13 3 1 4 2 Module Power Saving An internal interface clock gating feature provides SCM loca...

Page 2442: ...ation 13 3 2 Hardware Requests The SCM does not generate interrupt or wake up requests 13 4 SCM Functional Description 13 4 1 Block Diagram The SCM controls various device modules settings through register configuration and internal signals It also controls the pad configuration and multiplexing and the routing of internal signals such as PRCM signals or DMA requests to observable pins for debug F...

Page 2443: ...registers Observability muxing Module controls Pad configuration Msuspend muxing L4 Core interconnect Wakeup interface scm 006 Public Version www ti com SCM Functional Description Figure 13 6 SCM Block Diagram The following sections describe the functionality of the SCM registers 2443 SWPU177N December 2009 Revised November 2010 System Control Module Copyright 2009 2010 Texas Instruments Incorpora...

Page 2444: ...power domain It contains a 1K byte memory in which to save the pad configuration registers in the core control module before going to off mode Pad configuration registers driving the I O pad control in the WKUP power domain are also instantiated in the wake up control module The wake up control module is configured through the L4 Core interface in the core control module and is accessed from the c...

Page 2445: ...tional mode Off mode values 5 bits override the pin state when the OFFENABLE bit CONTROL CONTROL_PADCONF_X is set and off mode is active This feature allows having separate configurations for the pins when in off mode OFFENABLE Off mode pin state override control Set to 1 to enable the feature and to 0 to disable it OFFOUTENABLE Off mode output enable value Set to 0 to enable the feature and to 1 ...

Page 2446: ...0 Mode 4 0b101 Mode 5 0b110 Mode 6 0b111 Safe mode Mode 7 The MUXMODE field CONTROL CONTROL_PADCONF_X defines the multiplexing mode applied to the pad Functional modes are referred to by their decimal from 0 to 7 or binary from 0b000 to 0b111 representation For most pads the reset value for the MUXMODE field CONTROL CONTROL_PADCONF_X is 0b111 defining a mode referred to as the safe mode The except...

Page 2447: ... 0b0 0b1 Pulldown selected and activated if pin is NOT configured as OUTPUT 0b1 0b0 Pullup selected but not activated 0b1 0b1 Pullup selected and activated if pin is NOT configured as OUTPUT For more information on the pull available on each pin see Table 13 4 through Table 13 6 13 4 4 3 Pad Multiplexing Register Fields Table 13 4 through Table 13 6 provide for each pad configuration register fiel...

Page 2448: ...CONTROL_PADCONF_SDRC_D14 15 0 0x4800 204C sdrc_d14 CONTROL_PADCONF_SDRC_D14 31 16 0x4800 204C sdrc_d15 CONTROL_PADCONF_SDRC_D16 15 0 0x4800 2050 sdrc_d16 CONTROL_PADCONF_SDRC_D16 31 16 0x4800 2050 sdrc_d17 CONTROL_PADCONF_SDRC_D18 15 0 0x4800 2054 sdrc_d18 CONTROL_PADCONF_SDRC_D18 31 16 0x4800 2054 sdrc_d19 CONTROL_PADCONF_SDRC_D20 15 0 0x4800 2058 sdrc_d20 CONTROL_PADCONF_SDRC_D20 31 16 0x4800 20...

Page 2449: ...GPMC_A10 15 0 0x4800 208C gpmc_a10 sys_ndmar gpio_43 safe_mode eq3 CONTROL_PADCONF_GPMC_A10 31 16 0x4800 208C gpmc_d0 CONTROL_PADCONF_GPMC_D1 15 0 0x4800 2090 gpmc_d1 CONTROL_PADCONF_GPMC_D1 31 16 0x4800 2090 gpmc_d2 CONTROL_PADCONF_GPMC_D3 15 0 0x4800 2094 gpmc_d3 CONTROL_PADCONF_GPMC_D3 31 16 0x4800 2094 gpmc_d4 CONTROL_PADCONF_GPMC_D5 15 0 0x4800 2098 gpmc_d5 CONTROL_PADCONF_GPMC_D5 31 16 0x480...

Page 2450: ...PADCONF_GPMC_NWE 15 0 0x4800 20C4 gpmc_nwe CONTROL_PADCONF_GPMC_NWE 31 16 0x4800 20C4 gpmc_nbe gpio_60 safe_mode 0_cle CONTROL_PADCONF_GPMC_NBE1 15 0 0x4800 20C8 gpmc_nbe gpio_61 safe_mode 1 CONTROL_PADCONF_GPMC_NBE1 31 16 0x4800 20C8 gpmc_nwp gpio_62 safe_mode CONTROL_PADCONF_GPMC_WAIT0 15 0 0x4800 20CC gpmc_wait 0 CONTROL_PADCONF_GPMC_WAIT0 31 16 0x4800 20CC gpmc_wait gpio_63 safe_mode 1 CONTROL...

Page 2451: ...safe_mode CONTROL_PADCONF_DSS_DATA12 15 0 0x4800 20F4 dss_data12 gpio_82 safe_mode CONTROL_PADCONF_DSS_DATA12 31 16 0x4800 20F4 dss_data13 gpio_83 safe_mode CONTROL_PADCONF_DSS_DATA14 15 0 0x4800 20F8 dss_data14 gpio_84 safe_mode CONTROL_PADCONF_DSS_DATA14 31 16 0x4800 20F8 dss_data15 gpio_85 safe_mode CONTROL_PADCONF_DSS_DATA16 15 0 0x4800 20FC dss_data16 gpio_86 safe_mode CONTROL_PADCONF_DSS_DAT...

Page 2452: ...2128 cam_d9 gpio_108 safe_mode CONTROL_PADCONF_CAM_D9 31 16 0x4800 2128 cam_d10 Reserved gpio_109 hw_dbg8 safe_mode CONTROL_PADCONF_CAM_D11 15 0 0x4800 212C cam_d11 gpio_110 hw_dbg9 safe_mode CONTROL_PADCONF_CAM_D11 31 16 0x4800 212C cam_xclkb gpio_111 safe_mode CONTROL_PADCONF_CAM_WEN 15 0 0x4800 2130 cam_wen cam_shutte gpio_167 hw_dbg10 safe_mode r CONTROL_PADCONF_CAM_WEN 31 16 0x4800 2130 cam_s...

Page 2453: ... 0x4800 2160 sdmmc2_d mcspi3_cs gpio_135 safe_mode at3 0 CONTROL_PADCONF_MMC2_DAT4 15 0 0x4800 2164 sdmmc2_d sdmmc2_di sdmmc3_dat gpio_136 safe_mode at4 r_dat0 0 CONTROL_PADCONF_MMC2_DAT4 31 16 0x4800 2164 sdmmc2_d sdmmc2_di cam_global sdmmc3_dat gpio_137 hsusb3_tll_ mm3_rxdp safe_mode at5 r_dat1 _reset 1 stp CONTROL_PADCONF_MMC2_DAT6 15 0 0x4800 2168 sdmmc2_d sdmmc2_di cam_shutte sdmmc3_dat gpio_...

Page 2454: ...eserved gpio_153 hsusb3_tll_ mm3_rxrcv safe_mode data0 CONTROL_PADCONF_MCBSP4_DX 15 0 0x4800 2188 mcbsp4_dx Reserved gpio_154 hsusb3_tll_ mm3_txdat safe_mode data2 CONTROL_PADCONF_MCBSP4_DX 31 16 0x4800 2188 mcbsp4_fs Reserved gpio_155 hsusb3_tll_ mm3_txen safe_mode x data3 _n CONTROL_PADCONF_MCBSP1_CLKR 15 0 0x4800 218C mcbsp1_cl mcspi4_clk Reserved gpio_156 safe_mode kr CONTROL_PADCONF_MCBSP1_CL...

Page 2455: ..._cts_r gpio_169 uart2_cts safe_mode a3 ctx CONTROL_PADCONF_HSUSB0_DATA3 31 16 0x4800 21B0 hsusb0_dat gpio_188 safe_mode a4 CONTROL_PADCONF_HSUSB0_DATA5 15 0 0x4800 21B4 hsusb0_dat gpio_189 safe_mode a5 CONTROL_PADCONF_HSUSB0_DATA5 31 16 0x4800 21B4 hsusb0_dat gpio_190 safe_mode a6 CONTROL_PADCONF_HSUSB0_DATA7 15 0 0x4800 21B8 hsusb0_dat gpio_191 safe_mode a7 CONTROL_PADCONF_HSUSB0_DATA7 31 16 0x48...

Page 2456: ...181 safe_mode 0 m_evt data6 6 CONTROL_PADCONF_MCSPI2_CS0 31 16 0x4800 21DC mcspi2_cs gpt_8_pwm hsusb2_tll_ hsusb2_data gpio_182 mm2_txen safe_mode 1 _evt data3 3 _n CONTROL_PADCONF_SYS_NIRQ 15 0 0x4800 21E0 sys_nirq gpio_0 safe_mode CONTROL_PADCONF_SYS_NIRQ 31 16 0x4800 21E0 sys_clkout gpio_186 safe_mode 2 CONTROL_PADCONF_SAD2D_SBUSFLAG 31 16 0x4800 2260 sdrc_cke0 safe_mode_ou t1 1 CONTROL_PADCONF...

Page 2457: ... 0 0x4800 25D4 sdrc_dm3 CONTROL_PADCONF_SDRC_DM3 31 16 0x4800 25D4 CONTROL_PADCONF_ETK_CLK 15 0 0x4800 25D8 etk_clk mcbsp5_cl sdmmc3_cl hsusb1_stp gpio_12 mm1_rxdp hsusb1_tll_ hw_dbg0 kx k stp CONTROL_PADCONF_ETK_CLK 31 16 0x4800 25D8 etk_ctl sdmmc3_c hsusb1_clk gpio_13 hsusb1_tll_ hw_dbg1 md clk CONTROL_PADCONF_ETK_D0 15 0 0x4800 25DC etk_d0 mcspi3_si sdmmc3_d hsusb1_data gpio_14 mm1_rxrcv hsusb1...

Page 2458: ...14 for Non GP dir devices CONTROL_PADCONF_ETK_D12 31 16 0x4800 25F4 etk_d13 hsusb2_nxt gpio_27 mm2_rxdm hsusb2_tll_ hw_dbg15 nxt CONTROL_PADCONF_ETK_D14 15 0 0x4800 25F8 etk_d14 hsusb2_data gpio_28 mm2_rxrcv hsusb2_tll_ hw_dbg16 0 data0 CONTROL_PADCONF_ETK_D14 31 16 0x4800 25F8 etk_d15 hsusb2_data gpio_29 mm2_txse0 hsusb2_tll_ hw_dbg17 1 data1 Table 13 5 Core Control Module D2D Pad Configuration R...

Page 2459: ... sad2d_mcad mad2d_mc 14 ad14 CONTROL_PADCONF_SAD2D_MCAD14 31 16 0x4800 2200 sad2d_mcad mad2d_mc 15 ad15 CONTROL_PADCONF_SAD2D_MCAD16 15 0 0x4800 2204 sad2d_mcad mad2d_mc 16 ad16 CONTROL_PADCONF_SAD2D_MCAD16 31 16 0x4800 2204 sad2d_mcad mad2d_mc 17 ad17 CONTROL_PADCONF_SAD2D_MCAD18 15 0 0x4800 2208 sad2d_mcad mad2d_mc 18 ad18 CONTROL_PADCONF_SAD2D_MCAD18 31 16 0x4800 2208 sad2d_mcad mad2d_mc 19 ad1...

Page 2460: ...33 ad33 CONTROL_PADCONF_SAD2D_MCAD34 15 0 0x4800 2228 sad2d_mcad mad2d_mc 34 ad34 CONTROL_PADCONF_SAD2D_MCAD34 31 16 0x4800 2228 sad2d_mcad mad2d_mc 35 ad35 CONTROL_PADCONF_SAD2D_MCAD36 15 0 0x4800 222C sad2d_mcad mad2d_mc 36 ad36 CONTROL_PADCONF_SAD2D_MCAD36 31 16 0x4800 222C chassis_clk2 6mi CONTROL_PADCONF_SAD2D_NRESPWRON 15 0 0x4800 2230 chassis_nres pwron CONTROL_PADCONF_SAD2D_NRESPWRON 31 1 ...

Page 2461: ...is_rtck CONTROL_PADCONF_SAD2D_MSTDBY 15 0 0x4800 2250 chassis_mst dby CONTROL_PADCONF_SAD2D_MSTDBY 31 16 0x4800 2250 chassis_idler eq CONTROL_PADCONF_SAD2D_IDLEACK 15 0 0x4800 2254 chassis_idlea ck CONTROL_PADCONF_SAD2D_IDLEACK 31 16 0x4800 2254 sad2d_mwrit mad2d_swr e ite CONTROL_PADCONF_SAD2D_SWRITE 15 0 0x4800 2258 sad2d_swrite mad2d_mw rite CONTROL_PADCONF_SAD2D_SWRITE 31 16 0x4800 2258 sad2d_...

Page 2462: ..._boot3 dss_data20 gpio_5 safe_mode CONTROL_PADCONF_SYS_BOOT3 31 1 0x4800 2A10 sys_boot4 sdmmc2_dir_dat2 dss_data21 gpio_6 safe_mode 6 CONTROL_PADCONF_SYS_BOOT5 15 0 0x4800 2A14 sys_boot5 sdmmc2_dir_dat3 dss_data22 gpio_7 safe_mode CONTROL_PADCONF_SYS_BOOT5 31 1 0x4800 2A14 sys_boot6 dss_data23 gpio_8 safe_mode 6 CONTROL_PADCONF_SYS_OFF_MODE 0x4800 2A18 sys_off_mode gpio_9 safe_mode 15 0 CONTROL_PA...

Page 2463: ...tag_tdo CONTROL_PADCONF_JTAG_TDO 31 16 0x4800 2A50 CONTROL_PADCONF_GPIO127 15 0 0x4800 2A54 Reserved gpio_127 safe_mode CONTROL_PADCONF_GPIO127 31 16 0x4800 2A54 Reserved Reserved gpio_126 safe_mode CONTROL_PADCONF_GPIO128 15 0 0x4800 2A58 Reserved gpio_128 safe_mode CONTROL_PADCONF_GPIO128 31 16 0x4800 2A58 Reserved gpio_129 safe_mode NOTE Pad names are signal names available in mode 0 2463 SWPU1...

Page 2464: ...inary settings that must be done before performing OFF ON transitions see Section 13 5 3 Off Mode Preliminary Settings 13 4 4 4 1 Save and Restore Mechanism Before going to off mode there is a context saving of the device The save and restore mechanism saves the pad configuration registers in the CORE power domain in a WKUP power domain memory physical addresses 0x4800 2600 to 0x4800 29FC before g...

Page 2465: ...ke Up Event Detection In off mode wake up event detection can also be enabled on an input pad The pad wake up event is latched in the WAKEUPEVENT bit CONTROL CONTROL_PADCONF_X The off mode I O pads wake up scheme is enabled by setting the EN_I O bit PRCM PM _WKEN_WKUP 8 The wake up scheme status is transmitted by the WKUP_ENABLE signal The wake up event detection capability of each I O pad of the ...

Page 2466: ...e Table 13 7 lists the bit directions of the CONTROL_PADCONF_x registers Table 13 7 Bit Directions for CONTROL_PADCONF_x Registers CONTROL_PADCONF_x Bit Bit Direction 0 1 PULLUDENABLE Not activated Activated PULLTYPESELECT Pulldown Pullup INPUTENABLE Input enable signal inactive Input enable signal active OFFENABLE Off mode values are invalid Off mode values are valid OFFOUTENABLE Output Input OFF...

Page 2467: ...registers of the SCM See Section 13 6 3 Register Descriptions for the description of these registers Figure 13 12 shows the functional block diagram between the PBIAS cells and the extended I O cells Figure 13 12 Functional Block Diagram Table 13 8 describes the CONTROL CONTROL_PBIAS_LITE CONTROL CONTROL_PROG_IO1 and CONTROL CONTROL_WKUP_CTRL bit controls for the PBIAS and the extended drain I O c...

Page 2468: ...V or 1 8 V PRG_SDMMC1_SPEEDCTRL Bit that controls the extended drain MMC1 I O cell speed The control is in the CONTROL CONTROL_PROG_IO1 register The second extended drain I O cell GPIO pads associated does not have speed control PBIASLITEVMODEERROR0 PBIASLITEVMODEERROR1 Status indicating whether the software programmed VMODE level matches the SUPPLY_HI output signal PBIAS0_ERROR PBIAS1_ERROR This ...

Page 2469: ...drain I O cell support 1 8 V and 3 0 V voltages A PBIAS cell is not a part of a peripheral but a part of the device I Os to which this peripheral is internally connected These device I Os are not exclusive to only one peripheral through I O multiplexing they can be connected to other internal signals It is necessary to configure the PBIAS and corresponding I O cell to enable the I Os regardless of...

Page 2470: ...e MMC SD SDIO1 I O cell when the SDMMC1_VDDS voltage is not stable The GPIO_IO_PWRDNZ bit is used to protect the GPIO associated I O cell when the SIM_VDDS voltage is not stable CAUTION Software must keep the PWRDNZ related signals to 0b0 when the SDMMC1_VDDS or SIM_VDDS signal is ramping up down or changing When PBIASLITEPWRDNZ0 PBIASLITEPWRDNZ1 is 0 the PAD is floating the PAD may not reflect th...

Page 2471: ...licon temperature Main features of the BGAPTS module are A constant voltage reference output 0 5 V Four constant current reference outputs of 1mA Analog supply is a nominal 1 8 V Small A D converter with 8 bit digital output OFF mode compatible Thermal shutdown comparator output The band gap and the temperature sensor are software controlled by bits located in the CONTROL CONTROL_TEMP_SENSOR and t...

Page 2472: ...ge reference signal is a 0 5 V output that is used internally by the module and is exported for external modules or for tests The current reference signals consist in four lines that each supply a 1 µA current with a 1 8 V voltage These lines can be used to bias other modules 13 4 6 2 Temperature Sensor The temperature sensor feature is used to convert the temperature of the device into a decimal ...

Page 2473: ...les Figure 13 16 shows the timing sequence for a continuous temperature conversion Figure 13 16 Continuous Conversion Mode CONTCONV 1 13 4 6 2 3 ADC Codes Versus Temperature Table 13 11 gives the temperature corresponding to each value of the CONTROL CONTROL_TEMP_SENSOR 7 0 TEMP bits Table 13 11 ADC Code Versus Temperature ADC Temperature C ADC Temperature C ADC Temperature C ADC Temperature C Cod...

Page 2474: ...3 5 12 59 42 43 5 91 97 98 5 123 125 125 28 12 10 60 43 5 45 92 98 5 100 124 125 125 29 10 8 61 45 47 93 100 102 125 125 125 30 8 6 5 62 47 48 5 94 102 103 5 126 125 125 31 6 5 5 63 48 5 50 95 103 5 105 127 125 125 NOTE ADC code values in the subrange 128 255 are reserved for future use 13 4 7 Functional Register Description 13 4 7 1 Static Device Configuration Registers Table 13 12 describes the ...

Page 2475: ...ing DSP and MPU MSuspend signals ORing the DSP and MPU MSuspend signals creates a situation where the module is suspended when at least one processor is under debug therefore when one processor is halted stepping within the code of the other one does not change the module suspended state Not all modules use the MSUSPEND signal See the TRM chapter for each module to determine whether the module sup...

Page 2476: ... Register Physical Address Register Name Description Access 0x4800 2524 CONTROL_TEMP_SENSOR Temperature sensor control register R W 13 4 7 6 Signal Integrity Parameter Control Registers With Pad Group Assignment 13 4 7 6 1 Signal Integrity Parameter Controls Overview Most of the I O cells associated to the device pads are configurable controllable to deliver their carried signals to the targeted s...

Page 2477: ...Rate vs TL Length and Load Settings Table 13 21 and Table 13 22 provide the recommended SC 1 0 slew rate control vs LB 1 0 combined capacitance load and TL length control programming pattern applicable to low speed I O cells The SR settings determine three target maximal frequencies of I O operation Because the TL and SC parameter values are mutually constrained in the context of a certain I O sig...

Page 2478: ...ttings in Different Modes Non I2 C Mode FS I2 C Bus Mode HS I2 C p2p Mode nmode 1 nmode 0 nmode 0 hsmode 0 hsmode 0 hsmode 1 pullupresx 1 pullupresx 1 pullupresx 0 lb 1 0 00 lb 1 0 00 lb 1 0 00 400 kHz 3 4 MHz cap load 5 12pF external PU The I2Cx buffer contains internal pullup resistors for fast and high speed modes that meet the I2 C rise time specifications for loads up to 80 pF in high speed m...

Page 2479: ...drc_ncs0 O0 28 SDRC_NCS0 sdrc_ cke0 CONTROL CONTROL_PROG_I sdrc_ncs1 O0 27 SDRC_NCS1 sdrc_cke1 GPMC CONTROL CONTROL_PROG_I gpmc_a1 High speed I O single bit LB O0 26 PRG_GPMC_A1_LB control for more information see Table 13 20 CONTROL CONTROL_PROG_I gpmc_a2 O0 25 PRG_GPMC_A2_LB CONTROL CONTROL_PROG_I gpmc_a3 O0 24 PRG_GPMC_A3_LB CONTROL CONTROL_PROG_I gpmc_a4 O0 23 PRG_GPMC_A4_LB CONTROL CONTROL_PR...

Page 2480: ...NTROL CONTROL_PROG_I gpmc_wait1 O1 31 PRG_GPMC_WAIT1 CONTROL CONTROL_PROG_I gpmc_wait2 O1 30 PRG_GPMC_WAIT2 CONTROL CONTROL_PROG_I gpmc_wait3 O1 29 PRG_GPMC_WAIT3 DISPLAY CONTROL CONTROL_ dss_data0 dss_data5 Low speed I O LB 1 0 SC 1 0 PROG_IO1 27 26 PRG_DISP_D controls SI_SC for more information see CONTROL CONTROL_ Table 13 21 and Table 13 22 PROG_IO1 25 24 PRG_DISP_D SI_LB CONTROL CONTROL_PROG_...

Page 2481: ...1_rx control uart1_cts for more information see uart1_rts Table 13 20 UART2 CONTROL CONTROL_PROG_I uart2_tx High speed I O single bit LB O1 1 PRG_UART2_LB uart2_rx control uart2_cts for more information see uart2_rts Table 13 20 UART3 CONTROL CONTROL_PROG_I uart3_cts_rctx Low speed I O LB 1 0 SC 1 0 O1 13 12 PRG_UART3_SC uart3_rts_sd controls CONTROL CONTROL_PROG_I uart3_rx_irrx for more informati...

Page 2482: ...CLOC controls K_SC for more information see CONTROL CONTROL_PROG_I Table 13 21 and Table 13 22 O2 24 23 PRG_CHASSIS_CLOC K_LB CONTROL CONTROL_PROG_I chassis_nirq Low speed I Os LB 1 0 SC 1 0 O2 22 21 PRG_CHASSIS_INT_S chassi_fiq controls C chassis_armirq for more information see CONTROL CONTROL_PROG_I chassis_ivairq Table 13 21 and Table 13 22 O2 20 19 PRG_CHASSIS_INT_L B CHASSIS D2D CONTROL CONTR...

Page 2483: ...lupresx Controls and Load Range Settings I2C4 CONTROL CONTROL_PROG_I I2c4_scl I2C specific LB 1 0 setting O_WKUP1 4 3 PRG_SR_LB I2c4_sda for more information see Table 13 24 and Table 13 25 CONTROL CONTROL_PROG_I I2C4 internal pullup resistors O_WKUP1 5 PRG_SR_PULLUP enable control for more RESX information see Section 13 4 7 6 6 I2Cx I Os Group Pullupresx Controls and Load Range Settings HDQ CONT...

Page 2484: ... the L3 and L4 firewall embedded error log registers are cleared All bits in these registers reflect device internal events related to the device protection On a specific event signal rising edge the corresponding bit is set On a rising edge the input signal must stay high for at least two interface clocks periods to be recognized Software must clear each bit after reviewing the events When a prot...

Page 2485: ...SDRC configuration register 1 R W At reset the following occur CONTROL CONTROL_SDRC_SHARING 30 0 copies into SDRC SDRC_SHARING 30 0 CONTROL CONTROL_SDRC_MCFG0 30 0 copies into SDRC SDRC_MCFG_0 30 0 CONTROL CONTROL_SDRC_MCFG1 30 0 copies into SDRC SDRC_MCFG_1 30 0 When LOCK bit SDRC SDRC_SHARING 30 is set a copy of SDRC SDRC_SHARING 30 0 is made into CONTROL CONTROL_SDRC_SHARING 30 0 When LOCK bit ...

Page 2486: ...egisters and selects the set of internal signals from the WKUP power domain The pads used for the hardware debug must be properly configured by selecting the hardware debug function hw_dbgn of the pad To configure the pads select mode 5 0b101 in the MUXMODE bit field of the CONTROL CONTROL_PADCONF_CAM_x register only for hw_dbg0 to hw_dbg11 or select mode 7 0b111 in the MUXMODE bit field of the CO...

Page 2487: ...re used to select the signal set to be observed 0x00 selection sets the output to CORE_OBSMUXn signal For more information see the description of each register in Section 13 4 10 2 Observability Tables 3 To observe the CORE_OBSMUXn signals from the first layer of the multiplexer set the WKUPOBSMUX field CONTROL CONTROL_WKUP_DEBOBS_n to 0x00 and then set the proper values of the OBSMUX field CONTRO...

Page 2488: ...MUX0 1 tie_low 0 CM_96_FCLK 1 96 MHz functional clock of the CM module CM_32K_CLK 2 32 kHz functional clock of the CM module PRCM_DPLL3_enable 3 Signal used to enable DPLL3 DPLL is DPLL is enabled disabled PRCM_CAM_domainFreeze 4 Indicates whether the CAM Domain is Domain is not domain is frozen frozen frozen PRCM_NEON_forceWakeup 5 Indicates whether a wakeup of Wakeup is Wakeup is the NEON domain...

Page 2489: ... is domain transition ongoing PRCM_CORED2D_domai 6 Indicates if the CORE_D2D Domain is not Domain is n domain is ready In other words ready ready Nready is domain transition ongoing PRCM_WKUP_domain 7 Indicates whether the WKUP Domain is not Domain is Nready domain is ready In other words ready ready is domain transition ongoing PRCM_STATE_IS_ON_ 8 Indicates to the global power FSM state is FSM st...

Page 2490: ...ower manager FSM that OFF not OFF the MPU domain power state is OFF Reserved 12 9 PRCM_CORE_48M_GFCL 13 96 MHz functional clock of K the CORE domain Reserved 16 14 sdma_PI_DMAREQ 87 17 DMA requests lines mapped to the system DMA module See Chapter 11 DMA for more information about the system DMA request mapping Reserved 127 88 Table 13 33 Internal Signals Multiplexed on OBSMUX3 Out Signal Name Mux...

Page 2491: ...108 Table 13 34 Internal Signals Multiplexed on OBSMUX4 Out Signal Name Muxed Signal Name OBSMUX4 Field Description High State Low State CONTROL CONTROL_ DEBOBS_2 22 16 dec CORE_OBSMUX4 1 tie_low 0 PRCM_L4_ICLK 1 Interface clock of the L4 interconnect PRCM_DPLL1_idle 2 Indicates whether DPLL1 is idle Domain is in Domain is not idle mode in Idle mode PRCM_DPLL4_idle 3 Indicates whether DPLL4 is idl...

Page 2492: ...main transition ongoing PRCM_CAM_forceSl 6 Indicates whether the CAM Sleep mode Sleep mode eep domain is forced to sleep mode is forced is not forced PRCM_EMU_domain 7 Indicates whether the EMU Domain is Domain is Nready domain is ready In other not ready ready words is domain transition ongoing Reserved 12 8 PRCM_CORE_L4_ 13 Interface clock of the L4 GICLK interconnect Reserved 16 14 mpu_PIIRQ 11...

Page 2493: ...e IsIdle Reserved 11 8 PRCM_DSS_GICLK 12 Interface clock of the DSS module Reserved for non GP 13 Reserved for non GP devices devices Reserved 16 14 mpu_PIIRQ 112 17 Interrupt request lines mapped to the interrupt controller See Chapter 12 Interrupt Controller for more information about these interrupt lines Reserved 114 113 PRCM_DPLL1_LOSSRE 115 Reference input loss Signal Signal not F acknowledg...

Page 2494: ...p Wakeup is Wakeup is Wakeup of the USBHOST domain is forced not forced forced Reserved 11 8 PRCM_CAM_GICLK 12 Interface clock of the CAM module Reserved for non GP 13 Reserved for non GP devices devices Reserved 16 14 mpu_PIIRQ 112 17 Interrupt request lines mapped to the interrupt controller See Chapter 12 Interrupt Controller for more information about these interrupt lines Reserved 114 113 PRC...

Page 2495: ...dicates whether a Wakeup is Wakeup is wakeup of the DSS forced not forced domain is forced PRCM_USBHOST_domain 7 Indicates whether the Domain is not Domain is Nready DSS domain is ready In ready ready other words is domain transition ongoing Reserved 11 8 PRCM_CSI2_96M_GFCLK 12 96 MHz functional clock of the CSIb module Reserved 18 13 PRCM_DPLL1_PHASELO 19 Indicates whether DPLL1 Lock Lock CK is i...

Page 2496: ...dicates whether the Sleep mode Sleep mode eSleep USBHOST domain forced to is forced is not forced sleep mode Reserved 11 8 PRCM_PER_48M_GF 12 48 MHz functional clock of CLK the PER domain PRCM_DSS_96M_GF 13 96 MHz functional clock of CLK the DSS domain Reserved 22 14 iva_gl_dmarq_na 42 23 DMA requests lines used by the IVA2 subsystem See Chapter 5 IVA2 Subsystem for more information about these DM...

Page 2497: ...ed sleep mode PRCM_USBHOST_domai 7 Indicates whether the Domain is Domain is not nFreeze USBHOST domain is frozen frozen frozen Reserved 10 8 This information is not 11 This information is not available in public domain available in public domain PRCM_PER_96M_GFCL 12 96 MHz functional clock of K the PER domain PRCM_EMU_MPU_ALW 13 Functional clock of the ON_CLK MPU module in the EMU domain Reserved...

Page 2498: ...ode vitystatus and required if DPLL3 is forced not forced forced in lock mode in order to ensure high speed emulation or trace clocks Reserved 10 8 This information is not 11 This information is not available in public available in public domain domain PRCM_PER_L4_GICLK 12 Interface clock of the L4 interconnect in the PER clock domain PRCM_MPU_I2ASYNC_ 13 Not a direct MPU clock CLKREQFIFO Reserved...

Page 2499: ...nternal Signals Multiplexed on OBSMUX13 Out Signal Name Muxed Signal Name OBSMUX13 Description High State Low State Field CONTROL CONT ROL_DEBOBS_6 6 0 dec CORE_OBSMUX13 1 tie_low 0 PRCM_DPLL2_FCLK 1 Functional clock of DPLL2 PRCM_DPLL2_enablediv 2 Signal used to enable the clock DPLL clock DPLL clock divisor of DPLL2 divisor is divisor is enabled disabled PRCM_DPLL5_enablediv 3 Signal used to ena...

Page 2500: ...nIsIdl 4 Indicates whether MPU domain Domain is in Domain is e is idle idle mode not in idle mode PRCM_CORED2D_domai 5 Indicates if the CORED2D Domain is in Domain is nIsIdle domain is in idle idle mode not in idle mode PRCM_PER_domainNrea 6 Indicates whether the PER Domain is Domain is dy domain is ready In other words not ready ready is domain transition ongoing PRCM_EMU_MStandby 7 EMU asserts t...

Page 2501: ... Idle mode PRCM_PER_forceSleep 6 Indicates whether the PER Sleep mode Sleep mode domain is forced to sleep mode is forced is not forced PRCM_STATE_IS_ON_M 7 Indicates to the global Power FSM state is FSM state is PU Manager FSM that the MPU ON not ON domain power state is ON Reserved 11 8 PRCM_USBHOST_120M 12 96 MHz functional clock of the _GFCLK USBHOST module PRCM_DPLL4_M2_CLK 13 M2 clock genera...

Page 2502: ...ongoing PRCM_WKUP_domainIsI 6 Indicates whether WKUP domain Domain is in Domain is dle is Idle Idle mode not in Idle mode PRCM_STATE_IS_OFF_ 7 Indicates to the global Power FSM state is FSM state is MPU Manager FSM that the MPU OFF not OFF domain power state is OFF Reserved 11 8 PRCM_SGX_GICLK 12 Interface clock of the L4 interconnect in the SGX clock module PRCM_DPLL4_M4_CLK 13 M4 clock generated...

Page 2503: ...n Domain is dle domain is Idle Idle mode not in Idle mode PRCM_COREL3_domain 5 Indicates whether the COREL3 Domain is Domain is Nready domain is ready In other words not ready ready is domain transition ongoing PRCM_WKUP_domainW 6 Indicates whether a wakeup of Command Command akeupAck the WKUP domain is acknowledge not acknowledged d acknowledge d PRCM_STATE_IS_ON_I 7 Indicates to the global Power...

Page 2504: ...ether the device is ON State is ON State is not ON PRCM_MPU_SRAMAONIN 11 SRAM array power control input bit 1 for Array is Array is not 1 MPU power domain powered powered PRCM_IVA2_SRAMAONIN 12 SRAM array power control input bit 3 for Array is Array is not 3 IVA2 power domain powered powered PRCM_CORE_POWER_IS 13 PM command for CORE domain isolation Isolation is Isolation is O ON OFF PRCM_CORE_SRA...

Page 2505: ...ltage supply of the Low power Low power device is in a low power mode OFF activated not RETENTION or SLEEP activated PRCM_MPU_SRAMAGOO 11 MPU array Powergood indication from Power is Power is DOUT 0 SRAM to PSCON bit 0 stable not stable PRCM_IVA2_SRAMAONIN 12 SRAM array power control input bit 4 for Array is Array is not 4 IVA2 power domain powered powered PRCM_CORE_POWER_G 13 Indicates whether th...

Page 2506: ...trol Module for more information about the save and restore mechanism Reserved 10 PRCM_MPU_SRAMAGOO 11 MPU array Powergood indication from Power is Power is DOUT 1 SRAM to PSCON bit 1 stable not stable PRCM_IVA2_SRAMAGOO 12 IVA2 array Powergood indication from Power is Power is DOUT 0 SRAM to PSCON bit 0 stable not stable PRCM_CORE_POWER_G 13 Indicates whether the CORE power Power is Power is OOD ...

Page 2507: ...AMRETO 11 SRAM retention on signal to MPU power Retention is Retention is NIN 0 domain bit 0 ON OFF PRCM_IVA2_SRAMAGOO 12 IVA2 array Powergood indication from Power is Power is DOUT 1 SRAM to PSCON bit 1 stable not stable PRCM_CORE_POWER_G 13 Indicates whether the CORE power Power is Power is OOD 2 switches status bit 2 stable not stable PRCM_CORE_SRAMRET 14 SRAM retention on signal to CORE power ...

Page 2508: ...transition of the VDD1 domain to Transition No ff_mode OFF_MODE initiated transition PRCM_MPU_SRAMRETO 11 SRAM retention on signal to MPU power Retention is Retention is NIN 1 domain bit 1 ON OFF PRCM_IVA2_SRAMAGOO 12 IVA2 array Powergood indication from Power is Power is DOUT 2 SRAM to PSCON bit 2 stable not stable PRCM_CORE_POWER_G 13 Indicates whether the CORE power Power is Power is OOD 3 swit...

Page 2509: ...tention is Retention is domain bit 0 ON OFF PRCM_MPU_SRAMRETG 11 Indicates whether the SRAM retention Power is Power is OODOUT 0 banks in the MPU domain are stable bit 0 stable not stable PRCM_IVA2_SRAMAGOO 12 IVA2 array Powergood indication from Power is Power is DOUT 3 SRAM to PSCON bit 3 stable not stable PRCM_CORE_POWER_R 13 CORE domain switch command for Retention is Retention is ET power ret...

Page 2510: ...n is Retention is domain bit 1 ON OFF PRCM_MPU_SRAMRETG 11 Indicates whether the SRAM retention Power is Power is OODOUT 1 banks in the MPU domain are stable bit 1 stable not stable PRCM_IVA2_SRAMAGOO 12 IVA2 array Powergood indication from Power is Power is DOUT 4 SRAM to PSCON bit 4 stable not stable PRCM_CORE_SRAMAONI 13 SRAM array power control input bit 0 for Array is Array is not N 0 CORE po...

Page 2511: ... OFF mode bit 0 OFF OFF PRCM_IVA2_POWER_ON 11 IVA2 switch command for power on Power is Power is ON OFF PRCM_IVA2_SRAMRETO 12 SRAM retention on signal to IVA2 power Retention is Retention is NIN 0 domain bit 0 ON OFF PRCM_CORE_SRAMAONI 13 SRAM array power control input bit 1 for Array is Array is not N 1 CORE power domain powered powered PRCM_CORE_SRAMRET 14 Indicates whether the SRAM retention Po...

Page 2512: ...asserted by the PRM when the State is State is not device enters in OFF mode bit 1 OFF OFF PRCM_IVA2_POWER_ISO 11 PM command for IVA2 domain isolation Isolation is Isolation is ON OFF PRCM_IVA2_SRAMRETO 12 SRAM retention on signal to IVA2 power Retention is Retention is NIN 1 domain bit 1 ON OFF PRCM_CORE_SRAMAONI 13 SRAM array power control input bit 2 for Array is Array is not N 2 CORE power dom...

Page 2513: ...waken up SLEEP mode PRCM_MPU_POWER_ON 10 MPU switch command for power on Power is Power is ON OFF PRCM_IVA2_POWER_GO 11 Indicates whether the IVA2 power switches Power is Power is OD 0 status bit 0 stable not stable PRCM_IVA2_SRAMRETO 12 SRAM retention on signal to IVA2 power Retention is Retention is NIN 2 domain bit 2 ON OFF PRCM_CORE_SRAMAONI 13 SRAM array power control input bit 3 for Array is...

Page 2514: ...s not OFF mode OFF OFF PRCM_MPU_POWER_ISO 10 PM command for MPU domain isolation Isolation is Isolation is ON OFF PRCM_IVA2_POWER_GO 11 Indicates whether the IVA2 power switches Power is Power is OD 1 status bit 1 stable not stable PRCM_IVA2_SRAMRETO 12 SRAM retention on signal to IVA2 power Retention is Retention is NIN 3 domain bit 3 ON OFF PRCM_CORE_SRAMAONI 13 SRAM array power control input bi...

Page 2515: ...s whether the MPU power switches Power is Power is OD 0 status bit 0 stable not stable PRCM_IVA2_POWER_GO 11 Indicates whether the IVA2 power switches Power is Power is OD 2 status bit 2 stable not stable PRCM_IVA2_SRAMRETO 12 SRAM retention on signal to IVA2 power Retention is Retention is NIN 4 domain bit 4 ON OFF PRCM_CORE_SRAMAONI 13 SRAM array power control input bit 5 for Array is Array is n...

Page 2516: ...FF PRCM_IO_WUCLK 9 I O Wakeup clock PRCM_MPU_POWER_GO 10 Indicates whether the MPU power switches Power is Power is OD 1 status bit 1 stable not stable PRCM_IVA2_POWER_GO 11 Indicates whether the IVA2 power switches Power is Power is OD 3 status bit 3 stable not stable PRCM_IVA2_SRAMRETG 12 Indicates whether the SRAM retention Power is Power is OODOUT 0 banks in the IVA2 domain are stable bit 0 st...

Page 2517: ...he MPU power switches Power is Power is OD 2 status bit 2 stable not stable PRCM_IVA2_POWER_GO 11 Indicates whether the IVA2 power switches Power is Power is OD 4 status bit 4 stable not stable PRCM_IVA2_SRAMRETG 12 Indicates whether the SRAM retention Power is Power is OODOUT 1 banks in the IVA2 domain are stable bit 1 stable not stable PRCM_CORE_SRAMAGO 13 CORE array Powergood indication from Po...

Page 2518: ...R_GO 10 Indicates whether the MPU power switches Power is Power is OD 3 status bit 3 stable not stable PRCM_IVA2_POWER_GO 11 Indicates whether the IVA2 power switches Power is Power is OD 5 status bit 5 stable not stable PRCM_IVA2_SRAMRETG 12 Indicates whether the SRAM retention Power is Power is OODOUT 2 banks in the IVA2 domain are stable bit 2 stable not stable PRCM_CORE_SRAMAGO 13 CORE array P...

Page 2519: ... OFF OFF PRCM_MPU_POWER_GO 10 Indicates whether the MPU power switches Power is Power is OD 4 status bit 4 stable not stable PRCM_IVA2_SRAMAONIN 11 SRAM array power control input bit 0 for Array is Array is not 0 IVA2 power domain powered powered PRCM_IVA2_SRAMRETG 12 Indicates whether the SRAM retention Power is Power is OODOUT 3 banks in the IVA2 domain are stable bit 3 stable not stable PRCM_CO...

Page 2520: ...s bit 5 stable not stable PRCM_IVA2_SRAMAONIN 11 SRAM array power control input bit 4 for Array is Array is not 1 IVA2 power domain powered powered PRCM_IVA2_SRAMRETG 12 Indicates whether the SRAM retention Power is Power is OODOUT 4 banks in the IVA2 domain are stable bit 4 stable not stable PRCM_CORE_SRAMAGO 13 CORE array Powergood indication from Power is Power is ODOUT 4 SRAM to PSCON bit 4 st...

Page 2521: ...anager State is State is not FSM that the PER domain power state is OFF OFF OFF PRCM_MPU_SRAMAONIN 10 SRAM array power control input bit 0 Array is Array is not 0 for MPU power domain powered powered PRCM_IVA2_SRAMAONIN 11 SRAM array power control input bit 2 Array is Array is not 2 for IVA2 power domain powered powered PRCM_CORE_POWER_O 12 CORE switch command for power on Power is Power is N ON O...

Page 2522: ... causes interference This periodicity generates a significant power peak at the selected frequency which in turn causes an EMI disturbance to the environment The harmonics of the generated signal system clock radiates in the other modules of the device and the spurious energy can be enough to cause enough interference which results in performance degradation in the form of high bit error rates in ...

Page 2523: ...ER domain DPLL USBHOST DPLL Figure 13 19 shows the integration of DPLL D in the device Figure 13 19 DPLL D Integration The control of the DPLL is done by the PRCM module and the SCM The PRCM module controls the clocking generation of the DPLL For more information see Chapter 3 Power Reset and Clock Management The SCM contains all necessary bits that control the EMI reduction feature SSC 2523 SWPU1...

Page 2524: ... The total spreading deviation is equal to twice Δf fc is the original clock frequency fm is the spreading frequency Figure 13 20 Spreading Generation Block Diagram This additional block generates the required waveform used to reduce EMI This waveform is then modulated with the initial signal to add some controlled deviation in the clock signal frequency which spreads the energy of the clock and i...

Page 2525: ...dulation rate fm which is used to determine the clock frequency spreading cycling rate and is the time during which the generated clock frequency varies through Δf and returns to the original frequency The modulation waveform which describes the variation curve in terms of time The spectral power reduction in the DPLL clocks is dependent on the modulation index K which is a ratio of spreading freq...

Page 2526: ...SC in the Time Domain 13 4 11 3 2 3 Estimation of the EMI Reduction Level Figure 13 23 shows the effect of spreading on a clock and its harmonics Figure 13 23 Peak Reduction Caused by Spreading The electromagnetic interference reduction can be estimated with the following equation Peak_power_reduction 10 log Deviation fc fm With 2526 System Control Module SWPU177N December 2009 Revised November 20...

Page 2527: ...ngular pattern as a percent of M would be equal to the percent of the output frequency spread Δf that is ΔM M Δf fc Next mark with Finp the frequency of the clock signal at the input of the DPLL Because it is divided to N 1 before entering the phase detector the internal reference frequency is Fref Finp N 1 Assume the central frequency fc to be equal to the DPLL output frequency Fout or fc Fout Fi...

Page 2528: ..._SPREADING_FREQ 29 28 R_DSS_DELTA_M_INT bit field Fractional part is controlled by 18 bit signal DeltaMStepFraction through the CONTROL CONTROL_X_DPLL_SPREADING_FREQ 27 10 R_DSS_DELTA_M_FRACT bit field The frequency spread achieved has an overshoot of 20 percent or an inaccuracy of 20 percent If the Q_X_SPREADING_SIDE bit CONTROL CONTROL_X_DPLL_SPREADING 8 is set to 1 the frequency spread on lower...

Page 2529: ...fm fc 0 001 is needed hence fm 0 001 fc 0 001 160 MHz 160 KHz To check whether the modulation frequency has the appropriate value check whether it is within the DPLL loop bandwidth or if fm Fref 70 12 8 70 182 86 KHz which is true 3 Calculate the contents of the CONTROL CONTROL_X_DPLL_SPREADING_FREQ 6 0 R_X_MOD_FREQ_MANT and CONTROL CONTROL_X_DPLL_SPREADING_FREQ 9 7 R_X_MOD_FREQ_EXP bit fields on ...

Page 2530: ...ATA1AUTOEN bit 0 The hsusb0_data1 MuxMode signal is driven by the CONTROL CONTROL_PADCONF_HSUSB0_DATA1 2 0 MUXMODE0 bit 1 The hsusb0_data1 MuxMode signal is forced to 0x2 when the CARKITEN signal is active NOTE Associated pad configuration registers remain unchanged For more information about high speed USB see Chapter 22 High Speed USB Controllers 13 5 1 2 Video Driver This section gives informat...

Page 2531: ...al pin mcbsp_clks For more information about McBSP see Chapter 21 McBSP 13 5 1 6 McBSP4 Internal Clock The McBSP4 internal clock gates the internal interconnect clock and selects the FSR CLKR and CLKS input for the McBSP4 The McBSP4 does not have mcbsp4_clkr and mcbsp4_fsr external pins Clock input is from the mcbsp4_clkx pin FSR input is from the mcbsp4_fsx pin CONTROL CONTROL_DEVCONF1 2 MCBSP4_C...

Page 2532: ...ONTROL CONTROL_PROG_IO2 7 PRG_I2C3_PULLUPRESX bit 0 I2C3 I O internal pullup enabled 1 I2C3 I O internal pullup disabled CONTROL CONTROL_PROG_IO_WKUP1 5 PRG_SR_PULLUPRESX bit 0 I2C4 I O internal pullup enabled 1 I2C4 I O internal pullup disabled NOTE This feature is used for the I2 C master operating mode For more information about I2 C see Chapter 17 Multimaster Highspeed I2 C Controller 13 5 1 1...

Page 2533: ...G_IO0 22 PRG_GPMC_A5_LB bit selects GPMC_A5 I O equivalent far end load within 0 Load range 1 pF 10 pF 1 Load range 10 pF 16 pF The CONTROL CONTROL_PROG_IO0 21 PRG_GPMC_A6_LB bit selects GPMC_A6 I O equivalent far end load within 0 Load range 1 pF 10 pF 1 Load range 10 pF 16 pF The CONTROL CONTROL_PROG_IO0 20 PRG_GPMC_A7_LB bit selects GPMC_A7 I O equivalent far end load within 0 Load range 1 pF 1...

Page 2534: ...selects GPMC_NCS3 I O equivalent far end load within 0 Load range 1 pF 10 pF 1 Load range 10 pF 16 pF The CONTROL CONTROL_PROG_IO0 9 PRG_GPMC_NCS4_LB bit selects GPMC_NCS4 I O equivalent far end load within 0 Load range 1 pF 10 pF 1 Load range 10 pF 16 pF The CONTROL CONTROL_PROG_IO0 8 PRG_GPMC_NCS5_LB bit selects GPMC_NCS5 I O equivalent far end load within 0 Load range 1 pF 10 pF 1 Load range 10...

Page 2535: ...d load within 0 Load range 1 pF 10 pF 1 Load range 10 pF 16 pF 13 5 1 14 MCSPI1 I O Far End Load Settings The CONTROL CONTROL_PROG_IO2 1 PRG_MCSPI1_MIN_CFG_LB bit selects CLK SOMI SIMO and CS0 I O equivalent far end load within 0 Load range 1 pF 10 pF 1 Load range 10 pF 16 pF The CONTROL CONTROL_PROG_IO2 0 PRG_MCSPI1_CS1_LB bit selects CS1 I O equivalent far end load within 0 Load range 1 pF 10 pF...

Page 2536: ...LIT 0 PBIASLITEPWRDNZ0 EPWRDNZ1 CONTROL CONTROL_WKUP_CTRL 6 GPIO_IO _PWRDNZ VMODE CONTROL CONTROL_PBIAS_LITE 0 CONTROL CONTROL_PBIAS_LITE 8 1 PBIASLITEVMODE0 PBIASLITEVMODE1 SUPPLY_HIGH CONTROL CONTROL_PBIAS_LITE 7 CONTROL CONTROL_PBIAS_LITE 15 0 PBIASLITESUPPLYHIGH0 PBIASLITESUPPLYHIGH1 SPEEDCTRL CONTROL CONTROL_PROG_IO1 20 N A 0 PRG_SDMMC1_SPEEDCTRL VMODEERROR CONTROL CONTROL_PBIAS_LITE 3 CONTRO...

Page 2537: ... V Normal 3 0 V operation Figure 13 24 describes the programming flow to go from 3 0 V to 1 8 V and vice versa Figure 13 24 Flow Chart The PBIAS output is the same as SDMMC1_VDDS SIM_VDDS when the corresponding PBIAS cell related PWRDNZ bitis LOW Once the SDMMC1_VDDS SIM_VDDS supply settles software releases the PWRNDZ pulls it HIGH This then starts up the PBIAS cell work to generate the PBIAS vol...

Page 2538: ...g PWRDNZx bit s is kept at 0 If the corresponding PWRDNZx bit s is 1 the INPUTENABLE bit must be maintained at 0 in the corresponding CONTROL_PADCONF_x register In this case the receiver buffer does not cause static current even if the pad is left floating Weak pullup pulldown resistors can be used to define the pad state if needed The setting of the weak pull resistor does not affect the I O leak...

Page 2539: ... VDD2 and VDDS Figure 13 25 show the expected behavior of PWRNDZ bit with regard to supply ramp up This figure also shows the only possible combination when VDDS ramps up before VDD2 Figure 13 25 VDDS Ramps Up Before VDD2 NOTE These timing requirements are applicable only when SDMMC1_VDDS SIM_VDDS is 3 0 V If SDMMC1_VDDS SIM_VDDS is 1 8 V VDDS and SDMMC1_VDDS SIM_VDDS can be ramped up simultaneous...

Page 2540: ...lication See Section 13 4 4 3 Pad Multiplexing Register Fields Example Each UART1 interface signal is available on two pads These signals are also multiplexed with a McBSP signal Assume that the McBSP interface is required in the system Therefore for the UART1 interface signals pads must be used where those signals are not multiplexed with the McBSP signal Identify the pad configuration registers ...

Page 2541: ... PULLTYPESELECT bit and 0b1 in the PULLUDENABLE bit of the corresponding pad configuration register Set the INPUTENABLE bit of the pad configuration register if the pin is used as input Example uart1_rts and uart1_tx are output signals therefore clear the INPUTENABLE bit of the corresponding pad configuration register Because uart1_cts and uart1_rx are input signals set the INPUTENABLE bit of the ...

Page 2542: ...ffers according to the I O cell types The following describes some pieces of advice which can be useful to avoid extra current leakage For input pins use a pullup down when possible For output pins check existing pulls to avoid conflicts For bidirectional pins reconfigure the pin as an output driving 0 when possible Some I O configurations involve modifications during the software setup of I Os an...

Page 2543: ...rnal pull together 3 Logic conflicts consist in different electrical levels at the same time on one line This can occur when several devices are connected to the same line The two possible cases are If no external device drives the line configure the pin to drive a 0 If another device drives the line either the same value has to be driven or the pin has to be disconnected HZ NOTE It is advised to ...

Page 2544: ...ct configuration of each pin direction input output bidirectional the CONTROL CONTROL_PADCONF_X and the GPIOi GPIO_OE registers must be written 2544 System Control Module SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2545: ...le 13 72 lists the PADCONFS registers Table 13 72 PADCONFS Register Summary Register Width Register Name Type Address Offset Physical Address Bits CONTROL_PADCONF_SDRC_D0 RW 32 0x0000 0000 0x4800 2030 CONTROL_PADCONF_SDRC_D2 RW 32 0x0000 0004 0x4800 2034 CONTROL_PADCONF_SDRC_D4 RW 32 0x0000 0008 0x4800 2038 CONTROL_PADCONF_SDRC_D6 RW 32 0x0000 000C 0x4800 203C CONTROL_PADCONF_SDRC_D8 RW 32 0x0000 ...

Page 2546: ..._NBE1 RW 32 0x0000 0098 0x4800 20C8 CONTROL_PADCONF_GPMC_WAIT0 RW 32 0x0000 009C 0x4800 20CC CONTROL_PADCONF_GPMC_WAIT2 RW 32 0x0000 00A0 0x4800 20D0 CONTROL_PADCONF_DSS_PCLK RW 32 0x0000 00A4 0x4800 20D4 CONTROL_PADCONF_DSS_VSYNC RW 32 0x0000 00A8 0x4800 20D8 CONTROL_PADCONF_DSS_DATA0 RW 32 0x0000 00AC 0x4800 20DC CONTROL_PADCONF_DSS_DATA2 RW 32 0x0000 00B0 0x4800 20E0 CONTROL_PADCONF_DSS_DATA4 R...

Page 2547: ...00 015C 0x4800 218C CONTROL_PADCONF_MCBSP1_DX RW 32 0x0000 0160 0x4800 2190 CONTROL_PADCONF_MCBSP_CLKS RW 32 0x0000 0164 0x4800 2194 CONTROL_PADCONF_MCBSP1_CLKX RW 32 0x0000 0168 0x4800 2198 CONTROL_PADCONF_UART3_RTS_SD RW 32 0x0000 016C 0x4800 219C CONTROL_PADCONF_UART3_TX_IRTX RW 32 0x0000 0170 0x4800 21A0 CONTROL_PADCONF_HSUSB0_STP RW 32 0x0000 0174 0x4800 21A4 CONTROL_PADCONF_HSUSB0_NXT RW 32 ...

Page 2548: ...DCONF_SAD2D_NTRST RW 32 0x0000 0214 0x4800 2244 CONTROL_PADCONF_SAD2D_TDO RW 32 0x0000 0218 0x4800 2248 CONTROL_PADCONF_SAD2D_TCK RW 32 0x0000 021C 0x4800 224C CONTROL_PADCONF_SAD2D_MSTDBY RW 32 0x0000 0220 0x4800 2250 CONTROL_PADCONF_SAD2D_IDLEACK RW 32 0x0000 0224 0x4800 2254 CONTROL_PADCONF_SAD2D_SWRITE RW 32 0x0000 0228 0x4800 2258 CONTROL_PADCONF_SAD2D_SREAD RW 32 0x0000 022C 0x4800 225C CONT...

Page 2549: ... 32 0x0000 0024 0x4800 2294 DMUX_1 CONTROL_MSUSPEN RW 32 0x0000 0028 0x4800 2298 DMUX_2 CONTROL_MSUSPEN RW 32 0x0000 002C 0x4800 229C DMUX_3 CONTROL_MSUSPEN RW 32 0x0000 0030 0x4800 22A0 DMUX_4 CONTROL_MSUSPEN RW 32 0x0000 0034 0x4800 22A4 DMUX_5 CONTROL_PROT_CTR R OCO 32 0x0000 0040 0x4800 22B0 L CONTROL_DEVCONF1 RW 32 0x0000 0068 0x4800 22D8 RESERVED R 32 0x0000 006C 0x4800 22DC CONTROL_PROT_ERR...

Page 2550: ...ONTROL_DEBOBS_0 RW 32 0x0000 01B0 0x4800 2420 CONTROL_DEBOBS_1 RW 32 0x0000 01B4 0x4800 2424 CONTROL_DEBOBS_2 RW 32 0x0000 01B8 0x4800 2428 CONTROL_DEBOBS_3 RW 32 0x0000 01BC 0x4800 242C CONTROL_DEBOBS_4 RW 32 0x0000 01C0 0x4800 2430 CONTROL_DEBOBS_5 RW 32 0x0000 01C4 0x4800 2434 CONTROL_DEBOBS_6 RW 32 0x0000 01C8 0x4800 2438 CONTROL_DEBOBS_7 RW 32 0x0000 01CC 0x4800 243C CONTROL_DEBOBS_8 RW 32 0x...

Page 2551: ...2C 0x4800 249C RAM_FW_REQINFO CONTROL_DPF_OCM_ RW 32 0x0000 0230 0x4800 24A0 RAM_FW_WR CONTROL_DPF_REGI RW 32 0x0000 0234 0x4800 24A4 ON4_GPMC_FW_ADD R_MATCH CONTROL_DPF_REGI RW 32 0x0000 0238 0x4800 24A8 ON4_GPMC_FW_REQI NFO CONTROL_DPF_REGI RW 32 0x0000 023C 0x4800 24AC ON4_GPMC_FW_WR CONTROL_DPF_REGI RW 32 0x0000 0240 0x4800 24B0 ON1_IVA2_FW_ADDR_ MATCH CONTROL_DPF_REGI RW 32 0x0000 0244 0x4800...

Page 2552: ...Address Offset Physical Address CONTROL_PADCONF_ RW 32 0x0000 0000 0x4800 2A00 WKUP_I2C4_SCL CONTROL_PADCONF_ RW 32 0x0000 0004 0x4800 2A04 WKUP_SYS_32K CONTROL_PADCONF_ RW 32 0x0000 0008 0x4800 2A08 WKUP_SYS_NRESWA RM CONTROL_PADCONF_ RW 32 0x0000 000C 0x4800 2A0C WKUP_SYS_BOOT1 CONTROL_PADCONF_ RW 32 0x0000 0010 0x4800 2A10 WKUP_SYS_BOOT3 CONTROL_PADCONF_ RW 32 0x0000 0014 0x4800 2A14 WKUP_SYS_B...

Page 2553: ...88 _CTRL RESERVED R 32 0x0000 0030 0x4800 2A8C CONTROL_VBBLDO_S RW 32 0x0000 0034 0x4800 2A90 W_CTRL 13 6 3 SCM Register Description 13 6 3 1 INTERFACE Register Description Table 13 77 through Table 13 79 describe the interface register bits Table 13 77 CONTROL_REVISION Address Offset 0x00 Physical address 0x4800 2000 Instance INTERFACE Description Control module Revision number Type R 31 30 29 28...

Page 2554: ...t used in the module R 0x0 0 AUTOIDLE Internal interface clock gating strategy R W 0x1 0x0 Interface clock is free running 0x1 Automatic interface clock gating strategy is applied based on the interconnect interface activity Table 13 80 Register Call Summary for Register CONTROL_SYSCONFIG SCM Integration Resets 0 System Power Management 1 2 3 Module Power Saving 4 SCM Programming Model Off Mode Pr...

Page 2555: ...x R W 0 0 PullUp Down disabled 1 PullUp Down enabled 27 OFFOUTVALUE1 Off mode pad_x output value R W 0 26 OFFOUTENABLE1 Off mode pad_x output enable value Warning This is an R W 0 active low signal 0 Output enabled 1 Output disabled 25 OFFENABLE1 Off mode pad_x state override control R W 0 0 Off mode disabled 1 Off mode enabled 24 INPUTENABLE1 Input enable value for pad_x R W 1 23 21 RESERVED Rese...

Page 2556: ...ines 0 1 CAUTION The OFFOUTENABLE and OFFOUTVALUE bits are functional only if the pad configuration supports output mode on at least one MUXMODE For a pad that supports only the input feature the OFFOUTENABLE and OFFOUTVALUE bits cannot be configured they are don t care and read always returns 0 NOTE The bit field gives the field number for the pairs of pads gathered in each register Table 13 83 d...

Page 2557: ...0204C 0b1 0b000 0b00 CONTROL_PADCONF_SDRC_D14 31 16 sdrc_d15 0x4800204C 0b1 0b000 0b00 CONTROL_PADCONF_SDRC_D16 15 0 sdrc_d16 0x48002050 0b1 0b000 0b00 CONTROL_PADCONF_SDRC_D16 31 16 sdrc_d17 0x48002050 0b1 0b000 0b00 CONTROL_PADCONF_SDRC_D18 15 0 sdrc_d18 0x48002054 0b1 0b000 0b00 CONTROL_PADCONF_SDRC_D18 31 16 sdrc_d19 0x48002054 0b1 0b000 0b00 CONTROL_PADCONF_SDRC_D20 15 0 sdrc_d20 0x48002058 0...

Page 2558: ...1 0b000 0b11 CONTROL_PADCONF_GPMC_D1 15 0 gpmc_d1 0x48002090 0b00000 0b1 0b000 0b11 CONTROL_PADCONF_GPMC_D1 31 16 gpmc_d2 0x48002090 0b00000 0b1 0b000 0b11 CONTROL_PADCONF_GPMC_D3 15 0 gpmc_d3 0x48002094 0b00000 0b1 0b000 0b11 CONTROL_PADCONF_GPMC_D3 31 16 gpmc_d4 0x48002094 0b00000 0b1 0b000 0b11 CONTROL_PADCONF_GPMC_D5 15 0 gpmc_d5 0x48002098 0b00000 0b1 0b000 0b11 CONTROL_PADCONF_GPMC_D5 31 16 ...

Page 2559: ...C_WAIT2 31 16 gpmc_wait3 0x480020D0 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_DSS_PCLK 15 0 dss_pclk 0x480020D4 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_DSS_PCLK 31 16 dss_hsync 0x480020D4 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_DSS_VSYNC 15 0 dss_vsync 0x480020D8 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_DSS_VSYNC 31 16 dss_acbias 0x480020D8 0b00 0b00000 0b1 0b0...

Page 2560: ...cam_pclk 0x48002110 0b00 0b00000 0b1 0b000 0b01 0b111 CONTROL_PADCONF_CAM_FLD 15 0 cam_fld 0x48002114 0b00 0b00000 0b1 0b000 0b01 0b111 CONTROL_PADCONF_CAM_FLD 31 16 cam_d0 0x48002114 0b00 0b00 0 0b1 0b000 0b01 0b111 CONTROL_PADCONF_CAM_D1 15 0 cam_d1 0x48002118 0b00 0b00 0 0b1 0b000 0b01 0b111 CONTROL_PADCONF_CAM_D1 31 16 cam_d2 0x48002118 0b00 0b00000 0b1 0b000 0b01 0b111 CONTROL_PADCONF_CAM_D3 ...

Page 2561: ...1 CONTROL_PADCONF_MMC2_DAT0 31 16 sdmmc2_dat1 0x4800215C 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_MMC2_DAT2 15 0 sdmmc2_dat2 0x48002160 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_MMC2_DAT2 31 16 sdmmc2_dat3 0x48002160 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_MMC2_DAT4 15 0 sdmmc2_dat4 0x48002164 0b00 0b00000 0b1 0b000 0b01 0b111 CONTROL_PADCONF_MMC2_DAT4 31 16 sdmmc2_dat5 ...

Page 2562: ...11 CONTROL_PADCONF_UART3_TX_IRTX 15 0 uart3_tx_irtx 0x480021A0 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_UART3_TX_IRTX 31 16 hsusb0_clk 0x480021A0 0b00 0b00000 0b1 0b000 0b01 0b111 CONTROL_PADCONF_HSUSB0_STP 15 0 hsusb0_stp 0x480021A4 0b00 0b00000 0b1 0b000 0b11 0b111 CONTROL_PADCONF_HSUSB0_STP 31 16 hsusb0_dir 0x480021A4 0b00 0b00000 0b1 0b000 0b01 0b111 CONTROL_PADCONF_HSUSB0_NXT 15 0 hs...

Page 2563: ... 0b000 0b11 0b111 CONTROL_PADCONF_SYS_NIRQ 31 16 sys_clkout2 0x480021E0 0b00 0b00000 0b1 0b000 0b01 0b111 CONTROL_PADCONF_SAD2D_MCAD0 15 0 sad2d_mcad0 0x480021E4 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_MCAD0 31 16 sad2d_mcad1 0x480021E4 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_MCAD2 15 0 sad2d_mcad2 0x480021E8 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_MCAD2 31 16 sad2...

Page 2564: ..._mcad30 0x48002220 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_MCAD30 31 16 sad2d_mcad31 0x48002220 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_MCAD32 15 0 sad2d_mcad32 0x48002224 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_MCAD32 31 16 sad2d_mcad33 0x48002224 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_MCAD34 15 0 sad2d_mcad34 0x48002228 0b00000 0b1 0b000 0b01 0b000 CO...

Page 2565: ...8 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_SREAD 15 0 sad2d_sread 0x4800225C 0b00000 0b1 0b000 0b00 0b000 CONTROL_PADCONF_SAD2D_SREAD 31 16 sad2d_mbusflag 0x4800225C 0b00000 0b1 0b000 0b01 0b000 CONTROL_PADCONF_SAD2D_SBUSFLAG 15 0 sad2d_sbusflag 0x48002260 0b00000 0b000 0b00 0b000 CONTROL_PADCONF_SDRC_SBUSFLAG 31 16 sdrc_cke0 0x48002260 0b000 0b00 0b111 CONTROL_PADCONF_SDRC_CKE1 15 0 sdr...

Page 2566: ...0 0b00000 0b1 0b000 0b11 0b100 CONTROL_PADCONF_ETK_D0 15 0 etk_d0 0x480025DC 0b00 0b00000 0b1 0b000 0b11 0b100 CONTROL_PADCONF_ETK_D0 31 16 etk_d1 0x480025DC 0b00 0b00000 0b1 0b000 0b11 0b100 CONTROL_PADCONF_ETK_D2 15 0 etk_d2 0x480025E0 0b00 0b00000 0b1 0b000 0b11 0b100 CONTROL_PADCONF_ETK_D2 31 16 etk_d3 0x480025E0 0b00 0b00000 0b1 0b000 0b11 0b100 CONTROL_PADCONF_ETK_D4 15 0 etk_d4 0x480025E4 0...

Page 2568: ...trl module clock divider R W 0x0 0 Clock is divided by 4 1 Clock is divided by 2 1 STARTSAVE Start pad configuration registers save mechanism R W 0x0 0x0 Save is not started 0x1 Save is running This bit is auto cleared after 8 interface clock cycles 0 FORCEOFFMODEEN Force OFF mode active R W 0x0 0x0 OFF mode is not forced active 0x1 OFF mode is forced active Table 13 85 Register Call Summary for R...

Page 2569: ...in McBSP_CLKS 5 RESERVED Read returns reset value R 0 4 MCBSP1_FSR Select the FSR input for the module McBSP1 R W 0x0 0x0 FSR is from the pin McBSP1_FSR 0x1 FSR is from the pin McBSP1_FSX 3 MCBSP1_CLKR Select the CLKR input for the module McBSP1 R W 0x0 0x0 CLKR is from the pin McBSP1_CLKR 0x1 CLKR is from the pin McBSP1_CLKX 2 MCBSP1_CLKS Select the CLKS input for the module McBSP1 R W 0x0 0x0 CL...

Page 2570: ... the logical ORed MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sensitivity no MSuspend signal reaches the module 0x6 No sensitivity no MSuspend signal reaches the module 0x7 No sensitivity no MSuspend signal reaches the module 20 18 MCBSP1MSCTRL Control McBSP_1 sensitivity to MCU and or DSP RW 0x0 MSuspend signals 0x0 No sensitivity no MSusp...

Page 2571: ... 0x1 Sensitivity to MCU MSuspend signals DSP signal ignored 0x2 Sensitivity to DSP MSuspend signal MCU signal ignored 0x3 Sensitivity to the logical ORed MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sensitivity no MSuspend signal reaches the module 0x6 No sensitivity no MSuspend signal reaches the module 0x7 No sensitivity no MSuspend signal...

Page 2572: ...CU and DSP MSuspend signals 0x5 No sensitivity no MSuspend signal reaches the module 0x6 No sensitivity no MSuspend signal reaches the module 0x7 No sensitivity no MSuspend signal reaches the module 26 24 GPTM6MSCTRL Control General Purpose Timer 6 sensitivity to MCU RW 0x0 and or DSP MSuspend signals 0x0 No sensitivity no MSuspend signal reaches the module 0x1 Sensitivity to MCU MSuspend signals ...

Page 2573: ...nal ignored 0x2 Sensitivity to DSP MSuspend signal MCU signal ignored 0x3 Sensitivity to the logical ORed MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sensitivity no MSuspend signal reaches the module 0x6 No sensitivity no MSuspend signal reaches the module 0x7 No sensitivity no MSuspend signal reaches the module 17 15 GPTM3MSCTRL Control Ge...

Page 2574: ... reaches the module 0x1 Sensitivity to MCU MSuspend signals DSP signal ignored 0x2 Sensitivity to DSP MSuspend signal MCU signal ignored 0x3 Sensitivity to the logical ORed MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sensitivity no MSuspend signal reaches the module 0x6 No sensitivity no MSuspend signal reaches the module 0x7 No sensitivity...

Page 2575: ...end signals 0x5 No sensitivity no MSuspend signal reaches the module 0x6 No sensitivity no MSuspend signal reaches the module 0x7 No sensitivity no MSuspend signal reaches the module 26 24 RESERVED Read returns reset value R 0x0 23 21 WD3MSCTRL Control Watch Dog 3 sensitivity to MCU and or DSP R W 0x1 MSuspend signals 0x0 No sensitivity no MSuspend signal reaches the module 0x1 Sensitivity to MCU ...

Page 2576: ...uspend signals DSP signal ignored 0x2 Sensitivity to DSP MSuspend signal MCU signal ignored 0x3 Sensitivity to the logical ORed MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sensitivity no MSuspend signal reaches the module 0x6 No sensitivity no MSuspend signal reaches the module 0x7 No sensitivity no MSuspend signal reaches the module 8 6 GP...

Page 2577: ...nsitivity to MCU MSuspend signals DSP signal ignored 0x2 Sensitivity to DSP MSuspend signal MCU signal ignored 0x3 Sensitivity to the logical ORed MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sensitivity no MSuspend signal reaches the module 0x6 No sensitivity no MSuspend signal reaches the module 0x7 No sensitivity no MSuspend signal reache...

Page 2578: ...0 29 27 DMAMSCTRL Control DMA sensitivity to MCU and or DSP MSuspend R W 0x0 signals 0x0 No sensitivity No MSuspend signal reaches the module 0x1 Sensitivity to MCU MSuspend signals DSP signal ignored 0x2 Sensitivity to DSP MSuspend signal MCU signal ignored 0x3 Sensitivity to the logical ORed MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sen...

Page 2579: ...MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sensitivity No MSuspend signal reaches the module 0x6 No sensitivity No MSuspend signal reaches the module 0x7 No sensitivity No MSuspend signal reaches the module 20 9 RESERVED Read returns reset value R 0x0 8 6 MCBSP5MSCTRL Control McBSP 5 Sensitivity to MCU and or DSP R W 0x0 MSuspend Signals 0...

Page 2580: ...0x0 No sensitivity no MSuspend signal reaches the module 0x1 Sensitivity to MCU MSuspend signals DSP signal ignored 0x2 Sensitivity to DSP MSuspend signal MCU signal ignored 0x3 Sensitivity to the logical ORed MCU and DSP MSuspend signals 0x4 Sensitivity to the logical ANDed MCU and DSP MSuspend signals 0x5 No sensitivity No MSuspend signal reaches the module 0x6 No sensitivity No MSuspend signal ...

Page 2581: ...iption 0 SCM Register Manual SCM Register Summary 1 Table 13 102 CONTROL_DEVCONF1 Address Offset 0x0000 0068 Physical Address Instance GENERAL 0x4800 22D8 Description CONTROL_DEVCONF1 register description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED TVACEN RESERVED RESERVED RESERVED RESERVED MCBSP5_CLKS MCBSP4_CLKS MCBSP3_CLKS TVOU...

Page 2582: ...load 10 RESERVED Read returns reset value R 0 9 MPUFORCEWRNP Force MPU writes to be nonposted RW 0 0 Posted writes 1 Nonposted writes 8 SENSDMAREQ3 Set sensitivity on SYS nDMAREQ3 input pin RW 0 0 Level sensitivity 1 Edge sensitivity 7 SENSDMAREQ2 Set sensitivity on SYS nDMAREQ2 input pin RW 0 0 Level sensitivity 1 Edge sensitivity 6 MMCSDIO2ADPCLKISEL MMC SDIO2 Module Input Clock selection RW 0 0...

Page 2583: ...MSFWERROR GPMCFWERROR L4EMUFWERROR MAD2DFWERROR L4COREFWERROR OCMRAMFWERROR OCMROMFWERROR SYSDMAACCERROR L4PERIPHFWERROR SMSFUNCFWERROR DISPDMAACCERROR SMXAPERTFWERROR CAMERADMAACCERROR Bits Field Name Description Type Reset 31 18 RESERVED Read returns reset value R 0x0 17 L4EMUFWERROR L4 Emulation Firewall Error R 0x0 0x0 No L4 Emulation interconnect firewall error 0x1 L4 Emulation interconnect f...

Page 2584: ...0 No MAD2D functional firewall error 0x0 No MAD2D functional firewall error 4 SMSFWERROR SMS Firewall Error R 0x0 0x0 No SMS firewall error 0x1 SMS firewall error 3 SMSFUNCFW SMS Functional Firewall Error R 0x0 ERROR 0x0 No SMS functional firewall error 0x1 SMS functional firewall error 2 GPMCFWERROR GPMC Firewall Error R 0x0 0x0 No error from GPMC protection firewall 0x1 Error from GPMC protectio...

Page 2585: ...l Debug 15 13 RESERVED Read returns reset value R 0x0 12 SMXAPERT L3 Register target Debug Firewall error R 0x0 DBGFWERROR 0x0 No firewall error in L3 Register Target Debug 0x1 Firewall error in L3 Register Target Debug 11 8 RESERVED Read returns reset value R 0x0 7 L4COREDBGFW L4 Core Debug Firewall Error R 0x0 ERROR 0x0 No firewall error in L4 Core Debug 0x1 Firewall error in L4 Core Debug 6 IVA...

Page 2586: ...NTROL_STATUS Address Offset 0x0000 0080 Physical Address Instance GENERAL 0x4800 22F0 Description CONTROL_STATUS register description Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SYSBOOT RESERVED DEVICETYPE Bits Field Name Description Type Reset 31 11 RESERVED Reserved field R 0x 10 8 DEVICETYPE Device type value sampled at power_on reset R ...

Page 2587: ...3 111 Register Call Summary for Register CONTROL_GENERAL_PURPOSE_STATUS SCM Functional Description Save and Restore Mechanism 0 SCM Register Manual SCM Register Summary 1 GENERAL Register Description 2 Table 13 112 CONTROL_RPUB_KEY_H_0 Address Offset 0x0000 0090 Physical Address Instance GENERAL 0x4800 2300 Description rpub_key_h_0 register description Type R 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 2588: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RPKH_2 Bits Field Name Description Type Reset 31 0 RPKH_2 Root_public_key_hash 2 R 0x0000 0000 Table 13 117 Register Call Summary for Register CONTROL_RPUB_KEY_H_2 SCM Register Manual SCM Register Summary 0 Table 13 118 CONTROL_RPUB_KEY_H_3 Address Offset 0x0000 009C Physical Address Instance GENERAL 0x4800 230C Des...

Page 2589: ...ype R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_PROD_ID USB_VENDOR_ID Bits Field Name Description Type Reset 31 16 USB_PROD_ID USB product ID R 0x0000 15 0 USB_VENDOR_ID Vendor ID R 0x0000 Table 13 123 Register Call Summary for Register CONTROL_USB_CONF_0 SCM Register Manual SCM Register Summary 0 Table 13 124 CONTROL_USB_CONF_1 Address Offset 0x0000...

Page 2590: ... Call Summary for Register CONTROL_FUSE_OPP1G2_VDD1 SCM Register Manual SCM Register Summary 0 Table 13 128 CONTROL_FUSE_OPP1G_VDD1 Address Offset 0x0000 0110 Physical Address 0x4800 2380 Instance GENERAL Description Standard fuse OPP1G VDD1 23 0 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FUSE_OPP1G_VDD1 Bits Field Name Description Type Re...

Page 2591: ...ndard fuse OPP100 VDD1 23 0 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FUSE_OPP100_VDD1 Bits Field Name Description Type Reset 31 24 RESERVED Read returns reset value R 0x00000000 23 0 FUSE_OPP100_VDD1 SmartReflex Ntarget value for OPP100 VDD1 R 0x 1 1 Register reset value undefined differs between devices Table 13 133 Register Call Summar...

Page 2592: ...artReflex Ntarget value for OPP100 VDD2 with SGX R 0x running at 266 MHz 1 1 1 This N target is blown only for the OMAP3630 1200 device Table 13 137 Register Call Summary for Register CONTROL_FUSE_OPP100_2_VDD2 SCM Register Manual SCM Register Summary 0 Table 13 138 CONTROL_FUSE_OPP50_VDD2 Address Offset 0x0000 0128 Physical Address 0x4800 2398 Instance GENERAL Description Standard fuse OPP50 VDD2...

Page 2593: ... Address Offset 0x0000 0130 Physical Address 0x4800 23A0 Instance GENERAL Description Fuse SR1 and SR2 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FUSE_SR2 FUSE_SR1 Bits Field Name Description Type Reset 31 16 RESERVED Read returns reset value R 0x00000000 15 8 FUSE_SR2 Fuse SR 2 R 0x00000000 7 0 FUSE_SR1 Fuse SR 1 R 0x00000000 Table 13 143...

Page 2594: ... reset value R 0x0 3 0 BOOTMODE Boot mode of the IVA2 R W 0x0 Table 13 147 Register Call Summary for Register CONTROL_IVA2_BOOTMOD SCM Functional Description IVA2 2 Boot Registers 0 1 SCM Register Manual SCM Register Summary 2 Table 13 148 CONTROL_PROG_IO2 Address Offset 0x0000 0198 Physical Address Instance GENERAL 0x4800 2408 Description prog_io2 register description Type RW 31 30 29 28 27 26 25...

Page 2595: ...1cm 6cm 0x1 Far end load 10pF 16pF TL length 1cm 6cm 26 25 PRG_CHASSIS_CLOCK_SC Slew rate control bits RW 0x1 Format used in the field name below is programmable_group_name _ configurable_pin on IO cell See Table 13 21 for the allowed SC vs LB bit field combinations 24 23 PRG_CHASSIS_CLOCK_LB Effective TL length and farend capacitive load controls RW 0x0 This bit allows control of programmable dri...

Page 2596: ...e 0b00 1 66K Ohms 5 12pF cap load 0b01 920 Ohms 12 25pF cap load 0b10 500 Ohms 25 50pF cap load 0b11 300 Ohms 50 80pF cap load See Table 13 24 for example LB1 LB0 bit field vs PRG_I2C2_PULLUPRESX bit combinations 9 8 PRG_I2C3_FS The bits select a proper resistor value for the I2C3 pull ups RW 0x0 for a given load range at FS HS modes Format used in the field name below is programmable_group_name _...

Page 2597: ... Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF cm 0x0 Far end load 1pF 10pF TL length 1cm 6cm 0x1 Far end load 10pF 16pF TL length 1cm 6cm Table 13 149 Register Call Summary for Register CONTROL_PROG_IO2 SCM Functional Description Signal Integrity Parameter Controls Overview 0 Device Interfaces Signal Group Controls Mapping 1 2 3 4 5 6 7 8 9 10 11 ...

Page 2598: ..._DEBOBS_0 SCM Functional Description Description 0 Observability Tables 1 2 SCM Register Manual SCM Register Summary 3 Table 13 154 CONTROL_DEBOBS_1 Address Offset 0x0000 01B4 Physical Address 0x4800 2424 Instance GENERAL Description Select the set of signals to be observed for hw_dbg2 hw_dbg3 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OB...

Page 2599: ...vability Tables 1 2 SCM Register Manual SCM Register Summary 3 Table 13 158 CONTROL_DEBOBS_3 Address Offset 0x0000 01BC Physical Address 0x4800 242C Instance GENERAL Description Select the set of signals to be observed for hw_dbg6 hw_dbg7 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OBSMUX6 RESERVED OBSMUX7 Bits Field Name Description Type ...

Page 2600: ...lity Tables 1 2 SCM Register Manual SCM Register Summary 3 Table 13 162 CONTROL_DEBOBS_5 Address Offset 0x0000 01C4 Physical Address 0x4800 2434 Instance GENERAL Description Select the set of signals to be observed for hw_dbg10 hw_dbg11 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OBSMUX10 RESERVED OBSMUX11 Bits Field Name Description Type ...

Page 2601: ...vability Tables 1 2 SCM Register Manual SCM Register Summary 3 Table 13 166 CONTROL_DEBOBS_7 Address Offset 0x0000 01CC Physical Address 0x4800 243C Instance GENERAL Description Select the set of signals to be observed for hw_dbg14 hw_dbg15 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OBSMUX14 RESERVED OBSMUX15 Bits Field Name Description T...

Page 2602: ... GENERAL 0x4800 2444 Description prog_io0 register description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SDRC_NCS0 SDRC_NCS1 SDRC_ADDRCTR SDRC_LOWDATA SDRC_HIGHDATA PRG_GPMC_A1_LB PRG_GPMC_A2_LB PRG_GPMC_A3_LB PRG_GPMC_A4_LB PRG_GPMC_A5_LB PRG_GPMC_A6_LB PRG_GPMC_A7_LB PRG_GPMC_A8_LB PRG_GPMC_A9_LB PRG_GPMC_A10_LB PRG_GPMC_A11_LB PRG_GMP...

Page 2603: ...x1 Far end load 10pF 16pF TL length 1cm 6cm 25 PRG_GPMC_A2_LB Format used in the field name below is RW 0 programmable_group_name _ configurable_pin on IO cell Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF cm 0x0 Far end load 1pF 10pF TL length 1cm 6cm 0x1 Far end load 10pF 16pF TL length 1cm 6cm 24 PRG_GPMC_A3_LB Format used in the field name belo...

Page 2604: ...le_group_name _ configurable_pin on IO cell Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF cm 0x0 Far end load 1pF 10pF TL length 1cm 6cm 0x1 Far end load 10pF 16pF TL length 1cm 6cm 14 PRG_GPMC_D8_D15_LB Format used in the field name below is RW 0 programmable_group_name _ configurable_pin on IO cell Far end load setting Transmission Line TL charac...

Page 2605: ...0x0 Far end load 1pF 10pF TL length 1cm 6cm 0x1 Far end load 10pF 16pF TL length 1cm 6cm 4 PRG_GPMC_NBE0_CLE_LB Format used in the field name below is RW 0 programmable_group_name _ configurable_pin on IO cell Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF cm 0x0 Far end load 1pF 10pF TL length 1cm 6cm 0x1 Far end load 10pF 16pF TL length 1cm 6cm 3 ...

Page 2606: ...setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF cm 0x0 Far end load 1pF 10pF TL length 1cm 6cm 0x1 Far end load 10pF 16pF TL length 1cm 6cm 30 PRG_GPMC_WAIT2_LB Format used in the field name below is RW 0 programmable_group_name _ configurable_pin on IO cell Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF cm 0x0 Far...

Page 2607: ...ll up resistors enable 0x0 Enables internal pull ups for the I2C1 pad group 0x1 Disables internal pull ups for the I2C1 pad group 18 PRG_HSUSB0_CLK_LB Format used in the field name below is RW 0 programmable_group_name _ configurable_pin on IO cell Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF cm 0x0 Far end load 1pF 10pF TL length 1cm 6cm 0x1 Far ...

Page 2608: ...l Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF cm 0x0 Far end load 1pF 10pF TL length 1cm 6cm 0x1 Far end load 10pF 16pF TL length 1cm 6cm 5 PRG_MCBSP4_LB Format used in the field name below is RW 0 programmable_group_name _ configurable_pin on IO cell Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitance 1pF ...

Page 2609: ...uide 39 40 Speed Control and Voltage Supply State 41 SCM Register Manual SCM Register Summary 42 Table 13 174 CONTROL_DSS_DPLL_SPREADING Address Offset 0x0000 01E0 Physical Address Instance GENERAL 0x4800 2450 Description control_dss_dpll_spreading register description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED Q_DSS_SPR...

Page 2610: ...ABLE_STATUS Bits Field Name Description Type Reset 31 9 RESERVED Read returns reset value R 0x000000 8 Q_CORE_SPREADING_SIDE 0 Enables both side frequency spread about the RW 0 programmed frequency 1 Enables low frequency spread only 7 CORE_SPREADING_ Indicates the status of the SSC feature R ENABLE_STATUS 6 5 RESERVED Read returns reset value R 0x0 4 CORE_SPREADING_ENABLE Enables disables EMI red...

Page 2611: ...uency 1 Enables low frequency spread only 7 PER_SPREADING_ Indicates the status of the SSC feature R ENABLE_STATUS 6 5 RESERVED Read returns reset value R 0x0 4 PER_SPREADING_ENABLE Enables disables EMI reduction feature spreading RW 0 0 Modulation stops at the end of the current modulation cycle 1 Modulation cycle is started 3 0 RESERVED Reserved field R 0x0 Table 13 179 Register Call Summary for...

Page 2612: ... returns reset value R 0 4 USBHOST_SPREADING_ENAB Enables disables EMI reduction feature spreading RW 0 LE 0 Modulation stops at the end of the current modulation cycle 1 Modulation cycle is started 3 0 RESERVED Reserved field R 0x0 Table 13 181 Register Call Summary for Register CONTROL_USBHOST_DPLL_SPREADING SCM Register Manual SCM Register Summary 0 Table 13 182 CONTROL_SDRC_SHARING Address Off...

Page 2613: ...ss 0x4800 2464 Instance GENERAL Description SDRC MCFG Configuration register 0 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRCMCFG0 RESERVED SDRCMCFG0LOCK Bits Field Name Description Type Reset 31 RESERVED Reserved for non GP devices Reserved 0x0 30 SDRCMCFG0LOCK Exported value to SDRC SDRC_MCFG_0 30 R W 0x0 For more information see Section 13 4 9...

Page 2614: ... 187 Register Call Summary for Register CONTROL_SDRC_MCFG1 SCM Functional Description SDRC Registers 0 1 2 SCM Register Manual SCM Register Summary 3 Table 13 188 CONTROL_MODEM_FW_CONFIGURATION_LOCK Address Offset 0x0000 01FC Physical Address 0x4800 246C Instance GENERAL Description Allows locking of the modem isolation registers in the SCM until the next battery removal Type RW 31 30 29 28 27 26 ...

Page 2615: ...essible by the See Table 13 193 0x0 Modem 30 27 MODEMSTACKMEMORYSIZE Configuration of the modem stack memory size See Table 13 193 0x0 26 22 MODEMSMSMEMORYSIZE Configuration of the SMS modem memory See Table 13 193 0x00 21 17 MODEMGPMCRESERVED Configuration of the GPMC modem shared section size See Table 13 193 0x00 S2SIZE 16 12 MODEMGPMCRESERVED Configuration of the GPMC modem reserved section si...

Page 2616: ... Register Call Summary for Register CONTROL_MODEM_GPMC_DT_FW_REQ_INFO SCM Register Manual SCM Register Summary 0 Table 13 196 Type Value For CONTROL_MODEM_GPMC_DT_FW_REQ_INFO CONTROL_MODEM_FW_CONFIGURATION_LOCK 0 FWCONFIGURATIONLOCK bit 0 1 MODEMGPMCDTFWREQINFO R W R Table 13 197 CONTROL_MODEM_GPMC_DT_FW_RD Address Offset 0x0000 0208 Physical Address 0x4800 2478 Instance GENERAL Description Modem ...

Page 2617: ...WWR Exported values to the GPMC firewall region1 See 0xFFFF WRITE_PERMISSION field Table 13 202 Table 13 201 Register Call Summary for Register CONTROL_MODEM_GPMC_DT_FW_WR SCM Register Manual SCM Register Summary 0 Table 13 202 Type Value For CONTROL_MODEM_GPMC_DT_FW_WR CONTROL_MODEM_FW_CONFIGURATION_LOCK 0 FWCONFIGURATIONLOCK bit 0 1 MODEMGPMCDTFWWR R W R Table 13 203 CONTROL_MODEM_GPMC_BOOT_CODE...

Page 2618: ...IGURATIONLOCK bit 0 1 GPMCBOOTCODEWRITEPROTECTED R W R GPMCBOOTCODESIZE R W R Table 13 206 CONTROL_MODEM_SMS_RG_ATT1 Address Offset 0x0000 0214 Physical Address 0x4800 2484 Instance GENERAL Description Modem SMS Default firewall register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMSRGATT1 Bits Field Name Description Type Reset 31 0 SMSRGATT1 Expo...

Page 2619: ...URATION_LOCK 0 FWCONFIGURATIONLOCK bit 0 1 SMSRGRDPERM1 R W R Table 13 212 CONTROL_MODEM_SMS_RG_WRPERM1 Address Offset 0x0000 021C Physical Address 0x4800 248C Instance GENERAL Description Modem SMS Default firewall write permission register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SMSRGWRPERM1 Bits Field Name Description Type Reset 31 ...

Page 2620: ...217 Type Value For CONTROL_MODEM_D2D_FW_DEBUG_MODE CONTROL_MODEM_FW_CONFIGURATION_LOCK 0 FWCONFIGURATIONLOCK bit 0 1 D2DFWDEBUGMODE R W R Table 13 218 CONTROL_DPF_OCM_RAM_FW_ADDR_MATCH Address Offset 0x0000 0228 Physical Address 0x4800 2498 Instance GENERAL Description OCM RAM Dynamic Power Framework Handing Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 2621: ...ddress 0x4800 24A0 Instance GENERAL Description OCM RAM Dynamic Power Framework Handing Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED REGIONOCMRAMFWWR Bits Field Name Description Type Reset 31 16 RESERVED Read returns reset value R 0x00000 15 0 REGIONOCMRAMFWWR See L3 FW WR permission field R 0xFFFF Table 13 223 Register Call Summary for Reg...

Page 2622: ...0x0000 15 0 REGION4GPMCFWREQINFO Exported value to L3 FW region 4 GPMC R 0xFFFF REQINFO_PERMISSION_4 field Table 13 227 Register Call Summary for Register CONTROL_DPF_REGION4_GPMC_FW_REQINFO SCM Register Manual SCM Register Summary 0 Table 13 228 CONTROL_DPF_REGION4_GPMC_FW_WR Address Offset 0x0000 023C Physical Address 0x4800 24AC Instance GENERAL Description GPMC Dynamic Power Framework Handing ...

Page 2623: ... Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED REGION1IVA2FWREQINFO Bits Field Name Description Type Reset 31 16 RESERVED Read returns reset value R 0x0 15 0 REGION1IVA2FWREQINFO Exported value to L3 FW region 1 IVA2 R 0xFFFF REQINFO_PERMISSION_1 field Table 13 233 Register Call Summary for Register CONTROL_DPF_REGION1_IVA2_FW_REQINFO SCM Re...

Page 2624: ...IASLITEVMODEERROR1 Status indicating if the software programmed VMODE R 0 level matches the SUPPLY_HI output signal 0b0 VMODE Level same or VMODE level not considered 0b1 indicates VMODE_LEVEL not same as SUPPLY_HI_OUT 10 RESERVED Reserved R 0x0 9 PBIASLITEPWRDNZ1 Input signal referenced to VDD2 Software must keep this R W 0 signal low whenever SIM_VDDS is ramping up 1 SIM_VDDS stable 0 SIM_VDDS i...

Page 2625: ...ance GENERAL Description temperature sensor register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TEMP SOC EOCZ CONTCONV Bits Field Name Description Type Reset 31 11 RESERVED Read returns reset value R 0x0 10 CONTCONV VDD level digital inputs When high the ADC is in RW 0x0 continuous conversion mode 0 ADC Single Conversion Mode 1 ADC Contin...

Page 2626: ...x0000000 H Table 13 241 Register Call Summary for Register CONTROL_DPF_MAD2D_FW_ADDR_MATCH SCM Register Manual SCM Register Summary 0 Table 13 242 CONTROL_DPF_MAD2D_FW_REQINFO Address Offset 0x0000 02CC Physical Address 0x4800 253C Instance GENERAL Description MAD2D Dynamic Power Framework Handing Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVE...

Page 2627: ...Instance GENERAL 0x4800 2544 Description control_dss_dpll_spreading_freq register description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R_DSS_DELTA_M_FRACT R_DSS_MOD_FREQ_MANT RESERVED R_DSS_DELTA_M_INT R_DSS_MOD_FREQ_EXP Bits Field Name Description Type Reset 31 30 RESERVED Reserved field R 0x0 29 28 R_DSS_DELTA_M_INT Integer part of DeltaM coef...

Page 2628: ...sa of ModFreqDivider coefficient RW 0x00 Table 13 249 Register Call Summary for Register CONTROL_CORE_DPLL_SPREADING_FREQ SCM Register Manual SCM Register Summary 0 Table 13 250 CONTROL_PER_DPLL_SPREADING_FREQ Address Offset 0x0000 02DC Physical Address Instance GENERAL 0x4800 254C Description control_per_dpll_spreading_freq register description Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 2629: ...BHOST_MOD_FREQ_EXP R_USBHOST_MOD_FREQ_MANT Bits Field Name Description Type Reset 31 30 RESERVED Reserved field R 0x0 29 28 R_USBHOST_DELTA_M_INT Integer part of DeltaM coefficient RW 0x00000 27 10 R_USBHOST_DELTA_M_FRACT Fractional part of DeltaM coefficient RW 0x00000 9 7 R_USBHOST_MOD_FREQ_EXP Exponent of ModFreqDivider coefficient RW 0x0 6 0 R_USBHOST_MOD_FREQ_MANT Mantissa of ModFreqDivider c...

Page 2630: ...e configured as Chroma video channel dual channel configuration 17 AVDAC1_COMP_EN 1 Optional control for lower output swing It should be low RW 0x0 by default high output swing 0 default High full scale output swing 1 Low full scale output swing 16 AVDAC1_COMP_EN 0 Optional control for internal current reference It should RW 0x0 be low by default external current reference 0 default External curre...

Page 2631: ...l dual channel configuration 17 AVDAC2_COMP_EN 1 Optional control for lower output swing It should be low RW 0x0 by default high output swing 0 default High full scale output swing 1 Low full scale output swing 16 AVDAC2_COMP_EN 0 Optional control for internal current reference It should RW 0x0 be low by default external current reference 0 default External current reference external resistor conn...

Page 2632: ...f CSIPHY2 RW 0x0 CAMMODE 00 D PHY mode 01 CCP2 mode configured for data strobe transmission 10 CCP2 mode configured for data clock transmission 11 GPI mode Not a dynamic signal Should be changed only when the CSIPHY2 is in OFF power state Table 13 259 Register Call Summary for Register CONTROL_CAMERA_PHY_CTRL SCM Register Manual SCM Register Summary 0 NOTE If the parallel camera sensor is the only...

Page 2633: ...t PADCONF_WKUP register gathers the configuration of two pads For example CONTROL CONTROL_PADCONF_I2C4_SCL pad is used to configure i2c4_scl pad bits 15 0 and i2c4_sda pad bits 31 16 See Figure 13 8 for more information about PADCONF registers According to the pad type some features are configurable or not Table 13 81 gives the description of a fully configurable pad Table 13 262 describes the res...

Page 2634: ...F_SYS_OFF_MODE 15 0 sys_off_mode 0x48002A18 0b00 0b1 0b000 0b01 0b111 CONTROL_PADCONF_SYS_OFF_MODE 31 16 sys_clkout1 0x48002A18 0b00 0b1 0b000 0b01 0b111 CONTROL_PADCONF_JTAG_NTRST 15 0 jtag_ntrst 0x48002A1C 0b1 0b000 0b01 CONTROL_PADCONF_JTAG_NTRST 31 16 jtag_tck 0x48002A1C 0b1 0b000 0b01 CONTROL_PADCONF_JTAG_TMS_TMSC 15 0 jtag_tms_tmsc 0x48002A20 0b1 0b000 0b11 CONTROL_PADCONF_JTAG_TMS_TMSC 31 1...

Page 2635: ...e pulled down by asserting the PIPD pin 5 GPIO_1_IN_SEL_SAD2D_NRES Mux select for GPIO1 SAD2D_NRESWARM bit RW 0 WARM_IN_SEL 4 3 RESERVED Reserved field R 0x0 2 MM_FSUSB3_TXEN_N_OUT_P Polarity control for TXEN signal of multimode USB RW 0 OLARITY_CTRL interface port3 0 Active low 1 Active high 1 MM_FSUSB2_TXEN_N_OUT_P Polarity control for TXEN signal of multimode USB RW 0 OLARITY_CTRL interface por...

Page 2636: ...observed for hw_dbg1 See Table 13 267 0x00 7 5 RESERVED Read returns reset value R 0x0 4 0 OBSMUX0 Select the set of signals to be observed for hw_dbg0 See Table 13 267 0x00 Table 13 266 Register Call Summary for Register CONTROL_WKUP_DEBOBS_0 SCM Functional Description Description 0 Observability Tables 1 2 3 4 SCM Register Manual SCM Register Summary 5 Table 13 267 Type Value For CONTROL_WKUP_DE...

Page 2637: ...4 31 WKUPOBSERVABILITYDISABLE bit 0 1 OBSMUX7 RW R OBSMUX6 RW R OBSMUX5 RW R OBSMUX4 RW R Table 13 271 CONTROL_WKUP_DEBOBS_2 Address Offset 0x0000 0014 Physical Address 0x4800 2A70 Instance GENERAL_WKUP Description Select the WKUP domain set of signals to be observed for hw_dbg11 hw_dbg10 hw_dbg9 hw_dbg8 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 2638: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OBSMUX15 OBSMUX14 OBSMUX13 OBSMUX12 RESERVED RESERVED RESERVED RESERVED Bits Field Name Description Type Reset 31 29 RESERVED Read returns reset value R 0x0 28 24 OBSMUX15 Select the set of signals to be observed for hw_dbg15 See 0x00 Table 13 276 23 21 RESERVED Read returns reset value R 0x0 20 16 OBSMUX14 Select the set of signals to be observed for hw_db...

Page 2639: ... the ObsMux bit field in CONTROL_DEBOBS register 0x1 Observability is disabled If pads are configured for the hardware debug output is tied low 30 13 RESERVED Read returns reset value R 0x00000 12 8 OBSMUX17 Select the set of signals to be observed for hw_dbg17 See 0x00 Table 13 279 7 5 RESERVED Read returns reset value R 0x0 4 0 OBSMUX16 Select the set of signals to be observed for hw_dbg16 See 0...

Page 2640: ...See Table 13 21 for the allowed SC vs LB bitfield combinations 27 26 PRG_CLKREQ_SC Slew rate control bits RW 0x0 Format used in the field name below is programmable_group_name _ configurable_pin on I O cell See Table 13 21 for the allowed SC vs LB bitfield combinations 25 24 PRG_CLKREQ_LB Effective TL length and farend capacitive load controls RW 0x0 This bit allows control of programmable drive s...

Page 2641: ...e slew control on IO cell Format used in the field name below is programmable_group_name _ configurable_pin on I O cell See Table 13 21 for the allowed SC vs LB bitfield combinations 10 PRG_CHASSIS_PRCM_LB_WK Format used in the field name below is RW 0 UP programmable_group_name _ configurable_pin on I O cell Far end load setting Transmission Line TL characteristic impedance is 50 Ohm TL capacitan...

Page 2642: ...p Controls Mapping 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SCM Programming Model I2C I O Internal Pullup Enable 18 SCM Register Manual SCM Register Summary 19 GENERAL_WKUP Register Description 20 Table 13 282 CONTROL_BGAPTS_WKUP Address Offset 0x0000 0028 Physical Address Instance GENERAL_WKUP 0x4800 2A84 Description CONTROL_BGAPTS_WKUP register description Type RW 31 30 29 28 27 26 25 24 23 22 ...

Page 2643: ...eld R 0x000 5 0 RESERVED Write the reset value read returns the reset value RW 0 Table 13 285 Register Call Summary for Register CONTROL_SRAM_LDO_CTRL SCM Register Manual SCM Register Summary 0 GENERAL_WKUP Register Description 1 Table 13 286 CONTROL_VBBLDO_SW_CTRL Address Offset 0x0000 0034 Physical Address Instance GENERAL_WKUP 0x4800 2A90 Description CONTROL_VBBLDO_SW_CTRL register description ...

Page 2644: ...DOBYPASSZ RW 0 0 AIPOFF Override AIPOFF input When high will act as AIPOFF for RW 0 VBBLDO Table 13 287 Register Call Summary for Register CONTROL_VBBLDO_SW_CTRL SCM Register Manual SCM Register Summary 0 GENERAL_WKUP Register Description 1 2644 System Control Module SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2645: ...cation IPC module in the device Topic Page 14 1 IPC Overview 2646 14 2 IPC Integration 2646 14 3 IPC Mailbox Functional Description 2650 14 4 IPC Mailbox Basic Programming Model 2653 14 5 IPC Mailbox Register Manual 2657 2645 SWPU177N December 2009 Revised November 2010 Interprocessor Communication Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2646: ...re 14 1 shows a block diagram of the interprocessor communication IPC module Figure 14 1 Simplified Block Diagram of the IPC The mailbox module includes these features Two mailbox message queues for microprocessor unit MPU and imaging video and audio accelerator IVA2 2 communications Flexible assignment of receiver and sender for each mailbox through interrupt configuration 32 bit message width Fo...

Page 2647: ...ed internally and can be turned off to lower operating power when a module is not active The exact frequency of this clock depends on PRCM programming 14 2 1 2 Resets The IPC supports both a hardware reset and a software reset 14 2 1 2 1 Hardware Reset The mailbox module receives its reset signal CORE_RST the reset signal of the CORE power domain from the PRCM module 14 2 1 2 2 Software Reset The ...

Page 2648: ...CM module the mailbox module enters the idle state only after all asserted output interrupts are acknowledged Table 14 1 describes the mailbox power management modes Table 14 1 Mailbox Power Management Modes Power Management Mode MAILBOX MAILBOX_SYSCONFIG 4 3 SIDLEMODE Bit Field Requested by the PRCM Offset 0x010 Force idle 00 No idle 01 Smart idle 10 Reserved not used 11 NOTE The mailbox idle sta...

Page 2649: ...system interrupt controller MAIL_U1_IVA2_IRQ mapped on IVA2_IRQ 10 of the IVA2 2 subsystem interrupt controller Each interrupt allows the user MPU subsystem or IVA2 2 subsystem of the mailbox to be notified when a message is received or when the message queue is not full There is one interrupt per user 14 2 2 2 Idle Handshake Protocol The PRCM module handles an idle handshake protocol for the mail...

Page 2650: ...er from 0 to 1 The mailbox module provides a means of communication through message queues among the MPU and the IVA2 2 The two individual mailbox modules or FIFOs can associate with any of the processors using the MAILBOX MAILBOX_IRQENABLE_u registers The mailbox module includes the following two user subsystems User 0 MPU subsystem u 0 User 1 IVA2 2 subsystem u 1 Each user has a dedicated interr...

Page 2651: ...itial mailbox status check indicates the mailbox is full In this case the sender can enable the queue not full interrupt for its mailbox in the appropriate MAILBOX MAILBOX_IRQENABLE_u register This allows the sender to be notified by interrupt only when a FIFO queue has at least one available entry Reading the MAILBOX MAILBOX_IRQSTATUS_u register determines the status of the new message and the qu...

Page 2652: ...t always be accessed by either single 32 bit accesses or two consecutive 16 bit accesses CAUTION When using 16 bit accesses it is critical to ensure that the mailbox used has only one assigned receiver and only one assigned sender When using 16 bit accesses to the MAILBOX MAILBOX_MESSAGE_m registers the order of access must be the least significant half word first low address and the most signific...

Page 2653: ...QENABLE_u register The software must ensure that only one sender and one receiver are assigned per mailbox For example to assign mailbox 1 m 1 to the MPU u 0 see Section 14 3 Mailbox Functional Description for the user number as a receiver set the MAILBOX MAILBOX_IRQENABLE_0 2 NEWMSGENABLEUUMB1 bit to generate an interrupt to the MPU when a new message is received in mailbox 1 To assign mailbox 0 ...

Page 2654: ...the MAILBOX MAILBOX_MSGSTATUS_m register s to determine the number of messages in the FIFO queue The receiver can poll the appropriate MAILBOX MAILBOX_MSGSTATUS_m register s to check the status and determine if there are any pending messages to read The receiver can read the MAILBOX MAILBOX_MSGSTATUS_m 2 0 NBOFMSGMB field to determine how many messages are available 3 Using either ISR or polling m...

Page 2655: ...the MAILBOX MAILBOX_FIFOSTATUS_0 0 FIFOFULLMB bit or the MAILBOX MAILBOX_FIFOSTATUS_1 0 FIFOFULLMB bit for the IVA2 2 subsystem 2 If mailbox 0 or mailbox 1 for the IVA2 2 subsystem is full the MPU subsystem or the IVA2 2 subsystem can enable the queue not full interrupt by setting the MAILBOX MAILBOX_IRQENABLE_0 1 NOTFULLENABLEUUMB0 bit or the MAILBOX MAILBOX_IRQENABLE_1 3 NOTFULLENABLEUUMB1 bit f...

Page 2656: ...ws these steps 1 The MPU subsystem or the IVA2 2 subsystem determines how many messages are stored in the message queue of mailbox 1 by reading the MAILBOX MAILBOX_MSGSTATUS_1 2 0 NBOFMSGMB field or the MAILBOX MAILBOX_MSGSTATUS_0 2 0 NBOFMSGMB bit field for the IVA2 2 subsystem 2 The MPU subsystem or the IVA2 2 subsystem reads the MAILBOX MAILBOX_MESSAGE_1 register or the MAILBOX MAILBOX_MESSAGE_...

Page 2657: ...to 1 2 u 0 to 1 NOTE In MAILBOX_MESSAGE_0 MAILBOX_MESSAGE_1 MAILBOX_FIFOSTATUS_0 MAILBOX_FIFOSTATUS_1 MAILBOX_MSGSTATUS_0 and MAILBOX_MSGSTATUS_1 register names 0 or 1 is the mailbox number In MAILBOX_IRQSTATUS_0 MAILBOX_IRQSTATUS_1 MAILBOX_IRQENABLE_0 and MAILBOX_IRQENABLE_1 register names 0 or 1 is the user number User 0 MPU subsystem User 1 IVA2 2 subsystem 14 5 2 Register Description Table 14 ...

Page 2658: ...ed unconditionally 0x1 No idle An idle request is never acknowledged 0x2 Smart idle Acknowledgement to an idle request is given based on the internal activity of the module based on the internal activity of the module 0x3 Reserved Do not use 2 Reserved Write 0 s for future compatibility Read returns 0 RW 0 1 SOFTRESET Software reset This bit is automatically reset by the hardware During RW 0 reads...

Page 2659: ...r Mapping Summary 1 Table 14 10 MAILBOX_MESSAGE_m Address Offset 0x040 MAILBOX_MESSAGE_0 for mailbox 0 0x044 MAILBOX_MESSAGE_1 for mailbox 1 Physical Address 0x4809 4040 MAILBOX_MESSAGE_0 for mailbox 0 Instance MLB 0x4809 4044 MAILBOX_MESSAGE_1 for mailbox 1 Description The message register stores the next to be read message of the mailbox X Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 2660: ...ion 0 1 Description 2 IPC Mailbox Basic Programming Model Mailbox Communication Preparation 3 4 Mailbox Communication Sequence 5 6 IPC Mailbox Register Manual Mailbox Register Mapping Summary 7 Table 14 14 MAILBOX_MSGSTATUS_m Address Offset 0x0C0 MAILBOX_MSGSTATUS_0 for mailbox 0 0x0C4 MAILBOX_MSGSTATUS_1 for mailbox 1 Physical Address 0x4809 40C0 MAILBOX_MSGSTATUS_0 for mailbox 0 Instance MLB 0x4...

Page 2661: ...iven bit resets this bit Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NOTFULLSTATUSUUMB1 NOTFULLSTATUSUUMB0 NEWMSGSTATUSUUMB1 NEWMSGSTATUSUUMB0 Bits Field Name Description Type Reset 31 4 Reserved Write 0s for future compatibility Read returns 0 RW 0x0000000 3 NOTFULLSTATUSUUMB1 NotFull Status bit for User u Mailbox 1 RW 0 2 NEWMSGSTATUSUUM...

Page 2662: ...e Description Type Reset 31 4 Reserved Write 0s for future compatibility Read returns 0 RW 0x0000000 3 NOTFULLENABLEUUMB1 NotFull Enable bit for User u Mailbox 1 RW 0 2 NEWMSGENABLEUUMB1 NewMessage Enable bit for User u Mailbox 1 RW 0 1 NOTFULLENABLEUUMB0 NotFull Enable bit for User u Mailbox 0 RW 0 0 NEWMSGENABLEUUMB0 NewMessage Enable bit for User u Mailbox 0 RW 0 Table 14 19 Register Call Summa...

Page 2663: ...he memory management units MMUs Topic Page 15 1 MMU Overview 2664 15 2 MMU Integration 2665 15 3 MMU Functional Description 2668 15 4 MMU Basic Programming Model 2680 15 5 MMU Register Manual 2687 2663 SWPU177N December 2009 Revised November 2010 Memory Management Units Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2664: ...efix provides information about the register instantiation where n 1 for the camera MMU and n 2 for the IVA2 2 MMU The MMU instances include the following main features N entries fully associative translation look aside buffer TLB with N 8 for the camera MMU and N 32 for the IVA2 2 MMU 1 interrupt line out to the MPU subsystem 32 bit virtual addresses 32 bit physical address Mapping size 4KB and 6...

Page 2665: ... L4 core interconnect The IVA2 2 MMU is programmed through the L3 interconnect Both MMU error conditions are signaled as interrupts to the system master processor that is the MPU Figure 15 2 and Figure 15 3 show the system integration of the camera MMU instance and the IVA2 2 MMU instance Figure 15 2 Camera MMU System Integration Figure 15 3 IVA2 2 MMU System Integration 15 2 1 Clock Domains The c...

Page 2666: ...mode The MMU instance never enters the idle state Force idle mode The MMU instance immediately enters the idle state after receiving a low power mode request from the PRCM module In this mode the software must ensure that there are no pending interrupts before requesting this mode to go into the idle state otherwise an error can occur Smart idle mode After receiving a low power mode request from t...

Page 2667: ...enabled but no valid page table entry exists for the requested address TLB miss with table walk disabled No translation is found in the TLB for the given virtual address and the table walking logic is disabled Each of these events can be individually enabled and disabled using the MMUn MMU_IRQENABLE register If an event occurs and is enabled an interrupt is generated to the MPU The MPU can use the...

Page 2668: ...when the MMU instance is enable That is when MMUn MMU_CNTL 1 MMUENABLE is set to 1 Figure 15 4 shows the relationship between the physical address the virtual address and the MMU Figure 15 4 MMU Address Translation 15 3 1 MMU Benefits The MMU offers two major benefits Memory defragmentation Fragmented physical memory can be translated into contiguous virtual memory without moving data Memory prote...

Page 2669: ...gions prevents this problem because a region of unmapped memory separates the two tasks Any erroneous access to this region results in an error that can be detected easily 15 3 2 MMU Architecture The MMU translation process is based on translation entries stored in translation tables One first level translation table can exist with several optional second level translation tables Each table entry ...

Page 2670: ...e 15 6 MMU Architecture 15 3 2 1 MMU Address Translation Process Whenever an address translation is requested that is for every access with the MMU enabled the MMU first checks whether the translation is already contained in the TLB which acts like a cache storing recent translations The TLB can also be programmed manually to ensure that time critical data can be translated without delay If the re...

Page 2671: ...6MB supersection Using bigger page sizes means a smaller translation table Using a smaller page size greatly increases the efficiency of dynamic memory allocation and defragmentation That is why many operating systems OSs can operate on memory blocks as small as 4KB however the smaller size implies a more complex table structure A quick calculation shows that using 4KB memory pages with one transl...

Page 2672: ... Translation 15 3 3 2 First Level Translation Table The first level translation table describes the translation properties for 1MB sections To describe a 4GB address range requires 4096 32 bit entries so called first level descriptors The first level translation table start address must be aligned on a multiple of the table size with a 128 byte minimum Consequently an alignment of at least 16K byt...

Page 2673: ...X 0 0 Fault Second Level Translation Table Base Address X 0 1 Page Section Base Address X 0 M X E X ES X 1 0 Section 1 Supersection Base Address X 1 M X E X ES X 1 0 Supersection X 1 1 Fault 1 See Table 15 34 for endianness limitations M Mixed region 0 Page based endianness 1 Access based endianness E Endianness 0 Little endian 1 Big endian endianness is locked on little endian ES Element Size 00 ...

Page 2674: ... detection or if the specified element size parameter is used page based detection For example the specified element size parameter can be used when several smaller sized accesses are packed into a bigger sized access such as two 16 bit accesses packed into one 32 bit access In this case with no specified data access size 32 bits would be the access size detected leading to an incorrect result To ...

Page 2675: ...ed by bits 19 to 12 of the virtual address Figure 15 13 shows this indexing mechanism Figure 15 13 Two Level Translation Each second level translation table describes the translation of 1MB of address space in pages of 64KB large page or 4KB small page It consists of 256 second level descriptors describing 4KB each NOTE In the case of a large page the same descriptor must be repeated 16 times If a...

Page 2676: ...16 15 12 11 10 9 8 6 5 4 3 2 1 0 X 0 0 Fault Large Page Base Address X M X E X ES X 0 1 Large Page 1 Small Page Base Address M X E X ES X 1 X Small Page 1 See Table 15 34 for endianness limitations M Mixed region 0 Page based endianness 1 Access based endianness E Endianness 0 Little endian 1 Big endian endianness is locked on little endian ES Element Size 00 8 bit 01 16 bit 10 32 bit 11 No endian...

Page 2677: ...n is already cached in the TLB If the translation is cached this translation is used otherwise the translation is retrieved from the translation tables and the TLB is updated If the TLB is full one of its entries must be replaced This entry is selected on a random basis The first n TLB entries where n Total Number N of TLB Entries can be protected locked against being overwritten by setting the TL...

Page 2678: ...ntains the section page size as well as the preserved and the valid parameters See the MMU_CAM register table for more details The RAM part contains the address translation that belongs to the virtual address tag as well as the endianness element size and mixed parameters described in Section 15 3 3 2 See the MMU_RAM register table for more details The valid parameter specifies whether an entry is...

Page 2679: ... by the MMU while the fault is handled For example for a TLB miss the ISR might load the missing entry into the TLB The ISR can determine the cause of the fault interrupt by reading the MMUn MMU_IRQSTATUS register The virtual address that caused the fault can be determined by reading the MMUn MMU_FAULT_AD register In the case of a TLB miss the MMU continues servicing the request as soon as a valid...

Page 2680: ...e details They are automatically written by the MPU OS Symbian Linux Operating System may limit the memory section size to page or sections A MPU memory management software treats all information concerning addressing Sub set tables can be copied into external SDRAM to automatically create a given MMU translation table Features such as mixed region endianness element size are then overwritten in S...

Page 2681: ...tatically written in the TLB This method avoids the need to write Translation tables in memory and is commonly used for relatively small address spaces It ensures that the translation of time critical data accesses execute as fast as possible with entries already present in the TLB These entries must be locked to prevent them from being overwritten To setup the MMU follow those steps 1 Reset MMU w...

Page 2682: ...sses when the MMU is disabled 15 4 1 1 Protecting TLB Entries The first n TLB entries with n total number of TLB entries can be protected from being overwritten with new translations This is useful to ensure that certain commonly used or time critical translations are always in the TLB and do not require retrieval via the table walking process The entry protection mechanism is shown in Figure 15 1...

Page 2683: ...rs L1D and second level descriptors L2D Figure 15 19 MMUn Translation Table Hierarchy The first step is to build translation tables first and second level translation tables depending on translation strategy and place them into memory The start address of translation tables must always be aligned according to their size For example a 4096 entry first level translation table must be aligned on a 16...

Page 2684: ...16MB supersection When the page size is smaller 4KB or 64KB second level translation tables are necessary To set up the MMU follow the same steps as in the previous example but write the first and second level descriptors in physical memory The first level translation table describes the translation properties for 1MB sections To describe a 4 GB address range with 1 MB sections 4096 32 bit entries...

Page 2685: ...ex 2nd level table index 1 1 1 1 4 0 0 0 0 2 2 2 2 5 8 12 12 11 11 10 10 10 9 9 9 15 15 15 16 16 16 First level descriptor address Second level descriptor address First level descriptor Second level descriptor Physical address M E ES 16 25 12 8 22 16 MMU 022 Public Version www ti com MMU Basic Programming Model Figure 15 22 Translation of a Large Page Included in a Page Table 2685 SWPU177N Decembe...

Page 2686: ...dex 2nd level table index 1 1 1 1 4 0 0 0 0 2 2 2 2 5 8 12 12 12 11 11 11 10 10 10 9 9 9 First level descriptor address Second level descriptor address First level descriptor Second level descriptor Physical address M E ES 12 25 12 8 22 20 MMU 023 Public Version MMU Basic Programming Model www ti com Figure 15 23 Translation of an Extended Small Page Included in a Page Table 2686 Memory Management...

Page 2687: ...ata accesses Data access of 16 bits and 8 bits are not allowed and can corrupt register content Table 15 9 MMU Register Summary Register Name Type Register Address Offset MMU1 Camera MMU MMU2 IVA2 2 MMU Width Bits Physical Address Physical Address MMU_REVISION R 32 0x00 0x480B D400 0x5D00 0000 MMU_SYSCONFIG RW 32 0x10 0x480B D410 0x5D00 0010 MMU_SYSSTATUS R 32 0x14 0x480B D414 0x5D00 0014 MMU_IRQS...

Page 2688: ...ins the various parameters of the interconnect interface Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Reserved AUTOIDLE IDLEMODE SOFTRESET CLOCK ACTIVITY Bits Field Name Description Type Reset 31 10 Reserved Reads return 0 Write 0s for future compatibility R 0x000000 9 8 CLOCKACTIVITY Clock activity during wake up mode R 0x0 Read 0...

Page 2689: ...mary 8 Table 15 14 MMU_SYSSTATUS Address Offset 0x014 Physical address 0x480B D414 Instance MMU1 Camera ISP MMU 0x5D00 0014 MMU2 IVA2 2 MMU Description This register provides status information about the module excluding the interrupt status information Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved RESETDONE Bits Field Name Descripti...

Page 2690: ...Read 0x0 TableWalkFault false Write 0x0 TableWalkFault status bit unchanged Read 0x1 TableWalkFault is true pending Write 0x1 TableWalkFault status bit is reset 2 EMUMISS Unrecoverable TLB miss during debug hardware TWL disabled RW 0 Read 0x0 EMUMiss false Write 0x0 EMUMiss status bit unchanged Read 0x1 EMUMiss is true pending Write 0x1 EMUMiss status bit is reset 1 TRANSLATION Invalid descriptor ...

Page 2691: ...tiHitFault interrupt is masked 0x1 MultiHitFault event generates an interrupt if occurs 3 TABLEWALKFAULT Error response received during a table walk RW 0 0x0 TableWalkFault interrupt is masked 0x0 TableWalkFault event generates an interrupt if occurs 2 EMUMISS Unrecoverable TLB miss during debug hardware TWL disabled RW 0 0x0 EMUMiss interrupt is masked 0x1 EMUMiss event generates an interrupt if ...

Page 2692: ... Address Offset 0x044 Physical address 0x480B D444 Instance MMU1 Camera ISP MMU 0x5D00 0044 MMU2 IVA2 2 MMU Description This register programs the MMU features Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved TWLENABLE MMUENABLE EMUTLBUPDATE Bits Field Name Description Type Reset 31 4 Reserved Reads return 0 Write 0s for future compati...

Page 2693: ...ary for Register MMU_FAULT_AD MMU Integration Interrupts 0 MMU Functional Description MMU Error Handling 1 Basic Programming Model Writing TLB entries statically 2 MMU Register Manual Register Mapping Summary 3 Table 15 26 MMU_TTB Address Offset 0x04C Physical address 0x480B D44C Instance MMU1 Camera ISP MMU 0x5D00 004C MMU2 IVA2 2 MMU Description This register contains the resolution table base a...

Page 2694: ... is a 3 bit field ie bits 7 and 8 are reserved Write value TLB entry to be updated by software or TLB entry to be read Read value TLB entry to be updated by table walk logic 3 0 Reserved Reads return 0 Write 0s for future compatibility R 0x0 Table 15 29 Register Call Summary for Register MMU_LOCK Basic Programming Model Writing TLB entries statically 0 1 2 Protecting TLB Entries 3 4 Reading TLB En...

Page 2695: ...Field Name Description Type Reset 31 12 VATAG Virtual address tag RW 0x00000 11 4 Reserved Reads return 0 Write 0s for future compatibility R 0x00 3 P Preserved bit RW 0 0x0 TLB entry can be flushed 0x1 TLB entry is protected against flush 2 V Valid bit RW 0 0x0 TLB entry is invalid 0x1 TLB entry is valid 1 0 PAGESIZE Page size RW 0x0 0x0 Section 1MB 0x1 Large page 64KB 0x2 Small page 4KB 0x3 Supe...

Page 2696: ...little endian 8 7 ELEMENTSIZE Element size of the page 8 16 32 no translation RW 0x0 0x0 8 bits 0x1 16 bits 0x2 32 bits 0x3 No translation 6 MIXED Mixed page attribute use CPU element size RW 0 0x0 Use TLB element size 0x1 Use CPU element size 5 0 Reserved Reads return 0 Write 0s for future compatibility R 0x00 Table 15 35 Register Call Summary for Register MMU_RAM MMU Functional Description TLB E...

Page 2697: ...80B D464 Instance MMU1 Camera ISP MMU 0x5D00 0064 MMU2 IVA2 2 MMU Description This register flushes the entry pointed to by the CAM virtual address Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FLUSHENTRY Bits Field Name Description Type Reset 31 1 Reserved Reads return 0 Write 0s for future compatibility RW 0x00000000 0 FLUSHENTRY Flush the...

Page 2698: ...R 0 0x0 TLB entry is invalid 0x1 TLB entry is valid 1 0 PAGESIZE Page size R 0x0 0x0 Section 1MB 0x1 Large page 64KB 0x2 Small page 4KB 0x3 Supersection 16MB Table 15 41 Register Call Summary for Register MMU_READ_CAM Basic Programming Model Reading TLB Entries 0 MMU Register Manual Register Mapping Summary 1 Table 15 42 MMU_READ_RAM Address Offset 0x06C Physical address 0x480B D46C Instance MMU1 ...

Page 2699: ...MMU_READ_RAM Basic Programming Model Reading TLB Entries 0 MMU Register Manual Register Mapping Summary 1 Table 15 44 MMU_EMU_FAULT_AD Address Offset 0x070 Physical address 0x480B D470 Instance MMU1 Camera ISP MMU 0x5D00 0070 MMU2 IVA2 2 MMU Description This register contains the last virtual address of a fault caused by the debugger Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 2701: ...ers Overview 2702 16 2 General Purpose Timers 2703 16 3 General Purpose Timers Register Manual 2724 16 4 Watchdog Timers 2746 16 5 Watchdog Timer Register Manual 2755 16 6 32 kHz Synchronized Timer 2763 16 7 32 kHz Sync Timer Register Manual 2765 2701 SWPU177N December 2009 Revised November 2010 Timers Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2702: ...zed timer Figure 16 1 shows the counters in the device in a high level block diagram Figure 16 1 Timers The 2 WDTs are clocked with 32 kHz clocks The 32 kHz synchronized timer which is reset only at power up provides the operating system with a stable timing source that stores the relative time since the last power cycle of the product Finally 11 GP timers which are useful simply as basic timers a...

Page 2703: ...ck The selection of the clock source is made at the power reset clock management PRCM module level For more information see Section 16 2 3 1 Clocking Reset and Power Management Scheme GPTIMER1 has its GPT1_EVENT_CAPTURE pin tied to the 32 kHz clock and can be used to gauge the system clock input it detects its frequency among 12 13 16 8 19 2 26 or 38 4 MHz Each timer can provide an interrupt to th...

Page 2704: ...timers can send or receive stimulus to from the external off chip system In the device however only GPTIMER8 through GPTIMER11 are configured to output a PWM pulse or receive an external event signal used as a trigger to capture the current timer count GPTIMER1 is also configured to receive an event trigger input GPT1_EVENT_CAPTURE tied to the internal 32 kHz clock This event signal gauges the sys...

Page 2705: ...Output Description Pin Name Type 1 Reset Value Signal Name Description gpt8_pwm_evt I O 0 GPT8_EVENT_CAPTURE GPTIMER8 trigger input GPT8_PWM_OUT PWM output gpt9_pwm_evt I O 0 GPT9_EVENT_CAPTURE GPTIMER9 trigger input GPT9_PWM_OUT PWM output gpt10_pwm_evt I O 0 GPT10_EVENT_CAPTURE GPTIMER10 trigger input GPT10_PWM_OUT PWM output gpt11_pwm_evt I O 0 GPT11_EVENT_CAPTURE GPTIMER11 trigger input GPT11_...

Page 2706: ...RQ GPT10_FCLK L4 I F GPT10_EVENT_CAPTURE GPT10_PWM_OUT GPT10_IRQ GPT11_FCLK L4 I F GPT11_EVENT_CAPTURE GPT11_PWM_OUT GPT11_IRQ gpt8_pwm_evt 2 CM_CLKSEL_CORE sys_32k Public Version General Purpose Timers www ti com 16 2 3 GP Timers Integration Figure 16 4 shows the GP timer integration in the device Figure 16 4 GP Timer Integration 16 2 3 1 Clocking Reset and Power Management Scheme 16 2 3 1 1 Cloc...

Page 2707: ...EL_GPT11 From a global system power management perspective when one or both of the GP timer clocks is no longer required the GP timers can be deactivated at the PRCM level in the corresponding registers Table 16 4 lists the GP timer PRCM clock control bits Table 16 4 GP Timer PRCM Clock Control Bits Name Associated PRCM Clock Enable Bit Autoidle Bit Output GPT1_FCLK GPT1_FCLK PRCM CM_FCLKEN_WKUP 0...

Page 2708: ... IDLE request is configurable through the GPTi TIOCP_CFG 4 3 IDLEMODE bit Table 16 5 lists the IDLEMODE settings and the related acknowledgement modes Table 16 5 IDLEMODE Settings IDLEMODE Value Selected Mode Description The GP timer acknowledges unconditionally the IDLE request from the PRCM module regardless of its internal operations This mode 00 Force idle must be used carefully because it doe...

Page 2709: ...tially acknowledge the GP timer enters into the IDLE request without sleep mode and if a checking the internal 11 pending interrupt event functionalities linked to is finished during idle its clocks mode the wake up signal is asserted The wake up signal is enabled CAUTION The PRCM module does not have any hardware means to read the CLOCKACTIVITY settings The software must ensure consistent program...

Page 2710: ... the PRCM module For further details about the WKUP power domain implementation and the WKUP_RST signal see Chapter 3 Power Reset and Clock Management GPTIMER2 through GPTIMER9 belong to the PER power domain As part of that domain these GP timers are sensitive to a PER_RST signal issued by the PRCM module For further details about the PER power domain implementation and the PER_RST signal see Chap...

Page 2711: ...MPU IVA2_IRQ 8 GPTIMER7 interrupt to IVA2 2 MD_IRQ_7 GPTIMER7 interrupt to modem subsystem D2D GPTIMER8 GPT8_IRQ M_IRQ_44 GPTIMER8 interrupt to MPU IVA2_IRQ 9 GPTIMER8 interrupt to IVA2 2 MD_IRQ_8 GPTIMER8 interrupt to modem subsystem D2D GPTIMER9 GPT9_IRQ M_IRQ_45 GPTIMER9 interrupt to MPU MD_IRQ_9 GPTIMER9 interrupt to modem subsystem D2D GPTIMER10 GPT10_IRQ M_IRQ_46 GPTIMER10 interrupt to MPU G...

Page 2712: ...terrupt line and one wake up line Each internal interrupt source can be independently enabled disabled with a dedicated bit of the GPTi TIER register for the interrupt features and a dedicated bit of the GPTi TWER register for the wakeup In addition GPTIMER1 GPTIMER2 and GPTIMER10 have implemented a mechanism to generate an accurate tick interrupt For each GP timer implemented in the device there ...

Page 2713: ...tion logic Prescaler GPTi TIER GPTi TWER GPTi TISR Pulse PWM logic PWM_OUT Interrupt logic Wake up logic TIMER_INTERRUPT GPTi_SWAKEUP CLK_TIMER General purpose timer L4 interface Public Version www ti com General Purpose Timers Figure 16 6 Block Diagram of GPTIMER3 through GPTIMER9 and GPTIMER11 2713 SWPU177N December 2009 Revised November 2010 Timers Copyright 2009 2010 Texas Instruments Incorpor...

Page 2714: ...pped or on the fly while counting GPTn TCRR can be loaded directly by a GPTi TCRR write access with a new timer value The GPTi TCRR register can also be loaded with the value held in the timer load register GPTi TLDR by a trigger register GPTi TTGR write access The GPTi TCRR loading is done regardless of the GPTi TTGR written value The timer counter register GPTi TCRR value can be read when stoppe...

Page 2715: ...16 2 4 2 1 1 ms Tick Generation Only GPTIMER1 GPTIMER2 and GPTIMER10 Because the timer input clock is 32 768 Hz the interrupt period is not exactly 1 ms If the clock counts up to 32 it obtains a 0 977 ms period if it counts up to 33 it obtains a 1 007 ms period For large granularity the error is cumulative and can generate important deviations to the standard value To minimize the error between a ...

Page 2716: ...LDR 31 0 LOAD_VALUE bit field period less than 1 ms or the value of GPTi TLDR 31 0 LOAD_VALUE 1 period greater than 1 ms Table 16 8 lists the value loaded in the GPTi TCRR register according to the sign of the result of Add1 Add2 and Add3 MSB 0 Positive value MSB 1 Negative value Table 16 8 Value Loaded in GPTi TCRR to Generate 1 ms Tick Add1 MSB Add2 MSB Add3 MSB Value of GPTi TCRR Register 0 0 0...

Page 2717: ...field to trigger the timer counter capture The module sets the GPTi TISR 2 TCAR_IT_FLAG bit when an active edge is detected and at the same time the counter value GPTi TCRR is stored in timer capture register GPTi TCAR1 or GPTi TCAR2 as follows If the GPTi TCLR 13 CAPT_MODE bit is 0 then on the first enabled capture event the value of the counter register is saved in the GPTi TCAR1 register and al...

Page 2718: ...le for GPTi TCLR 13 CAPT_MODE 0 In Figure 16 11 the GPTi TCLR 9 8 TCM value is 0b01 and GPTi TCLR 13 CAPT_MODE is 1 Only the rising edge of EVENT_CAPTURE triggers a capture in the GPTi TCAR1 register on the first enabled event and the GPTi TCAR2 register updates on the second enabled event Figure 16 11 Capture Wave Example for GPTi TCLR 13 CAPT_MODE 1 16 2 4 4 Compare Mode Functionality When the c...

Page 2719: ...low event If a match event occurs first it will not toggle the PWM line Figure 16 13 illustrates those The GPTi TCLR 7 SCPWM bit can be programmed to set or clear the timer PWM output signal only while the counter is stopped or the trigger is off This allows setting the output pin to a known state before modulation starts Modulation synchronously stops when the GPTi TCLR 11 10 TRG field is cleared...

Page 2720: ...ose Timers www ti com Figure 16 12 Timing Diagram of PWM With GPTi TCLR 7 SCPWM Bit 0 Figure 16 13 Timing Diagram of PWM With GPTi TCLR 7 SCPWM Bit 1 16 2 4 7 Timer Counting Rate The timer rate is defined by the following values Value of the prescaler fields GPTi TCLR 5 PRE bit and GPTi TCLR 4 2 PTV field Value loaded into the timer load register GPTi TLDR Table 16 10 lists prescaler clock ratio v...

Page 2721: ...with a timer clock input of 32 kHz and a GPTn TCLR 5 PRE field equal to 0 the timer output period is as listed in Table 16 11 Table 16 11 Value and Corresponding Interrupt Period GPTi TLDR 31 0 LOAD_VALUE Interrupt Period 0x0000 0000 39 h 0xFFFF 0000 2 1 s 0xFFFF FFF0 524 ms 0xFFFF FFFE 65 5 ms 16 2 5 Timer Under Emulation During emulation mode the timer continues to run according to the value of ...

Page 2722: ...RR GPTi TLDR GPTi TTGR GPTi TMAR and GPTi TPIR GPTi TNIR GPTi TCVR GPTi TOCR and GPTi TOWR for GPTIMER1 GPTIMER2 and GPTIMER10 Therefore the write transaction is immediately acknowledged on the L4 interface although the effective write operation occurs later because of a resynchronization in the timer clock domain The advantage is that neither the interconnect nor the device that requested the wri...

Page 2723: ...tion and the same stall period applies A register read following a write to the same register is always coherent This mode is functional regardless of the ratio between the L4 interface frequency and the timer clock frequency 16 2 6 2 Reading From Timer Counter Registers In 16 bit access mode reading the 16 LSBs from the timer counter registers GPTi TCRR GPTi TCAR1 and GPTi TCAR2 captures the curr...

Page 2724: ...MER5 0x4903 8000 4K bytes GPTIMER6 0x4903 A000 4K bytes GPTIMER7 0x4903 C000 4K bytes GPTIMER8 0x4903 E000 4K bytes GPTIMER9 0x4904 0000 4K bytes GPTIMER10 0x4808 6000 4K bytes GPTIMER11 0x4808 8000 4K bytes 16 3 2 GP Timer Register Mapping Summary CAUTION The GP timer registers are limited to 32 bit and 16 bit data accesses 8 bit access is not allowed and can corrupt the register content Table 16...

Page 2725: ...24 0x4831 8024 0x4903 2024 0x4903 4024 0x4903 6024 TCRR RW 32 0x028 0x4831 8028 0x4903 2028 0x4903 4028 0x4903 6028 TLDR RW 32 0x02C 0x4831 802C 0x4903 202C 0x4903 402C 0x4903 602C TTGR RW 32 0x030 0x4831 8030 0x4903 2030 0x4903 4030 0x4903 6030 TWPS R 32 0x034 0x4831 8034 0x4903 2034 0x4903 4034 0x4903 6034 TMAR RW 32 0x038 0x4831 8038 0x4903 2038 0x4903 4038 0x4903 6038 TCAR1 R 32 0x03C 0x4831 8...

Page 2726: ...0x4903 C01C 0x4903 E01C TWER RW 32 0x020 0x4903 8020 0x4903 A020 0x4903 C020 0x4903 E020 TCLR RW 32 0x024 0x4903 8024 0x4903 A024 0x4903 C024 0x4903 E024 TCRR RW 32 0x028 0x4903 8028 0x4903 A028 0x4903 C028 0x4903 E028 TLDR RW 32 0x02C 0x4903 802C 0x4903 A02C 0x4903 C02C 0x4903 E02C TTGR RW 32 0x030 0x4903 8030 0x4903 A030 0x4903 C030 0x4903 E030 TWPS R 32 0x034 0x4903 8034 0x4903 A034 0x4903 C034...

Page 2727: ...0x4808 8038 TCAR1 R 32 0x03C 0x4904 003C 0x4808 603C 0x4808 803C TSICR RW 32 0x040 0x4904 0040 0x4808 6040 0x4808 8040 TCAR2 R 32 0x044 0x4904 0044 0x4808 6044 0x4808 8044 TPIR RW 32 0x048 0x4808 6048 TNIR RW 32 0x04C 0x4808 604C TCVR RW 32 0x050 0x4808 6050 TOCR RW 32 0x054 0x4808 6054 TOWR RW 32 0x058 0x4808 6058 16 3 3 GP Timer Register Descriptions Table 16 16 through Table 16 54 describe the ...

Page 2728: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved EMUFREE AUTOIDLE IDLEMODE SOFTRESET ENAWAKEUP CLOCKACTIVITY Bits Field Name DESCRIPTION Type Reset 31 10 Reserved Write 0s for future compatibility Reads return 0 R 0x0000000 9 8 CLOCKACTIVITY Clock activity during wakeup mode period RW 0x0 0x0 L4 interface and Functional clocks can be switched off 0x1 L4 interface clock is maintained during ...

Page 2729: ... clock is free running 0x1 Automatic L4 interface clock gating strategy is applied based on the L4 interface activity Table 16 19 Register Call Summary for Register TIOCP_CFG General Purpose Timers Clock Management 0 1 2 Wake Up Capability 3 4 Software Reset 5 6 Timer Under Emulation 7 8 9 Accessing GP Timer Registers 10 Writing to Timer Registers 11 General Purpose Timers Register Manual GP Timer...

Page 2730: ...Address 0x4831 8018 Instance GPT1 0x4903 2018 GPT2 0x4903 4018 GPT3 0x4903 6018 GPT4 0x4903 8018 GPT5 0x4903 A018 GPT6 0x4903 C018 GPT7 0x4903 E018 GPT8 0x4904 0018 GPT9 0x4808 6018 GPT10 0x4808 8018 GPT11 Description This register shows which interrupt events are pending inside the module Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OVF_IT...

Page 2731: ...g GP Timer Registers 7 Writing to Timer Registers 8 General Purpose Timers Register Manual GP Timer Register Mapping Summary 9 10 11 Table 16 24 TIER Address Offset 0x01C Physical Address 0x4831 801C Instance GPT1 0x4903 201C GPT2 0x4903 401C GPT3 0x4903 601C GPT4 0x4903 801C GPT5 0x4903 A01C GPT6 0x4903 C01C GPT7 0x4903 E01C GPT8 0x4904 001C GPT9 0x4808 601C GPT10 0x4808 801C GPT11 Description Th...

Page 2732: ...7 8 9 Table 16 26 TWER Address Offset 0x020 Physical Address 0x4831 8020 Instance GPT1 0x4903 2020 GPT2 0x4903 4020 GPT3 0x4903 6020 GPT4 0x4903 8020 GPT5 0x4903 A020 GPT6 0x4903 C020 GPT7 0x4903 E020 GPT8 0x4904 0020 GPT9 0x4808 6020 GPT10 0x4808 8020 GPT11 Description This register controls enable disable the wake up feature on specific interrupt events Type RW 31 30 29 28 27 26 25 24 23 22 21 2...

Page 2733: ...08 6024 GPT10 0x4808 8024 GPT11 Description This register controls optional features specific to the timer functionality Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRG TCM PTV PT ST CE AR PRE SCPWM GPO_CFG CAPT_MODE Bits Field Name Description Type Reset 31 15 Reserved Reads return 0 R 0x00000 14 GPO_CFG PWM output event detection input p...

Page 2734: ...r enabled 4 2 PTV Trigger output mode 0x0 The timer counter is prescaled with the value RW 0x0 2 PTV 1 Example PTV 3 counter increases value if started after 16 functional clock periods 1 AR Autoreload mode RW 0 0x0 One shot mode overflow 0x1 Autoreload mode overflow 0 ST Start stop timer control RW 0 0x0 Stop the timer 0x1 Start the timer Table 16 29 Register Call Summary for Register TCLR Genera...

Page 2735: ...R_COUNTER The value of the timer counter register RW 0x00000000 Table 16 31 Register Call Summary for Register TCRR General Purpose Timers Wake Up Capability 0 1 Timer Mode Functionality 2 3 4 5 6 7 8 9 10 1 ms Tick Generation Only GPTIMER1 GPTIMER2 and GPTIMER10 11 12 13 Capture Mode Functionality 14 15 Compare Mode Functionality 16 17 Prescaler Functionality 18 19 Accessing GP Timer Registers 20...

Page 2736: ...Bits Field Name Description Type Reset 31 0 LOAD_VALUE The value of the timer load register RW 0x00000000 Table 16 33 Register Call Summary for Register TLDR General Purpose Timers Timer Mode Functionality 0 1 2 1 ms Tick Generation Only GPTIMER1 GPTIMER2 and GPTIMER10 3 4 5 6 7 8 9 10 11 12 Prescaler Functionality 13 14 Pulse Width Modulation 15 16 17 Timer Counting Rate 18 19 20 21 22 Accessing ...

Page 2737: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTGR_ VALUE Bits Field Name Description Type Reset 31 0 TTGR_ VALUE The value of the trigger register During reads it RW 0xFFFFFFFF always returns 0xFFFFFFFF Table 16 35 Register Call Summary for Register TTGR General Purpose Timers Timer Mode Functionality 0 1 Prescaler Functionality 2 Accessing GP Timer Registers 3 Writing to Timer...

Page 2738: ...rns reset value R 0 5 6 7 8 9 11 12 8 W_PEND_TOCR Write pending for register GPT_TOCR R 0 0x0 Overflow counter register write not pending 0x1 Overflow counter register write pending Reserved for instances 3 4 Read returns reset value R 0 5 6 7 8 9 11 12 7 W_PEND_TCVR Write pending for register GPT_TCVR R 0 0x0 Counter value register write not pending 0x1 Counter value register write pending Reserv...

Page 2739: ...ter write pending Table 16 37 Register Call Summary for Register TWPS General Purpose Timers Write Posting Synchronization Mode 0 General Purpose Timers Register Manual GP Timer Register Mapping Summary 1 2 3 Table 16 38 TMAR Address Offset 0x038 Physical Address 0x4831 8038 Instance GPT1 0x4903 2038 GPT2 0x4903 4038 GPT3 0x4903 6038 GPT4 0x4903 8038 GPT5 0x4903 A038 GPT6 0x4903 C038 GPT7 0x4903 E...

Page 2740: ...03 C03C GPT7 0x4903 E03C GPT8 0x4904 003C GPT9 0x4808 603C GPT10 0x4808 803C GPT11 Description This register holds the first captured value of the counter register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPTURE_ VALUE1 Bits Field Name Description Type Reset 31 0 CAPTURE_ VALUE1 The value of first captured counter register R 0x00000000 Table 16 ...

Page 2741: ... Field Name Description Type Reset 31 3 Reserved Reads return 0 R 0x00000000 2 POSTED Posted mode selection RW 1 0x0 Non posted mode selected 0x1 Posted mode selected 1 SFT Reset software functional registers This bit is automatically reset RW 0 by the hardware During reads it always returns 0 0x0 Normal functional mode 0x1 The functional registers are reset 0 Reserved Reads return 0 R 0 Table 16 ...

Page 2742: ...re Mode Functionality 0 1 2 3 4 5 Reading From Timer Counter Registers 6 General Purpose Timers Register Manual GP Timer Register Mapping Summary 7 8 9 GP Timer Register Descriptions 10 Table 16 46 TPIR Address Offset 0x048 Physical Address 0x4831 8048 Instance GPT1 0x4903 2048 GPT2 0x4808 6048 GPT10 Description This register is used for 1 ms tick generation The TPIR register holds the value of th...

Page 2743: ...6 5 4 3 2 1 0 NEGATIVE_INC_VALUE Bits Field Name Description Type Reset 31 0 NEGATIVE_INC_VALUE The value of negative increment RW 0x00000000 Table 16 49 Register Call Summary for Register TNIR General Purpose Timers 1 ms Tick Generation Only GPTIMER1 GPTIMER2 and GPTIMER10 0 1 2 3 4 5 Accessing GP Timer Registers 6 Writing to Timer Registers 7 Write Posting Synchronization Mode 8 General Purpose ...

Page 2744: ... 24 Reserved Reads return 0 RW 0x00 23 0 OVF_COUNTER_VALUE The number of overflow events RW 0x00000000 Table 16 53 Register Call Summary for Register TOCR General Purpose Timers 1 ms Tick Generation Only GPTIMER1 GPTIMER2 and GPTIMER10 0 1 2 3 4 Accessing GP Timer Registers 5 Writing to Timer Registers 6 Write Posting Synchronization Mode 7 General Purpose Timers Register Manual GP Timer Register ...

Page 2745: ...ms Tick Generation Only GPTIMER1 GPTIMER2 and GPTIMER10 0 1 2 Accessing GP Timer Registers 3 Writing to Timer Registers 4 Write Posting Synchronization Mode 5 General Purpose Timers Register Manual GP Timer Register Mapping Summary 6 7 2745 SWPU177N December 2009 Revised November 2010 Timers Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2746: ...M module its interrupt outputs are unused and the IVA2 WDT serves watchdog interrupts to the MPU its reset outputs are unused The WDTs can be accessed loaded and cleared by registers through the L4 interface The MPU and IVA2 WDTs have the 32 kHz clock for their timer clock input The MPU WDT directly generates a warm reset condition on overflow The IVA2 WDT generates an MPU interrupt condition on o...

Page 2747: ...rupt in its hardware integration WDT2 or WDT3 16 4 2 WDT Integration Figure 16 15 shows the integration of the WDT in the device Figure 16 15 WDT Integration 16 4 2 1 Clocking Reset and Power Management Scheme 16 4 2 1 1 Clock Management There are two clock domains in the WDTs Functional clock domain WDTi_FCLK is the WDT functional clock It is used to clock the WDT internal logic Interface clock d...

Page 2748: ...etails about source clocks gating and domain transitions see Chapter 3 Power Reset and Clock Management At the PRCM level when the conditions to shut off the PRCM functional or interface output clocks are met see Chapter 3 Power Reset and Clock Management for details the PRCM automatically launches a hardware handshake protocol to ensure the WDT is ready to have its clocks switched off Namely the ...

Page 2749: ... concerned ON ON None of the clocks are shut down Therefore the WDT 11 can potentially acknowledge the IDLE request without checking the internal functionalities linked to its clocks CAUTION The PRCM module does not have any hardware means to read the CLOCKACTIVITY settings The software must ensure consistent programming between the WDT CLOCKACTIVITY and the PRCM functional clock and interface clo...

Page 2750: ...ly by reading the WDT counter register WDTi WCRR modified by accessing the WDT load register WDTi WLDR no on the fly update or reloaded by following a specific reload sequence on the WDT trigger register WDTi WTGR A start stop sequence applied to the WDT start stop register WDTi WSPR can start and stop the WDT Figure 16 16 32 Bit WDT Functional Block Diagram 16 4 3 2 Reset Context After reset the ...

Page 2751: ... is composed of a prescaler stage and a timer counter The timer rate is defined by the following values Value of the prescaler fields the WDTi WCLR 5 PRE bit and the WDTi WCLR 4 2 PTV field Value loaded into the timer load register WDTi WLDR The prescaler stage is clocked with the timer clock and acts as a clock divider for the timer counter stage The ratio is managed by accessing the ratio defini...

Page 2752: ...rflows Hence the WDTi WLDR 31 0 value must be chosen according to the ongoing activity preceding the watchdog reload Due to design reasons WDTi WLDR 31 0 0xFFFF FFFF is a special case although such a WDTi WLDR value is meaningless When WDTi WLDR is programmed with the overflow value a triggering event generates a reset interrupt one functional clock cycle later even if the WDT is stopped Table 16 ...

Page 2753: ...at the WDTi WCRR value is not read while it is being incremented When 32 bit read access is performed the shadow register is not updated Read access is made directly from the accessed register To ensure that a coherent value is read inside WDTi WCRR the first read access is to the lower 16 bits offset 0x08 followed by read access to the upper 16 bits offset 0x0A 16 4 3 9 WDT Interrupt Generation T...

Page 2754: ... and a reset pulse is still generated when overflow is reached When EMUFREE is 0 the counters prescaler timer are frozen and incrementation restarts after exiting from emulation mode 2754 Timers SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2755: ...WDTIMER2 Register Summary Register Name Type Register Width Address Offset WDTIMER2 Physical Address Bits WIDR R 32 0x000 0x4831 4000 WD_SYSCONFIG RW 32 0x010 0x4831 4010 WD_SYSSTATUS R 32 0x014 0x4831 4014 WISR RW 32 0x018 0x4831 4018 WIER RW 32 0x01C 0x4831 401C WCLR RW 32 0x024 0x4831 4024 WCRR RW 32 0x028 0x4831 4028 WLDR RW 32 0x02C 0x4831 402C WTGR RW 32 0x030 0x4831 4030 WWPS R 32 0x034 0x4...

Page 2756: ...See 1 7 4 Major revision 3 0 Minor revision Examples 0x10 for 1 0 0x21 for 2 1 1 TI internal data Table 16 70 Register Call Summary for Register WIDR Watchdog Timer Register Manual WDT Register Mapping Summary 0 1 Table 16 71 WD_SYSCONFIG Address Offset 0x010 Physical Address 0x4831 4010 Instance WDTIMER2 0x4903 0010 WDTIMER3 Description This register controls the various parameters of the L4 inte...

Page 2757: ...eset by the hardware RW 0 During reads it always return 0 0x0 Normal mode 0x1 The module is reset 0 AUTOIDLE L4 interconnect clock gating strategy RW 0 0x0 L4 interface clock is free running 0x1 Automatic L4 interface clock gating strategy is applied based on the L4 interface activity Table 16 72 Register Call Summary for Register WD_SYSCONFIG Watchdog Timers Clock Management 0 1 WDT Under Emulati...

Page 2758: ... which interrupt events are pending inside the module Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OVF_IT_FLAG Bits Field Name Description Type Reset 31 1 Reserved Reads return 0 R 0x00000000 0 OVF_IT_FLAG Pending overflow interrupt status RW 0 Read 0x0 No overflow interrupt pending Write 0x0 Status unchanged Read 0x1 Overflow interrupt pen...

Page 2759: ...rrupt Generation 1 Watchdog Timer Register Manual WDT Register Mapping Summary 2 3 Table 16 79 WCLR Address Offset 0x024 Physical Address 0x4831 4024 Instance WDTIMER2 0x4903 0024 WDTIMER3 Description This register controls the prescaler stage of the counter Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PTV PRE Reserved Bits Field Name Descr...

Page 2760: ..._COUNTER The value of the timer counter register RW 0x00000000 Table 16 82 Register Call Summary for Register WCRR Watchdog Timers General WDT Operation 0 Overflow Reset Generation 1 Modifying Timer Count Load Values and Prescaler Setting 2 Watchdog Counter Register Access Restriction WDTi WCRR Register 3 4 5 6 Watchdog Timer Register Manual WDT Register Mapping Summary 7 8 WDT Register Descriptio...

Page 2761: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTGR_VALUE Bits Field Name Description Type Reset 31 0 TTGR_VALUE The value of the trigger register RW 0x00000000 Table 16 86 Register Call Summary for Register WTGR Watchdog Timers General WDT Operation 0 Triggering a Timer Reload 1 2 Modifying Timer Count Load Values and Prescaler Setting 3 Watchdog Timer Register Manual WDT Register Mapping Summary 4...

Page 2762: ... Call Summary for Register WWPS Watchdog Timer Register Manual WDT Register Mapping Summary 0 1 Table 16 89 WSPR Address Offset 0x048 Physical Address 0x4831 4048 Instance WDTIMER2 0x4903 0048 WDTIMER3 Description This register holds the start stop value that controls the internal start stop FSM Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSPR_VALU...

Page 2763: ...r The sync counter register is 32 bits wide and for correct count capture must be accessed as 16 bit LSB access first and two 16 bit MSB access last Internal synchronization logic allows reading of the counter value while the counter is running The time latency to read the counter is one L4 interconnect clock period 16 6 1 2 32 kHz Sync Timer Features The following are the main features of the 32 ...

Page 2764: ...ains for 32 kHz Sync Timer Timer Source Clock Intertface Clock Clock and Power Reset Domain Domain 32 kHz sync timer sys_32k 32KSYNC_ICLK WKUP SYNCT_RST 1 16 6 3 2 Interrupts The 32 kHz sync timer has no interrupt outputs 16 6 3 3 Sync Timer 32k and MSuspend Signal By default the Sync Timer 32k is not stopped when the MPU or DSP is in halt To activate its sensitivity to the MSuspend signal the CON...

Page 2765: ...ster Width Bits Offset Address 32 kHz Sync Timer Physical Address REG_32KSYNCNT_REV R 32 0x0000 0x4832 0000 REG_32KSYNCNT_SYSCO R W 32 0x0004 0x4832 0004 NFIG REG_32KSYNCNT_CR R 32 0x0010 0x4832 0010 16 7 3 32 kHz Sync Timer Register Descriptions Table 16 94 REG_32KSYNCNT_REV Address Offset 0x0000 Physical Address 0x4832 0000 Description This register contains the sync counter IP revision code Typ...

Page 2766: ...rved 2 0 Reserved Reads return 0 R 0x0 Table 16 97 Register Call Summary for Register REG_32KSYNCNT_SYSCONFIG 32 kHz Sync Timer Register Manual 32 kHz Sync Timer Register Mapping Summary 0 Table 16 98 REG_32KSYNCNT_CR Address Offset 0x0010 Physical Address 0x4832 0010 Description This register contains the 32 kHz sync counter value Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12...

Page 2767: ...se the multimaster high speed controller 1 2 3 and 4 will be referred and factorized as HS I2Ci Topic Page 17 1 HS I2 C Overview 2768 17 2 HS I2 C Environment 2770 17 3 HS I2 C Integration 2781 17 4 HS I2 C Functional Description 2790 17 5 HS I2 C Basic Programming Model 2798 17 6 HS I2 C Register Manual 2818 2767 SWPU177N December 2009 Revised November 2010 Multimaster High Speed I2 C Controller ...

Page 2768: ...he SCCB is a serial bus developed by Omnivision Technologies Inc to act as a master on a 2 wire SCCB bus Only HS I2C2 and I2C3 can be configured in SCCB mode to act as a master device on a 3 wire SCCB bus The fourth HS I2 C4 controller I2C4 is in the power reset and clock management PRCM module to perform dynamic voltage control and power sequencing For mode details on I2 C4 see Chapter 3 Power Re...

Page 2769: ...access DMA channels Wide interrupt capability Auto Idle mechanism Idle Request Idle Acknowledge handshake mechanism The master transmitter HS I2 C4 controller has the following features Support of HS and fast modes 7 bit addressing mode only Master transmitter mode only Start restart stop NOTE The I2 C4 clock frequency in HS mode is equal to the SYS_CLK clock frequency divided by 15 NOTE Before us...

Page 2770: ...ctions in I2 C Mode Figure 17 3 shows the HS I2 C controllers pins used for typical connections with I2 C devices Figure 17 3 HS I2 C Controller Interface Signals in I2 C Mode 17 2 1 2 HS I2 C Interface Typical Connections Table 17 1 lists the pins associated with the I2 C interface Table 17 1 HS I2 C Input Output Signal I O 1 Description Reset Value i2ci_scl I O OD I2 C serial clock line 2 Open d...

Page 2771: ... HS I2 C Data Validity The data on the serial data line must be stable during the high period of the clock i2ci_scl The high and low states of the data line can change only when the clock signal on the serial clock line is low Figure 17 5 is an example of data validity requirements Figure 17 5 HS I2 C Bit Data Validity Transfer on the I2 C Bus 17 2 1 3 3 HS I2 C Start and Stop Conditions The HS I2...

Page 2772: ...hows the I2 C data transfer format in F S mode Figure 17 7 HS I2 C Data Transfer Formats in F S Mode The first word after an S condition consists of 8 bits In acknowledge mode an extra dedicated acknowledgment bit is inserted after each byte In addressing formats with 7 bit addresses the first byte is composed of 7 MSB slave address bits and 1 least significant bit LSB R W_ bit The LSB R W_ bit of...

Page 2773: ... master transmitter mode With any of the address formats a b or c see Figure 17 7 if the R W_ bit is high the module enters master receiver mode after the slave address byte and bit R W_ are transmitted Serial data bits received on bus line i2ci_sda are shifted in synchronization with the self generated clock pulses on i2ci_scl When the intervention of the processor is required the I2Ci I2C_STAT 1...

Page 2774: ...are two or more master devices and the clock must be synchronized so that the data output can be compared The wired AND property of the clock line means that the device that first generates a low period of the clock line overrules the other devices At this high low transition the clock generators of the other devices are forced to start generating their own low periods The clock line is then held ...

Page 2775: ... HS I2 C controllers support the 2 wire SCCB protocol in master mode Only I2C2 and I2C3 support the 3 wire SCCB protocol in master mode Figure 17 11 shows the HS I2 C controllers and their related connections with 3 wire or 2 wire SCCB compliant devices Figure 17 11 HS I2 C Controllers and Typical Connections to SCCB Devices NOTE Only one 2 wire SCCB slave device can be connected to the 2 wire SCC...

Page 2776: ...ternal conflict protection resistor for each slave device connected to the bus i2ci_sccbe 3 O SCCB enable line Standard CMOS output buffer High High 1 I Input O Output OD Open Drain Hi Z High Impedance 2 This output signal is also used as retiming input 3 This signal is used for the 3 wire SCCB protocol only NOTE Because they share the same ball the i2c2_sccbe and i2c3_sccbe signals are not availa...

Page 2777: ... the timing diagram of the 3 wire SCCB data transmission Figure 17 13 HS I2 C 3 Wire SCCB Transmission Timing Diagram NOTE When operating in 2 wire SCCB mode the i2ci_sccbe signal is not used by the 2 wire SCCB compliant slave device attached to the 2 wire SCCB bus 17 2 2 3 2 HS I2 C SCCB Transmission Data Formats Figure 17 14 describes the data format of the three kinds of transmission Figure 17 ...

Page 2778: ...f the current cycle A logical 0 represents a write cycle and a logical 1 represents a read cycle The ninth bit of phase 1 is a don t care bit X bit Phase 2 subaddress read data is asserted by the master subaddress or the slave s read data A phase 2 transmission asserted by the master identifies the subaddress of the slave s the master intends to access A phase 2 transmission asserted by the slave ...

Page 2779: ...ter only high speed Figure 17 16 HS I2 C Interface Signals for I2 C4 17 2 3 2 HS I2 C Interface Typical Connections for I2C4 Table 17 3 lists the pins associated with the I2 C interface of the HS I2 C controller I2C4 of the device Table 17 3 HS I2 C Input Output Description for I2C4 Signal I O 1 Description Reset Value i2c4_scl I O OD I2 C serial clock line 2 Open drain output buffer Requires exte...

Page 2780: ... 3 1 HS I2 C Serial Data Format 17 2 3 3 2 HS I2 C Data Validity for I2C4 The data validity is the same as described in Section 17 2 1 3 2 HS I2 C Data Validity 17 2 3 3 3 HS I2 C Start and Stop Conditions for I2C4 The S and P conditions are the same as described in Section 17 2 1 3 3 HS I2 C Start and Stop Conditions 17 2 3 3 4 HS I2 C Addressing for I2C4 The master transmitter HS I2 C controller...

Page 2781: ...S mode HS mode Or HS mode continues Master to slave F S mode Master to slave W 1 Public Version www ti com HS I2 C Integration Figure 17 18 HS I2 C Data Transfer Format in HS Mode for I2C4 17 3 HS I2 C Integration Figure 17 19 shows the integration of the four HS I2 C controllers in the device 2781 SWPU177N December 2009 Revised November 2010 Multimaster High Speed I2 C Controller Copyright 2009 2...

Page 2782: ...2 C Integration www ti com Figure 17 19 HS I2 C Controller Integration Diagram 17 3 1 HS I2 C Clocking Reset and Power Management Scheme 17 3 1 1 HS I2 C Clocks 17 3 1 1 1 HS I2 C Module Clocks Each HS I2 C controller is clocked with an independent functional clock of 96 MHz I2Ci_FCLK and an interface clock I2Ci_ICLK for interfacing with the L4 Core interconnect These clocks are provided by the PR...

Page 2783: ...vity is detected on the L4 Core interface automatic idle mode is enabled and the interface clock I2Ci_ICLK is disabled internally to the module thus reducing power consumption When new activity is detected on the L4 Core interconnect interface of the module the clock restarts with no latency penalty After reset automatic idle mode is disabled thus this mode must be enabled by software for reduced ...

Page 2784: ...3 The I2Ci I2C_SYSC 9 8 CLOCKACTIVITY bit field indicates the state of the interface and functional clocks of the module when in idle mode Table 17 5 lists the value of the I2Ci I2C_SYSC 9 8 CLOCKACTIVITY bit field and indicates the state of the interface and functional clocks at the PRCM clock generator output in idle mode Table 17 5 HS I2 C State of the Interface and Functional Clocks When the M...

Page 2785: ...ntegration The wake up request is composed of the merge of all wake up events Each wake up event can be separately enabled or disabled by setting the corresponding bit in the I2Ci I2C_WE register The global wake up capability of the module can be enabled or disabled by setting the I2Ci I2C_SYSC 2 ENAWAKEUP bit 1 enabled 0 disabled Figure 17 20 shows the wake up generation flow Figure 17 20 HS I2 C...

Page 2786: ...E The TXFIFO level is below the threshold I2Ci I2C_BUF 5 0 mode only XTRSH bit field value 1 and the amount of data left to be transferred is less than this threshold This allows the module to inform the LH that it can check the amount of data to be written to the TX FIFO 2 Wake up event asynchronously detected 3 This event must not be enabled if the functional clock cannot be disabled NOTE With t...

Page 2787: ...ta in the I2C1 I2C_DATA 7 0 register I2C1_DMA_RX I2C1 S_DMA_27 I2C1 DMA read request to inform the sDMA to read the data in the I2C1 I2C_DATA 7 0 register I2C2_DMA_TX I2C2 S_DMA_28 I2C2 DMA write request to inform the sDMA to write new data in the I2C2 I2C_DATA 7 0 register I2C2_DMA_RX I2C2 S_DMA_29 I2C2 DMA read request to inform the sDMA to read the data in the I2C2 I2C_DATA 7 0 register I2C3_DM...

Page 2788: ...STAT 3 I2Ci I2C_IE 3 The RX FIFO level is above the threshold event mode and RRDY RRDY_IE I2Ci I2C_BUF 13 8 RTRSH bit field value 1 SCCB read mode XRDY I2 C transmit I2Ci I2C_STAT 4 I2Ci I2C_IE 4 The module requires new data to be served A master event mode and XRDY XRDY_IE transmitter module requests new data when the TX FIFO SCCB write level is below the threshold I2Ci I2C_BUF 5 0 XTRSH bit mode...

Page 2789: ...n overrun event on the event receive mode ROVR ROVR_IE receiving line RDR I2 C receive I2Ci I2C_STAT 13 I2Ci I2C_IE 13 The module is configured as a receiver a stop P event mode only RDR RDR_IE condition was received on the I2 C bus and the RX FIFO level is below the threshold I2Ci I2C_BUF 13 8 RTRSH bit field value 1 XDR I2 C master I2Ci I2C_STAT 14 I2Ci I2C_IE 14 The module is configured as a ma...

Page 2790: ...The operation mode is selected by configuring the I2Ci I2C_CON 13 12 OPMODE bit field Table 17 10 lists the available operation modes Table 17 10 HS I2 C Operation Mode Selection Operation Mode I2Ci I2C_CON 13 12 OPMODE Bit Field Value F S I2 C 0x0 HS I2 C 0x1 SCCB 0x2 Reserved not used 0x3 17 4 2 HS I2 C Transmit Mode in I2 C Mode This mode is available for master or slave The master and slave mo...

Page 2791: ...r implements two internal 8 bit FIFOs the RX and TX FIFOs The FIFOs are fully configurable controllable to deliver their carried signals to the targeted sink with maximum signal integrity Configuration of the buffers is done by groups assignment and not individually per pad each group is assigned a specific prg_xxx register inside the System Control Module Refer to Chapter 13 System Control Module...

Page 2792: ...generated In receive mode an RRDY interrupt is generated as soon as the FIFO reaches its receive threshold the I2Ci I2C_BUF 13 8 RTRSH bitfield value 1 The interrupt can be deasserted only when the LH has handled enough bytes to make the number of bytes in the RX FIFO lower than the programmed threshold For each interrupt the LH can be configured to read a number of bytes equal to the value of the...

Page 2793: ...e must not be used because the transfer length is not known at configuration time and the external master can end the transfer at any point by not acknowledging 1 data byte If the draining feature is used in slave transmit mode data can remain in the TX FIFO without being transmitted over the I2 C bus In this case the TX FIFO must be cleared by setting the I2Ci I2C_BUF 6 TXFIFO_CLR bit 17 4 4 2 HS...

Page 2794: ...Figure 17 26 HS I2 C Transmit FIFO Request Generation Low Threshold NOTE In SCCB mode the RX and TX threshold values must be set to 1 by setting the I2Ci I2C_BUF 13 8 RTRSH and I2Ci I2C_BUF 5 0 XTRSH bitfields to 0x0 17 4 4 4 HS I2 C Draining Feature I2 C Mode Only The draining feature is implemented to handle the end of a transfer whose length is not a multiple of the FIFO threshold values the I2...

Page 2795: ...last bytes to the FIFO In master mode the LH can alternately skip the checking of the value of the I2Ci I2C_BUFSTAT 5 0 TXSTAT and I2Ci I2C_BUFSTAT 13 8 RXSTAT bitfields because it can obtain this information internally by computing the value of the I2Ci I2C_CNT 15 0 DATACOUNT bitfield modulo I2Ci I2C_BUF 13 8 RTRSH or I2Ci I2C_BUF 5 0 XTRSH By default the draining feature is disabled it can be en...

Page 2796: ... not generate the I2 C clock Table 17 12 HS I2 C tLOW and thighValues of the I2 C Clock Mode I2Ci_INTERNAL_CLK tLOW thigh F S SCCB or HS I2Ci_FCLK I2Ci I2C_SCLL 7 0 SCLL I2Ci I2C_SCLH 7 0 first phase I2Ci I2C_PSC 7 0 PSC bitfield bitfield value 7 x SCLH bitfield value 5 x 1 I2Ci_INTERNAL_CLK I2Ci_INTERNAL_CLK period period HS second phase I2Ci_FCLK I2Ci I2C_SCLL 15 8 I2Ci I2C_SCLH 15 8 HSSCLL bitf...

Page 2797: ...st mode the I2Ci_SYSTEST 13 12 TMODE bit field selects the type of test Table 17 14 lists the tests available for the HS I2 C controllers Table 17 13 HS I2 C List of tests for the HS I2 C Controllers I2Ci I2C_SYSTEST 13 12 Test Description TMODE Bit Field Value b00 Functional mode Normal operation mode b01 Reserved not used b10 Test of i2ci_scl serial The i2ci_scl line is driven with a permanent c...

Page 2798: ...ing the I2Ci I2C_CON 9 TRX bit to 0 The external device slave address 7 bit address of the ID value is set in the I2Ci I2C_SA register the register address 8 bit subaddress in the external SCCB device is set in the I2Ci I2C_OA register The 8 bit data received from the external SCCB device is read by the LH from the I2Ci I2C_DATA register NOTE In SCCB mode the RX and TX thresholds must be set to 1 ...

Page 2799: ... four Own Addresses can be programmed in the I2Ci I2C_OAi registers where i 0 1 2 3 for each I2 C controller NOTE For a 10 bit address set the corresponding expand Own Address bit in the I2Ci I2C_CON register 7 Set the TX threshold in transmitter mode and the RX threshold in receiver mode by setting the I2Ci I2C_BUF 5 0 XTRSH field to TX threshold 1 and the I2Ci I2C_BUF 13 8 RTRSH bit field to RX ...

Page 2800: ...l to low to prevent other bytes from being received The I2Ci I2C_STAT 7 AERR bit is set to 1 when a read access is performed in the I2Ci I2C_DATA register while the RX FIFO is empty The corresponding interrupt can be enabled by setting the I2Ci I2C_IE 7 AERR_IE bit to 1 17 5 1 1 6 HS I2 C Transmit Data I2 C Mode Poll the I2Ci I2C_STAT 4 XRDY bit or use the XRDY interrupt the I2Ci I2C_IE 4 XRDY_IE ...

Page 2801: ...ve accordingly 6 Test for general call the I2Ci I2C_STAT 5 GC status bit and resolve accordingly 7 Test for start S condition the I2Ci I2C_STAT 6 STC status bit and resolve accordingly For this test the functional clock must be inactive 8 Test for access error the I2Ci I2C_STAT 7 AERR status bit and resolve accordingly 9 Test for bus free the I2Ci I2C_STAT 8 BF status bit and resolve accordingly 1...

Page 2802: ...2C_IE register i enable interrupts Write I2C I2C_BUF register i for DMA usage Set CONTROL CONTROL_PROG_IO1 19 PRG_I2C1_PULLUPRESX for I2C1 or Set CONTROL CONTROL_ 0 PROG_IO1 PRG_I2C2_PULLUPRESX for I2C2 or Set CONTROL CONTROL_ 7 PROG_IO2 PRG_I2C3_PULLUPRESX for I2C3 HS mode and bus capacitance 45 pF No Yes i2c 028 Write I2C I2C_OA0 i F S mode I2C I2C_OA0 9 0 OA bit field i HS mode I2C I2C_OA0 9 0 ...

Page 2803: ...r for I2C I2C_BUFSTAT 5 0 i TXSTAT times I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP and i I2C I2C_CON 10 MST bits i are cleared by hardware I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP bits i are cleared by hardware Reprogram the registers see Note 2 New start Yes No No Hardware releases the serial clock line i2c _scl to high i I C controller goes into 2 slave receiver mode Stop Yes I2C I2C_STAT 12 BB...

Page 2804: ..._CON 0 STT bit I2C I2C_CON 1 STP bit 1 0 1 0 and then 0 1 or 1 1 i i EXPECTED I2C_IE I2C I2C_IE 0000h i Read I2C I2C_BUFSTAT 13 8 i RXSTAT to check the amount of data left to be received Clear ARDY bit see Note 1 Clear AL bit see Note 1 Clear NACK bit see Note 1 Read I2C I2C_DATA i register for I2C I2C_BUFSTAT 13 8 i RXSTAT times I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP and i I2C I2C_CON 10 MST b...

Page 2805: ...2C_BUFSTAT 5 0 i TXSTAT times I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP and i I2C I2C_CON 10 MST bits i are cleared by hardware I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP bits i are cleared by hardware Reprogram the registers see Note 2 New start Yes No Hardware releases the serial clock line i2c _scl to high i I C controller goes into 2 slave receiver mode Stop Yes Is interrupt received Yes No Set...

Page 2806: ... Clear NACK bit see Note 1 Read I2C I2C_DATA i register for I2C I2C_BUFSTAT 13 8 i RXSTAT times I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP and i I2C I2C_CON 10 MST bits i are cleared by hardware I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP bits i are cleared by hardware Reprogram the registers see Note 2 New start Yes No Hardware releases the serial clock line i2ci_scl to high I C controller goes into...

Page 2807: ...STP and i I2C I2C_CON 10 MST bits i are cleared by hardware I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP bits i are cleared by hardware Reprogram the registers see Note 2 New start Yes No Hardware releases the serial clock line i2c _scl to high i I C controller goes into 2 slave receiver mode Stop Yes Is interrupt received Yes No Take necessary action DMA serves the request Is DMA request received Ye...

Page 2808: ...F 13 8 i RTRSH 1 times See Note 2 I2C I2C_STAT 13 RDR i I2C I2C_STAT 3 RRDY i i2c 035 Public Version HS I2 C Basic Programming Model www ti com Figure 17 34 HS I2 C Master Receiver Mode DMA Method in F S and HS Modes I2 C Mode 1 The XRDY RDR RRDY and ARDY bits are cleared by writing 1 to each corresponding bit in the I2Ci I2C_STAT register 2 Reprogram registers means I2Ci I2C_CON 11 STB and or I2C...

Page 2809: ...ivating the draining feature of the DMA controller I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP and i I2C I2C_CON 10 MST bits are i cleared by hardware I2C I2C_CON 0 STT and i I2C I2C_CON 1 STP bits i are cleared by hardware Reprogram the registers see Note 2 New start Yes No No Hardware releases the serial clock line i2c _scl to high i I C controller goes into 2 slave receiver mode Stop Yes Is inter...

Page 2810: ...2 HS I2 C Controller Basic Programming Model in SCCB Mode This section describes the programming model of the multimaster HS I2 C controllers configured in SCCB mode 17 5 2 1 HS I2 C Main Program SCCB Mode 17 5 2 1 1 HS I2 C Configure the Module Before Enabling the I2 C Controller SCCB Mode Before enabling the I2 C controller perform the following steps 1 Enable the functional and interface clocks...

Page 2811: ... I2Ci I2C_CON 0 STT bit to 1 Because a transfer allows the LH to write or read only a single byte to or from the external SCCB device the transmission automatically stops at the end of the transfer When the transfer completes the I2Ci I2C_STAT 2 ARDY bit is set to 1 In SCCB mode the I2Ci I2C_CON 1 STP bit is not used 17 5 2 1 4 HS I2 C Receive Data SCCB Mode Poll the I2Ci I2C_STAT 3 RRDY bit or us...

Page 2812: ...ite I2C I2C_SCLH 7 0 SCLH bit field only i Write the 8 bit register address subaddress in the I2C I2C_OA0 register i Write I2C I2C_IE register i enable interrupts i2c 037 Public Version HS I2 C Basic Programming Model www ti com Figure 17 37 HS I2 C Setup Procedure SCCB Mode 2812 SWPU177N December 2009 Revised November 2010 Multimaster High Speed I2 C Controller Copyright 2009 2010 Texas Instrumen...

Page 2813: ...Y i bit 1 End Write I2C I2C_DATA i register Clear XRDY bit See Note Clear ARDY bit See Note Yes i2c 038 Public Version www ti com HS I2 C Basic Programming Model Figure 17 38 HS I2 C Master Transmitter Mode Polling SCCB Mode NOTE The XRDY and ARDY bits are cleared by writing 1 to the corresponding bit in the I2Ci I2C_STAT register 2813 SWPU177N December 2009 Revised November 2010 Multimaster High ...

Page 2814: ...ear ARDY bit See Note Is received data in 2C I2C_DATA RRDY 1 i No Read I2C I2C_DATA i register Yes i2c 039 Public Version HS I2 C Basic Programming Model www ti com Figure 17 39 HS I2 C Master Receiver Mode Polling SCCB Mode NOTE The RRDY and ARDY bits are cleared by writing 1 in the corresponding bit in the I2Ci I2C_STAT register 2814 SWPU177N December 2009 Revised November 2010 Multimaster High ...

Page 2815: ...es Can update the registers ARDY 1 No End I2C I2C_STAT 2 ARDY i bit 1 I2C I2C_STAT 4 XRDY i bit 1 I2C 040 Public Version www ti com HS I2 C Basic Programming Model Figure 17 40 HS I2 C Master Transmitter Mode Interrupt SCCB Mode NOTE The XRDY and ARDY bits are cleared by writing 1 in the corresponding bit in the I2Ci I2C_STAT register 2815 SWPU177N December 2009 Revised November 2010 Multimaster H...

Page 2816: ...ee Note Clear ARDY bit See Note Is received data in I2C I2C_DATA i RRDY 1 No Read I2C I2C_DATA i register Yes i2c 041 Public Version HS I2 C Basic Programming Model www ti com Figure 17 41 HS I2 C Master Receiver Mode Interrupt SCCB Mode NOTE The RRDY and ARDY bits are cleared by writing 1 in the corresponding bit in the I2Ci I2C_STAT register 2816 SWPU177N December 2009 Revised November 2010 Mult...

Page 2817: ...re the HS I2 C4 At power on reset PoR the I2C4 is in HS mode the PRCM PRM_VC_I2C_CFG 3 HSEN bit In HS mode the LH must configure the master code value for the preamble I2 C HS transmission by configuring the PRCM PRM_VC_I2C_CFG 2 0 MCODE bit field If the external power chips do not support the I2 C HS mode the HS mode can be disabled and F S mode enabled by clearing the PRCM PRM_VC_I2C_CFG 3 HSEN ...

Page 2818: ...04 0x4807 0004 0x4807 2004 0x4806 0004 I2C_STAT RW 16 0x08 0x4807 0008 0x4807 2008 0x4806 0008 I2C_WE RW 16 0x0C 0x4807 000C 0x4807 200C 0x4806 000C I2C_SYSS R 16 0x10 0x4807 0010 0x4807 2010 0x4806 0010 I2C_BUF RW 16 0x14 0x4807 0014 0x4807 2014 0x4806 0014 I2C_CNT RW 16 0x18 0x4807 0018 0x4807 2018 0x4806 0018 I2C_DATA RW 16 0x1C 0x4807 001C 0x4807 201C 0x4806 001C I2C_SYSC RW 16 0x20 0x4807 002...

Page 2819: ...V IP revision R See 1 7 4 Major revision 3 0 Minor revision Examples 0x30 for 3 0 0x31 for 3 1 1 TI internal data Table 17 18 Register Call Summary for Register I2C_REV HS I2C Register Manual HS I2C Register Summary 0 Table 17 19 I2C_IE Address Offset 0x04 Physical Address 0x4806 0004 Instance I2C3 0x4807 0004 I2C1 0x4807 2004 I2C2 Description I2 C interrupt enable register This register contains ...

Page 2820: ...ndition interrupt enable Mask or unmask the RW 0 interrupt signaled by the bit in I2C_STAT STC 0x0 Start Condition interrupt disabled 0x1 Start Condition interrupt enabled 5 GC_IE General Call interrupt enable Mask or unmask the RW 0 interrupt signaled by the bit in I2C_STAT GC 0x0 General Call interrupt disabled 0x1 General Call interrupt enabled 4 XRDY_IE Transmit data ready interrupt enable Mas...

Page 2821: ...x4807 0008 I2C1 0x4807 2008 I2C2 Description I2 C status register This register provides specific status information about the module including interrupt status information Type RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XDR RDR BB ROVR XUDF AAS BF AERR STC GC XRDY RRDY ARDY NACK AL RESERVED Bits Field Name Description Type Reset 15 RESERVED Write 0s for future compatibility Read returns 0 RW 0 14 X...

Page 2822: ...Write No effect 0x0 Write Clear this bit to 0 0x1 9 AAS Address recognized as slave IRQ status RW 0 Read No action 0x0 Read Address recognized 0x1 Write No effect 0x0 Write Clear this bit to 0 0x1 8 BF Bus Free IRQ status RW 0 Read No action 0x0 Read Bus free 0x1 Write No effect 0x0 Write Clear this bit to 0 0x1 7 AERR Access Error IRQ status RW 0 Read No action 0x0 Read Access error 0x1 Write No ...

Page 2823: ...gnaled to MPU subsystem Read No data available 0x0 Read Receive data available 0x1 Write No effect 0x0 Write Clear this bit to 0 0x1 2 ARDY Register Access Ready IRQ status Setting this bit to 1 RW 0 indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPU subsystem Read Module busy 0x0 Read Access ready 0x1 Write No effect 0x0 ...

Page 2824: ...in I2C Mode 27 28 29 30 HS I2C FIFO Interrupt Mode Operation 31 32 HS I2C FIFO Polling Mode Operation 33 34 35 36 37 38 HS I2C Draining Feature I2C Mode Only 39 40 41 42 43 HS I2C System Test Mode 44 45 46 HS I2C Basic Programming Model HS I2C Main Program I2C Mode 47 48 49 50 51 52 53 HS I2C Interrupt Subroutine Sequence I2C Mode 54 55 56 57 58 59 60 61 62 HS I2C Programming Flow Diagrams I2C Mod...

Page 2825: ...abled 8 BF_WE Bus Free wakeup enable RW 0 0x0 Bus Free wakeup disabled 0x1 Bus Free wakeup enabled 7 Reserved Write 0s for future compatibility Read returns 0 RW 0 6 STC_WE Start Condition wakeup enable RW 0 0x0 Start condition wakeup disabled 0x1 Start condition wakeup enabled 5 GC_WE General call wakeup enable RW 0 0x0 General call wakeup disabled 0x1 General call wakeup enabled 4 Reserved Write...

Page 2826: ...Field Name Description Type Reset 15 1 RESERVED Read returns 0 R 0x00 0 RDONE Internal reset monitoring R 0 Read Internal module reset in ongoing 0x0 Read Internal module reset complete 0x1 Table 17 26 Register Call Summary for Register I2C_SYSS HS I2C Integration HS I2C Resets 0 1 2 HS I2C Register Manual HS I2C Register Summary 3 Table 17 27 I2C_BUF Address Offset 0x14 Physical Address 0x4806 00...

Page 2827: ... 18 HS I2C FIFO Polling Mode Operation 19 20 HS I2C FIFO DMA Mode Operation I2C Mode Only 21 22 23 24 25 HS I2C Draining Feature I2C Mode Only 26 27 28 29 30 31 32 33 HS I2C Write and Read Operations in SCCB Mode 34 35 HS I2C Basic Programming Model HS I2C Main Program I2C Mode 36 37 38 39 40 41 42 43 44 HS I2C Programming Flow Diagrams I2C Mode 45 46 HS I2C Main Program SCCB Mode 47 48 49 50 HS I...

Page 2828: ...FIFO i e at reset or write accesses to a full FIFO will return error Type RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATA Bits Field Name Description Type Reset 15 8 Reserved Write 0s for future compatibility Read returns 0 RW 0x00 7 0 DATA Transmit Receive FIFO data RW 0x Table 17 32 Register Call Summary for Register I2C_DATA HS I2C Integration HS I2C DMA Requests 0 1 2 3 4 5 HS I2C Inter...

Page 2829: ...f 0x3 Both clocks must be kept active 7 5 RESERVED Write 0s for future compatibility Read returns 0 RW 0x0 4 3 IDLEMODE Idle Mode selection bits RW 0x0 0x0 Force Idle mode 0x1 No Idle mode 0x2 Smart Idle mode 0x3 Reserved 2 ENAWAKEUP Enable wakeup control bit RW 0 0x0 Wakeup mechanism is disabled 0x1 Wakeup mechanism is enabled 1 SRST Software reset This bit is automatically reset by the RWl 0 har...

Page 2830: ...ODE Operation mode selection RW 0x0 0x0 I2C Fast Standard mode 0x1 I2C High Speed mode 0x2 SCCB mode 0x3 Reserved 11 STB Start byte mode master mode only RW 0 0x0 Normal mode 0x1 Start byte mode 10 MST Master slave mode selection RWl 0 0x0 Slave mode 0x1 Master mode 9 TRX Transmitter Receiver mode master mode only RW 0 0x0 Receiver mode 0x1 Transmitter mode 8 XSA Expand slave address enable bit RW...

Page 2831: ...13 14 HS I2C Transmit Mode in I2C Mode 15 16 HS I2C Receive Mode in I2C Mode 17 HS I2C FIFO Interrupt Mode Operation 18 19 HS I2C Programmable Multislave Channel Feature I2C Mode Only 20 21 22 23 HS I2C Clocking 24 HS I2C System Test Mode 25 26 27 HS I2C Write and Read Operations in SCCB Mode 28 29 30 31 HS I2C Basic Programming Model HS I2C Main Program I2C Mode 32 33 34 35 36 37 38 39 40 41 HS I...

Page 2832: ...Name Description Type Reset 15 10 Reserved Write 0s for future compatibility Read returns 0 RW 0x00 9 0 SA Slave address value RW 0x3FF Table 17 40 Register Call Summary for Register I2C_SA HS I2C Functional Description HS I2C Write and Read Operations in SCCB Mode 0 1 HS I2C Basic Programming Model HS I2C Main Program I2C Mode 2 HS I2C Programming Flow Diagrams I2C Mode 3 4 5 6 7 8 HS I2C Main Pr...

Page 2833: ... 43 I2C_SCLL Address Offset 0x34 Physical Address 0x4806 0034 Instance I2C3 0x4807 0034 I2C1 0x4807 2034 I2C2 Description This register is used to determine the SCL low time value when master Type RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSSCLL SCLL Bits Field Name Description Type Reset 15 8 HSSCLL I2 C High Speed mode SCL low time value RW 0x00 7 0 SCLL I2 C Fast Standard or SCCB modes SCL low t...

Page 2834: ...ummary 11 Table 17 47 I2C_SYSTEST Address Offset 0x3C Physical Address 0x4806 003C Instance I2C3 0x4807 003C I2C1 0x4807 203C I2C2 Description This register is used to facilitate system level tests by overriding some of the standard functional features of the peripheral Type RW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FREE TMODE SSB Reserved SCL_I SDA_I ST_EN SCL_O SDA_O SCCBE_O SCL_I_FUNC SDA_I_FUNC...

Page 2835: ...output value functional mode RW 0 0x0 Driven 0 to SDA line 0x1 Driven 1 to SDA line 4 SCCBE_O SCCBE line sense output value Writing is possible only if RW 0 ST_EN bit is set to 1 0x0 Write 0 to SCCBE line 0x1 Write 1 to SCCBE line 3 SCL_I SCL line sense input value R 0 0x0 Read 0 from SCL line 0x1 Read 1 from SCL line 2 SCL_O SCL line drive output value Writing is possible only if RW 0 ST_EN bit i...

Page 2836: ...compatibility Read returns 0 R 0x0 5 0 TXSTAT TX Buffer Status It indicates the number of bytes to be R 0x00 written in the TX FIFO when the I2C_STAT XDR is asserted set to 1 This indication is useful only in transmitter mode when the draining feature is enabled 1 See Table 17 11 Table 17 50 Register Call Summary for Register I2C_BUFSTAT HS I2C Integration HS I2C Interrupt Requests 0 HS I2C Functi...

Page 2837: ...ure compatibility Read returns 0 R 0x00 9 0 OA2 Own address 2 value RW 0x000 Table 17 54 Register Call Summary for Register I2C_OA2 HS I2C Register Manual HS I2C Register Summary 0 Table 17 55 I2C_OA3 Address Offset 0x4C Physical Address 0x4806 004C Instance I2C3 0x4807 004C I2C1 0x4807 204C I2C2 Description This register is used to specify the module I2C 7 bit or 10 bit address Type RW 15 14 13 1...

Page 2838: ...0 Read Own Address inactive 0x0 Read Own Address active 0x1 2 OA2_ACT Own Address 2 active R 0 Read Own Address inactive 0x0 Read Own Address active 0x1 1 OA1_ACT Own Address 1 active R 0 Read Own Address inactive 0x0 Read Own Address active 0x1 0 OA0_ACT Own Address 0 active R 0 Read Own Address inactive 0x0 Read Own Address active 0x1 Table 17 58 Register Call Summary for Register I2C_ACTOA HS I...

Page 2839: ...x0 I2C Clock Released 0x1 I2C Clock Blocked 2 OA2_EN Enable I2C Clock Blocking for Own Address 2 RW 0 0x0 I2C Clock Released 0x1 I2C Clock Blocked 1 OA1_EN Enable I2C Clock Blocking for Own Address 1 RW 0 0x0 I2C Clock Released 0x1 I2C Clock Blocked 0 OA0_EN Enable I2C Clock Blocking for Own Address 0 RW 0 0x0 I2C Clock Released 0x1 I2C Clock Blocked Table 17 60 Register Call Summary for Register ...

Page 2841: ... 1 HDQ 1 Wire Overview 2842 18 2 HDQ 1 Wire Environment 2843 18 3 HDQ 1 Wire Integration 2846 18 4 HDQ 1 Wire Functional Description 2848 18 5 HDQ 1 Wire Basic Programming Model 2854 18 6 HDQ 1 Wire Use Cases and Tips 2858 18 7 HDQ 1 Wire Register Manual 2861 2841 SWPU177N December 2009 Revised November 2010 HDQ 1 Wire Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2842: ...e Highlight The HDQ and 1 Wire module has a generic L4 interface and is intended to be used in an interrupt driven fashion The one pin interface is implemented as an open drain output at the device level The HDQ operates from a fixed 12 MHz functional clock provided by the PRCM module Only the MPU subsystem uses the HDQ 1 Wire module The main features of the HDQ 1 Wire module support the following...

Page 2843: ...n initialization pulse to the slave However the slave can be reset by using an initialization pulse also referred to as a break pulse The initialization pulse is generated by setting the INITIALIZATION bit HDQ HDQ_CTRL_STATUS 2 The slave does not respond with a presence pulse as it does in the 1 Wire protocol The HDQ is a command based protocol in which the host sends a command byte to the slave T...

Page 2844: ...e before enabling any communication sequence As for the initialization pulse the presence pulse is a low going edge on the line initiated by the slave The timing diagram in Figure 18 4 shows the 1 Wire SDQ reset sequence Figure 18 4 1 Wire SDQ Reset Timing Diagram The host drives the line to a logic low state for a minimum of reset low time Once the slave detects this pulse it must drive the line ...

Page 2845: ...B being transmitted first The command byte of the HDQ 1 Wire protocols consists of eight contiguous valid command bits The command byte contains two fields R W command and address The R W bit of the command byte determines whether the command is a read or a write and the address field containing bits AD6 AD0 indicates the address to be read or written Table 18 2 lists the command byte values Table...

Page 2846: ...vided the other modules that receive it do not require it either For details about the PRCM register settings and DPLL4 configuration see Chapter 3 Power Reset and Clock Management HDQ_ICLK is the interface clock It runs at L4 interconnect clock speed and is used to trigger access to the HDQ 1 Wire L4 interface Its source is the PRCM CORE_L4_ICLK signal It typically runs at L3 2 frequency When the...

Page 2847: ...n about the CORE power domain see Chapter 3 Power Reset and Clock Management 18 3 2 Hardware Requests The HDQ 1 Wire can generate one interrupt HDQ_IRQ This is an interrupt to the MPU subsystem interrupt controller It is mapped on M_IRQ_58 2847 SWPU177N December 2009 Revised November 2010 HDQ 1 Wire Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2848: ... a single wire to establish communication between the master and the slave Both protocols use a return to 1 mechanism that is after any command is driven the line is pulled to a high level This mechanism requires an external pullup 18 4 1 HDQ 1 Wire Block Diagram Figure 18 8 shows the HDQ 1 Wire block diagram Figure 18 8 HDQ 1 Wire Block Diagram The MODE bit HDQ HDQ_CTRL_STATUS 0 allows selection ...

Page 2849: ... The timing parameters and protocol are different in the two modes 18 4 2 HDQ Mode Default 18 4 2 1 HDQ Mode Features The HDQ mode supports the following Benchmark HDQ protocol Power down mode 18 4 2 2 Description In the HDQ mode there is no need for the host to create an initialization pulse to the slave However the host can reset the slave by using an initialization pulse also known as a break p...

Page 2850: ...individually masked 18 4 2 3 Single Bit Mode In HDQ mode the single bit mode 1_WIRE_SINGLE_BIT bit HDQ HDQ_CTRL_STATUS 7 set to 1 has no effect because the HDQ protocol supports only byte transfers 18 4 2 4 Interrupt Conditions The HDQ 1 Wire module provides the following interrupt status 1 Transmission complete A write operation of one byte was completed Successful or failed completion is not ind...

Page 2851: ...ions 1 Wire is a bit by bit protocol which means the slave must be clocked by the host for each bit of the byte to read The line is pulled up at the end of the command address byte On the first read the host creates a low going edge to initiate a bit read The line is then pulled up pulled to the high impedance state by the host and set to a high logical level by the external pullup and the slave e...

Page 2852: ...ck domain The interconnect clock autoidle power saving mode is enabled or disabled through the AUTOIDLE bit HDQ HDQ_SYSCONFIG 0 When this mode is enabled and there is no activity on the interconnect interface the interconnect clock HDQ_ICLK is disabled inside the module thereby reducing power consumption When there is new activity on the interconnect interface the interconnect clock is restarted w...

Page 2853: ... whole domain is put into idle the HDQ 1 Wire is also put into idle Software must ensure correct clock management CAUTION There is no hardware mechanism to prevent cutting off the HDQ 1 Wire clocks while the module is performing a transfer The result would be a loss of data being transferred 2853 SWPU177N December 2009 Revised November 2010 HDQ 1 Wire Copyright 2009 2010 Texas Instruments Incorpor...

Page 2854: ...t HDQ HDQ_CTRL_STATUS 4 to 1 to send the pulse When the pulse is sent the bit is cleared in the register 2 Wait for the presence detect flag TIMEOUT bit HDQ HDQ_INT_STATUS 0 to generate an interrupt This flag is set when the response time allowed to the slave has elapsed whether it has sent a pulse or not 3 Read the HDQ HDQ_CTRL_STATUS register to check whether the presence pulse has been received...

Page 2855: ...leted or a time out occurred 6 The software reads the RX receive buffer register HDQ HDQ_RX_DATA to retrieve the read data from the slave 7 Repeat step 1 through step 6 for each successive byte NOTE In HDQ mode the address command is written only once to the slave However after the first byte is received an RX complete interrupt is set Therefore the software must initiate the read of the second by...

Page 2856: ...setting the 1_WIRE_SINGLE_BIT bit HDQ HDQ_CTRL_STATUS 7 to 1 In this mode only one bit of data at a time is transferred between the master and the slave After the bit is transferred the corresponding interrupt flag is set that is there is an RX complete RXCOMPLETE bit HDQ HDQ_INT_STATUS 1 for a read operation and a TX complete TXCOMPLETE bit HDQ HDQ_INT_STATUS 2 for a write operation Bit 0 of the ...

Page 2857: ...HDQ HDQ_RX_DATA to retrieve the read data 4 The HDQ_ICLK can be shut off by entering the system idle mode In a write operation 1 Wait for a TX complete interrupt In a write operation the transfer is completed when the TX complete flag TXCOMPLETE bit HDQ HDQ_INT_STATUS 2 generates an interrupt The software must check whether the interrupt was generated after the address command byte was sent or aft...

Page 2858: ...2 Programming Flow This section details the programming flow of the HDQ 1 Wire Figure 18 11 shows the main steps of this configuration The BQ27000 gauge uses the HDQ mode Figure 18 11 HDQ 1 Wire Configuration in HDQ Mode 18 6 1 3 Pad Configuration and HDQ 1 Wire Clock and Power Management Table 18 3 shows the pad multiplexing and the clock and power management configuration to select for the HDQ 1...

Page 2859: ...oidle mode 18 6 1 4 HDQ 1 Wire Software Reset Perform a software reset as described in Figure 18 12 Figure 18 12 Software Reset Flowchart Table 18 4 describes the registers to be configured for the HDQ 1 Wire software reset step Table 18 4 Registers Print for HDQ 1 Wire Software Reset Register Name Address Value Value description HDQ_SYSCONFIG 0x480B 2014 0x0000 0002 Initiate a software reset The ...

Page 2860: ...nd Write Operations The Read and Write operations in HDQ mode are described in Section 18 5 2 Some write operations are needed to configure the BQ27000 gauge for example it is necessary to write a COMMAND KEY 0xA9 or 0x56 in the Device Control Register of the gauge For more information see the TI BQ27000 gauge specification 2860 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 200...

Page 2861: ...odule Polling of the interrupt status register by software to determine whether an interrupt was generated is not allowed No access to the module registers should be done after the software puts the module in power down mode by setting bit 5 of the control and status register to 0 except to re enable the clock CAUTION The HDQ 1 Wire registers are limited to 32 bit data accesses 16 bit and 8 bit ar...

Page 2862: ...l HDQ 1 Wire Register Mapping Summary 0 Table 18 10 HDQ_TX_DATA Address Offset 0x004 Physical Address 0x480B 2004 Instance HDQ 1 Wire Description This register contains the data to be transmitted Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TX_DATA Bits Field Name Description Type Reset 31 8 Reserved Reads return 0s R 0x000000 7 0 TX_DATA T...

Page 2863: ...ire Bit Mode Operation 6 System Idle Mode 7 HDQ 1 Wire Register Manual HDQ 1 Wire Register Mapping Summary 8 Table 18 14 HDQ_CTRL_STATUS Address Offset 0x00C Physical Address 0x480B 200C Instance HDQ 1 Wire Description This register provides status information about the module Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved GO DIR MODE INITIAL...

Page 2864: ...ire Functional Description HDQ 1 Wire Block Diagram 1 Description 2 Single Bit Mode 3 Description 4 5 1 Wire Single Bit Mode Operation 6 Status Flags 7 Power Down Mode 8 HDQ 1 Wire Basic Programming Model Mode Selection 9 Reset Initialization 10 11 12 13 14 Write Operation 15 16 17 Read Operation 18 19 20 21 22 23 24 Write Operation 25 26 Read Operation 27 28 29 30 31 32 33 1 Wire Bit Mode Operati...

Page 2865: ...gister Call Summary for Register HDQ_INT_STATUS HDQ 1 Wire Functional Description Description 0 1 2 Interrupt Conditions 3 4 5 Description 6 7 Interrupt Conditions 8 9 10 Status Flags 11 HDQ 1 Wire Basic Programming Model Reset Initialization 12 Write Operation 13 Read Operation 14 15 Write Operation 16 17 Read Operation 18 19 1 Wire Bit Mode Operation 20 21 Module Power Down Mode 22 23 24 System ...

Page 2866: ...e Software Reset 4 5 HDQ 1 Wire Register Manual HDQ 1 Wire Register Mapping Summary 6 Table 18 20 HDQ_SYSSTATUS Address Offset 0x018 Physical Address 0x480B 2018 Instance HDQ 1 Wire Description This register monitors the reset sequence Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RESETDONE Bits Field Name Description Type Reset 31 1 Reserved...

Page 2869: ...data association IrDA consumer infrared CIR module Topic Page 19 1 UART IrDA CIR Overview 2870 19 2 UART IrDA CIR Environment 2873 19 3 UART IrDA CIR Integration 2886 19 4 UART IrDA CIR Functional Description 2890 19 5 UART IrDA CIR Basic Programming Model 2920 19 6 UART IrDA CIR Register Manual 2928 2869 SWPU177N December 2009 Revised November 2010 UART IrDA CIR Copyright 2009 2010 Texas Instrume...

Page 2870: ...ut for use as UART devices only UART1 and UART2 must be programmed by setting the UARTi MDR1_REG 2 0 MODE_SELECT field to one of the three UART operating modes UART3 which adds infrared communication support is pinned out for use as a UART infrared data association IrDA or consumer infrared CIR device and can be programmed to any available operating mode Figure 19 1 UART Module 19 1 1 UART Feature...

Page 2871: ...400 16 208 0 16 19 200 16 156 0 16 28 800 16 704 0 16 38 400 16 78 0 16 57 600 16 52 0 16 115 200 16 26 0 16 230 400 16 13 0 16 460 800 13 8 0 16 921 600 13 4 0 16 1 843 200 13 2 0 16 3 000 000 16 1 0 3 686 400 13 1 0 16 19 1 2 IrDA Features The IrDA UART3 only includes the following key features Support of IrDA 1 4 slow infrared SIR medium infrared MIR and fast infrared FIR communications Frame f...

Page 2872: ... mode uses a variable pulse width modulation PWM technique based on multiples of a programmable t period to encompass the various formats of infrared encoding for remote control applications The CIR logic transmits data packets based on a user definable frame structure and packet content The CIR UART3 only includes the following key features to provide CIR support for remote control applications T...

Page 2873: ... UART3 or UART4 can be connected easily to the UART port of an external IC see Figure 19 2 Figure 19 2 UART Mode Bus System Overview NOTE UART4 does not provide flow control so it does not have uarti_rts and uarti_cts signals 19 2 2 System Using IrDA Communication Protocol As Figure 19 3 shows UART3 can be connected to an external infrared transceiver in the IrDA modes FIR SIR and MIR Figure 19 3 ...

Page 2874: ...e uses uarti_cts to control the transmitter uarti_rts O Request to send UART1 UART2 and UART3 only 1 When active low the module is ready to receive data Setting the UARTi MCR_REG 1 RTS bit activates uarti_rts which becomes inactive as the result of a module reset loopback mode or clearing the UARTi MCR_REG 1 RTS bit In auto RTS mode uarti_rts becomes inactive as a result of the receiver threshold ...

Page 2875: ...19 2 5 2 1 SIR Mode In SIR mode data is transferred between the MPU and peripheral devices at speeds of up to 115 200 baud A SIR transmit frame begins with start flags a single 0xC0 a multiple 0xC0 or a single 0xC0 preceded by a number of 0xFF flags is followed by frame data and a CRC 16 and ends with a stop flag 0xC1 The bit format for a single word uses 1 start bit 8 data bits and 1 stop bit and...

Page 2876: ...dth is 1 6 Îµs and in 3 16th encoding the infrared pulse width is 3 16th of a bit duration 1 baud rate The transmitting device must send at least two start flags at the start of each frame for back to back frames NOTE Reception supports variable length stop bits 19 2 5 2 1 1 Frame Format Figure 19 6 shows the IrDA SIR frame format Figure 19 6 IrDA SIR Frame Format The CRC is applied on the address...

Page 2877: ...d to transmit data to the optoelectronics While the TX FIFO output is high the uart3_tx_irtx line is always low and the counter used to form a pulse on uart3_tx_irtx is cleared continuously After the TX FIFO output resets to 0 uart3_tx_irtx rises on the falling edge of the 7th 16XCLK On the falling edge of the 10th 16XCLK pulse uart3_tx_irtx falls creating a three clock wide pulse While the TX FIF...

Page 2878: ...nment To program two frame addresses that the UART3 receives in IrDA mode use the UART3 XON1_ADDR1_REG 7 0 field and the UART3 XON2_ADDR2_REG 7 0 field Table 19 5 EFR_REG 0 1 IR Address Checking Options EFR_REG 1 EFR_REG 0 IR Address Checking 0 0 All address checking operations disabled 0 1 Only address 1 checking enabled 1 0 Only address 2 checking enabled 1 1 All address checking operations enab...

Page 2879: ...ve 1s this is called bit stuffing 0x7E is used for both start and stop flags unambiguously not data because of bit stuffing Abort sequence requires a minimum of seven consecutive 1s unambiguously not data because of bit stuffing Back to back frames are allowed with three or more stop flags in between If two consecutive frames are not back to back the gap between the last stop flag of the first fra...

Page 2880: ...actly 1 4 but it is within the tolerances defined by the IrDA specifications Figure 19 11 shows the MIR baud rate adjustment mechanism Figure 19 11 MIR Baud Rate Adjustment Mechanism 19 2 5 2 3 2 SIP Generation In the MIR and FIR operation modes the transmitter must send a serial infrared interaction pulse SIP at least once every 500 ms The SIP informs slow devices operating in SIR mode that the m...

Page 2881: ...p Flag Frame Part Transmitted Frame Bin Preamble 1000 0000 1010 1000 16 repeated transmissions Start Flag 0000 1100 0000 1100 0110 0000 0110 0000 Stop Flag 0000 1100 0000 1100 0000 0110 0000 0110 All fields are transmitted the LSBs of each byte first see Table 19 9 Table 19 9 FIR Data Byte Transmission Order Example Data Byte Hex Data Byte Pair Bin 4 PPM Data Symbol Bin Transmission Order 0x0B 00 ...

Page 2882: ... is an inverted value of the UART3 ACREG_REG 6 SD_MOD bit 1 I Input O Output 19 2 6 2 CIR Protocol and Data Format In the CIR mode the infrared operation functions as a programmable universal remote control The CIR mode uses a variable PWM technique based on multiples of a programmable t period to encompass the various formats of infrared encoding for remote control applications The CIR logic tran...

Page 2883: ...e receiving end needs it 19 2 6 2 3 Consumer IR Encoding Decoding There are two methods of encoding for remote control applications The first method uses time extended bit forms a variable pulse distance or duration in which the difference between a logic 1 and logic 0 is the length of the pulse width The second encoding method uses a biphase in which the encoding of the logic 0 and logic 1 is in ...

Page 2884: ...ngth that is multiples of T is the method used to distinguish between 1 and 0 The following SIRC digits show the difference in encoding between this and for example RC 5 The pulse width is extended for one digit Figure 19 16 shows SIRC bit encoding Figure 19 16 SIRC Bit Encoding To construct comprehensive packets constituting remote control commands the MPU software must combine a number of 8 bit ...

Page 2885: ...range to increase to 7 bits This format is known as the extended RC 5 format SIRC encoding uses the duration of modulation for mark and space therefore the duration of data bits inside the standard frame length varies Figure 19 18 shows the packet format and bit encoding As Figure 19 19 shows 1 start bit of 2 ms and control codes are followed by data that constitute the entire frame Figure 19 18 S...

Page 2886: ...UART4_FCLK IDLE hardware handshake 3 32 L4 Per Registers UART4 UART UART4_IRQ UART4_DMA_TX RX 2 Registers UART4 SYSC 4 3 32 M_IRQ_80 S_DMA_80 81 UART4_SWAKEUP Public Version UART IrDA CIR Integration www ti com 19 3 UART IrDA CIR Integration Figure 19 20 shows the device internal connections with related modules for UART functions Figure 19 20 UART Functional Integration 19 3 1 Clocking Reset and ...

Page 2887: ...his clock with the PRCM CM_FCLKEN_PER 11 EN_UART3 bit Interface clock PER_L4_ICLK UART3_ICLK Source and gating is the PRCM module Enable disable this clock with the PRCM CM_ICLKEN_PER 11 EN_UART3 bit Enable disable auto idle for this clock with the PRCM CM_AUTOIDLE_ PER 11 AUTO_UART3 bit UART4 Functional clock PER_48M_FCLK UART4_FCLK Source and gating is the PRCM module Enable disable this clock w...

Page 2888: ...IRQ UART module 3 interrupt to MPU M_IRQ_80 UART4_IRQ UART module 4 interrupt to MPU Table 19 15 Interrupt Mapping to IVA2 2 Subsystem IRQ SOURCE DESCRIPTION IVA2_IRQ 15 UART3_IRQ UART module 3 interrupt to IVA2 2 subsystem 19 3 2 2 DMA Requests Table 19 16 describes the UART DMA requests Table 19 16 UART DMA Requests to System DMA DMA 1 Source Description S_DMA_48 UART1_DMA_TX UART module 1 trans...

Page 2889: ...om PRCM Wake Up Pin PRCM Input Description uart1_cts UART1_SWAKEUP Wake UART1 system wake up capabilities uart2_cts UART2_SWAKEUP Wake UART2 system wake up capabilities uart3_cts UART3_SWAKEUP Wake UART3 system wake up capabilities CAUTION UARTs are not in the WAKEUP power domain which implies limitations on wake up capability If the CORE power domain is off UART1 and UART2 cannot wake up the syst...

Page 2890: ...ent Mode selection Protocol formatting FIFO management is common to all functions and enables the transmission and reception of data from the host processor point of view There are two mode selections Function mode selection Route the data to the chosen functionality UART IrDA or CIR and enable the mechanism corresponding to the chosen functionality Register mode selection which enables conditiona...

Page 2891: ...ary control register UARTi SCR_REG Reading the UARTi SSR_REG 0 TX_FIFO_FULL bit at 1 means the FIFO is full The UARTi TLR_REG register controls the FIFO trigger level which enables the DMA and interrupt generation After reset both transmitter and receiver FIFOs are disabled so in effect the trigger level is the default value of 1 byte Figure 19 22 shows the FIFO management registers NOTE Data in t...

Page 2892: ...rs with a granularity of 1 character Note The combination of RX_FIFO_TRIG_DMA 0x0 and RX_FIFO_TRIG 0x0 all zeros is not supported minimum 1 character required All zeros result in unpredictable behavior The receive threshold is programmed using the UARTi TCR_REG 7 4 RX_FIFO_TRIG_START and UARTi TCR_REG 3 0 RX_FIFO_TRIG_HALT fields Trigger levels from 0 to 60 bytes are available with a granularity o...

Page 2893: ...s respectively is reached The interrupt signals instruct the MPU to transfer data to the destination from the UART module in receive mode and or from any source to the UART FIFO in transmit mode When the UART flow control is enabled with the interrupt capabilities the UART flow control FIFO threshold UARTi TCR_REG 3 0 RX_FIFO_TRIG_HALT field must be greater than or equal to the receive FIFO thresh...

Page 2894: ... remaining DMA request is used for TX The DMA requests in mode 2 and mode 3 use S_DMA_48 S_DMA_50 and S_DMA_52 D_DMA_10 S_DMA_49 S_DMA_51 and S_DMA_53 D_DMA_11 are not used by the module in mode 2 and mode 3 and can be selected as follows When the UARTi SCR_REG 0 DMA_MODE_CTL bit is set to 0 setting the UARTi FCR_REG 3 DMA_MODE bit to 0 enables DMA mode 0 Setting the DMA_MODE bit to 1 enables DMA ...

Page 2895: ...s generated when the receive FIFO reaches its threshold level defined in the trigger level register UARTi TLR_REG This request is deasserted when the number of bytes defined by the threshold level is read by the system DMA sDMA In transmit mode a DMA request is automatically asserted when the transmit FIFO is empty This request is deasserted when the number of bytes defined by the number of spaces...

Page 2896: ...ure 19 27 shows an example with eight spaces to show the buffer level crossing the space threshold Again the local host DMA controller settings must correspond to that of the UART IrDA CIR module Figure 19 27 Transmit FIFO DMA Request Generation 8 Spaces The final example shows the setting of one space that uses the DMA for each transfer of one character to the transmit buffer see Figure 19 28 The...

Page 2897: ...d are put in the device memory reserved for UART IrDA CIR transmission by the DMA Until the TX FIFO trigger level is not reached a DMA request is generated An element 1 byte is transferred from the SDRAM to the TX FIFO at each DMA request DMA element synchronization Data in the TX FIFO are automatically transmitted The end of the transmission is signaled by the UARTi THR_REG empty TX FIFO empty NO...

Page 2898: ...nal mode is the selected mode when the function is active serial data transfer can be performed in this mode Both configuration mode A and configuration mode B are used during module initialization steps These modes enable access to configuration registers which are hidden in the operational mode The modes are used when the module is inactive no serial data transfer processed and only in the initi...

Page 2899: ...x00C LCR_REG LCR_REG LCR_REG LCR_REG LCR_REG LCR_REG 0x010 MCR_REG MCR_REG XON1_ADDR1_REG XON1_ADDR1_RE MCR_REG MCR_REG G 0x014 LSR_REG XON2_ADDR2_REG XON2_ADDR2_RE LSR_REG G 0x018 MSR_REG TCR_REG 2 TCR_REG TCR_REG MSR_REG TCR_REG 2 1 TCR_REG 2 2 XOFF1_REG 3 2 XOFF1_REG 3 1 TCR_REG 2 0x01C SPR_REG SPR_REG TLR_REG TLR_REG SPR_REG SPR_REG 1 TLR_REG 2 1 TLR_REG 2 2 XOFF2_REG 3 2 XOFF2_REG 3 1 TLR_REG...

Page 2900: ...8 SYSS_REG SYSS_REG SYSS_REG 0x05C WER_REG WER_REG WER_REG WER_REG WER_REG WER_REG 0x060 CFPS_REG CFPS_REG CFPS_REG CFPS_REG CFPS_REG CFPS_REG 0x064 RXFIFO_LVL_R RXFIFO_LVL_REG RXFIFO_LVL_REG EG 0x068 TXFIFO_LVL_R TXFIFO_LVL_REG TXFIFO_LVL_REG EG 0x06C IER2_REG IER2_REG IER2_REG IER2_REG IER2_REG IER2_REG 0x070 ISR2_REG ISR2_REG ISR2_REG ISR2_REG ISR2_REG ISR2_REG 0x080 MDR3_REG MDR3_REG MDR3_REG ...

Page 2901: ... IIR_REG UART FCR_REG UAR T 0x00C LCR_REG LCR_REG LCR_REG LCR_REG LCR_REG LCR_REG 0x010 MCR_REG MCR_REG XON1_ADDR1_REG XON1_ADDR1_RE MCR_REG MCR_REG G 0x014 LSR_REG UAR XON2_ADDR2_REG XON2_ADDR2_RE LSR_REG UART T G 0x018 MSR_REG TCR TCR_REG XOFF1_REG TCR_R XOFF1_REG TCR MSR_REG TCR_RE TCR_REG _REG EG _REG G 0x01C TLR_REG SPR TLR_REG SPR_ TLR_REG XOFF2_R TLR_REG XOFF2_ TLR_REG SPR_RE TLR_REG SPR _R...

Page 2902: ...R_REG IrDA IER_REG IrDA 0x008 IIR_REG FCR_REG EFR_REG 4 EFR_REG 4 IIR_REG IrDA FCR_REG IrDA 0x00C LCR_REG LCR_REG LCR_REG LCR_REG LCR_REG LCR_REG 0x010 XON1_ADDR1_REG XON1_ADDR1_RE MCR_REG MCR_REG G 0x014 LSR_REG IrDA XON2_ADDR2_REG XON2_ADDR2_RE LSR_REG IrDA G 0x018 MSR_REG TCR TCR_REG TCR_REG TCR_REG MSR_REG TCR_RE TCR_REG _REG G 0x01C TLR_REG SPR TLR_REG SPR_ TLR_REG TLR_REG TLR_REG SPR_RE TLR_...

Page 2903: ...A Configuration_Mode_B Operational_Mode Read Write Read Write Read Write 0x000 DLL_REG DLL_REG DLL_REG DLL_REG THR_REG 0x004 DLH_REG DLH_REG DLH_REG DLH_REG IER_REG CIR IER_REG CIR 0x008 IIR_REG FCR_REG EFR_REG EFR_REG IIR_REG CIR FCR_REG CIR 0x00C LCR_REG LCR_REG 7 LCR_REG 7 LCR_REG 7 LCR_REG 7 LCR_REG 7 0x010 0x014 LSR_REG IrDA LSR_REG IrDA 0x018 MSR_REG TCR TCR_REG TCR_REG TCR_REG MSR_REG TCR_R...

Page 2904: ...VL_REG TXFIFO_LVL_REG TXFIFO_LVL_REG TXFIFO_LVL_R EG G EG 0x06C IER2_REG IER2_REG IER2_REG IER2_REG IER2_REG IER2_REG 0x070 ISR2_REG ISR2_REG ISR2_REG ISR2_REG ISR2_REG ISR2_REG 0x080 MDR3_REG MDR3_REG MDR3_REG MDR3_REG MDR3_REG MDR3_REG 19 4 4 Protocol Formatting 19 4 4 1 UART Mode 19 4 4 1 1 UART Clock Generation Baud Rate Generation The UART function contains a programmable baud generator and a...

Page 2905: ...46 Mbps 0 16 3 6884 Mbps 13x 1 0x00 0x01 3 6923 Mbps 0 16 19 4 4 1 3 UART Data Formatting The UART module can use hardware flow control to manage transmission reception Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals The UART module is enhanced with the autobauding...

Page 2906: ...ter circuitry checks uarti_cts before sending the next data byte When uarti_cts is active the transmitter sends the next byte To stop the transmitter from sending the next byte uarti_cts must be deasserted before the middle of the last stop bit currently sent The auto CTS function reduces interrupts to the host system When auto CTS flow control is enabled the uarti_cts state changes do not have to...

Page 2907: ...s while receiving a software flow control character this character is treated as normal data and is written to the RX FIFO When XON any and special character detect are disabled and software flow control is enabled no valid XON or XOFF characters are written to the RX FIFO For example when UARTi EFR_REG 1 0 0x2 if XON1 and XOFF1 characters are received they do not get written to the RX FIFO When p...

Page 2908: ... fashion when a subsequent character is received Therefore it is recommended that the software enable the RHR interrupt when using the autobaud mode The following settings are detected in autobaud mode with a module clock of 48 MHz Speed 115 2k baud 57 6k baud 38 4k baud 28 8k baud 19 2k baud 14 4k baud 9 6k baud 4 8k baud 2 4k baud or 1 2k baud Length 7 or 8 bits Parity Odd even or space NOTE The...

Page 2909: ...ystem MPU must Reset the RX FIFO Read the UARTi RESUME_REG register which clears the internal flag 19 4 4 1 3 7 Time Out and Break Conditions 19 4 4 1 3 7 1 Time Out Counter An RX idle condition is detected when the receiver line uarti_rx is high for a time equivalent to 4x programmed word length 12 bits uarti_rx is sampled midway through each bit For sleep mode the counter is reset when there is ...

Page 2910: ... pin or CTS pin change state Read IIR_REG from active low to inactive high For the receiver line status interrupt the RX_FIFO_STS bit UARTi LSR_REG 7 generates the interrupt For the XOFF interrupt if an XOFF flow character detection caused the interrupt the interrupt is cleared by an XON flow character detection If special character detection caused the interrupt the interrupt is cleared by a read...

Page 2911: ...ing the Appropriate Divisor Value SIR mode Divisor value Operating frequency 16x baud rate MIR mode Divisor value Operating frequency 41x 42x baud rate FIR mode Divisor value None Table 19 34 lists the IrDA baud rate settings Table 19 34 IrDA Baud Rates Settings Baud Rate IR Mode Baud Multiple Encoding DLH DLL Actual Baud Error Source Jitter Pulse duration Decimal Rate 2 4 Kbps SIR 16x 3 16 1250 2...

Page 2912: ...on avoids receiving frames not meant for this device in a multipoint infrared environment It is possible to program two frame addresses that the UART IrDA receives with the UART3 XON1_ADDR1_REG 7 0 XON_WORD1 and UART3 XON2_ADDR2_REG 7 0 XON_WORD2 fields Setting the EFR_REG 0 bit to 1 selects address1 checking Setting the EFR_REG 1 bit to 1 selects address2 checking Setting the EFR_REG 1 0 bit to 0...

Page 2913: ...he UART3 RESUME_REG register which clears the internal flag This functionality can be disabled by the UART3 ACREG_REG 4 DIS_TX_UNDERRUN bit compensated by the extension of the stop bit in transmission if the TX FIFO is empty 19 4 4 2 3 8 Overrun During Receive Overrun during receive for the IrDA mode has the same functionality as that for the UART mode see Section 19 4 4 1 3 6 Overrun During Recei...

Page 2914: ...evant XOFF RTS CTS modem status register etc 19 4 4 2 5 MIR and FIR Mode Data Formatting This section describes common instructions for FIR and MIR mode programming At the end of a frame reception the MPU reads the line status register UART3 LSR_REG to detect possible errors in the received frame When the UART3 MDR1_REG 6 SIP_MODE bit is set to 1 the TX state machine always sends one SIP at the en...

Page 2915: ...essfully 6 Receiver line status interrupt CRC ABORT or frame length Read STATUS FIFO read until empty error is written into STATUS maximum of eight reads required FIFO 7 Received EOF Received end of frame Read IIR_REG 19 4 4 2 6 2 Wake Up Interrupts The wake up interrupt for the IrDA mode has the same functionality as that for the UART mode see Section 19 4 4 1 4 1 Wake Up Interrupt CAUTION Wake u...

Page 2916: ...value to provide the more accurate pulse frequency Dividing value FCLK 12 MODfreq Where FCLK System clock frequency 48 MHz 12 Real value of baud multiple MODfreq Effective frequency of the modulation MHz Example For a targeted modulation frequency of 36 kHz the CFPS_REG value must be set to 111 decimal which provides a modulation frequency of 36 04 kHz NOTE The UART3 CFPS_REG register starts with ...

Page 2917: ...CTX_EN bit depending on the timer status Using the UART3 IIR_REG 5 TX_STATUS_IT interrupt to preload the next frame in the TX FIFO and to control the start of the timer in case of control delay between the end of a frame and the start of the next frame 19 4 4 3 2 3 CIR Reception There are two methods of stopping reception The MPU can disable the reception by setting the UART3 ACREG_REG 5 DIS_IR_RX...

Page 2918: ...the Read IIR_REG frame is completed successfully 6 N A for CIR mode N A for CIR mode N A for CIR mode 7 N A for CIR mode N A for CIR mode N A for CIR mode 19 4 4 3 3 2 Wake Up Interrupts The wake up interrupt for the IrDA mode has the same functionality as that for the UART mode see Section 19 4 4 1 4 1 Wake Up Interrupt 19 4 5 Power Management 19 4 5 1 UART Mode Power Management 19 4 5 1 1 Module...

Page 2919: ...AWAKEUP bit and the UARTi WER_REG register For more information see Chapter 3 Power Reset and Clock Management 19 4 5 2 IrDA Mode Power Management UART3 Only 19 4 5 2 1 Module Power Saving In IrDA modes sleep mode is enabled by setting the UART3 MDR 3 IR_SLEEP bit to 1 Sleep mode is entered when all the following conditions exist The serial data input line uart3 rx_irrx is idle The TX FIFO and TX ...

Page 2920: ...ing steps 1 Initiate a software reset Set the UARTi SYSC_REG 1 SOFTRESET bit to 1 2 Wait for the end of the reset operation Poll the UARTi SYSS_REG 0 RESETDONE bit until it equals 1 19 5 1 1 2 FIFOs and DMA Settings To enable and configure the receive and transmit FIFOs and program the DMA mode perform the following steps 1 Switch to register configuration mode B to access the UARTi EFR_REG regist...

Page 2921: ...requests See Section 19 4 2 1 2 Receive FIFO Trigger to choose the following values UARTi FCR_REG 7 6 RX_FIFO_TRIG UARTi TLR_REG 7 4 RX_FIFO_TRIG_DMA UARTi SCR_REG 7 RX_TRIG_GRANU1 DMA mode enables the different DMA requests See Section 19 4 2 4 FIFO DMA Mode Operation to choose the following values UARTi FCR_REG 3 DMA_MODE UARTi SCR_REG 2 1 DMA_MODE_2 UARTi SCR_REG 0 DMA_MODE_CTL 19 5 1 1 3 Proto...

Page 2922: ..._TYPE_1 UARTi LCR_REG 3 PARITY_EN UARTi LCR_REG 2 NB_STOP UARTi LCR_REG 1 0 CHAR_LENGTH 13 Load the new UART mode Set UARTi MDR1_REG 2 0 MODE_SELECT to the desired value See Section 19 4 4 1 2 Choosing the Appropriate Divisor Value to choose the following values UARTi DLL_REG 7 0 CLOCK_LSB UARTi DLH_REG 5 0 CLOCK_MSB UARTi MDR1_REG 2 0 MODE_SELECT See Section 19 4 4 1 3 1 Frame Formatting to choos...

Page 2923: ..._RTS_EN 0 Disable 1 Enable Restore UARTi EFR_REG 4 ENHANCED_EN to the saved value 7 Switch to register configuration mode A to access UARTi MCR_REG Set UARTi LCR_REG to 0x0080 8 Restore the UARTi MCR_REG 6 TCR_TLR value saved in Step 2a 9 Restore the UARTi LCR_REG value saved in Step 1a See Section 19 4 4 1 3 2 Hardware Flow Control to choose the following values UARTi EFR_REG 7 AUTO_CTS_EN UARTi ...

Page 2924: ...0 Switch to register configuration mode A to access the UARTi MCR_REG register Set UARTi LCR_REG to 0x0080 11 Restore the UARTi MCR_REG 6 TCR_TLR value saved in Step 6a 12 Restore the UARTi LCR_REG value saved in Step 1a See Section 19 4 4 1 3 3 Software Flow Control to choose the following values UARTi EFR_REG 5 SPEC_CHAR UARTi EFR_REG 3 0 SW_FLOW_CONTROL UARTi TCR_REG 7 4 AUTO_RTS_START UARTi TC...

Page 2925: ... MDR1_REG 0x01 7 Disable access to DLL_REG and DLH_REG and switch to register operational mode UART3 LCR_REG UART3 LCR_REG 0x00 8 Force DTR output to active UART3 MCR_REG 0 DTR 0x1 9 Optional Enable THR interrupt UART3 IER_REG 1 THR_IT 0x1 10 Set transmit frame length to 6 bytes UART3 TXFLL_REG 0x06 11 Set 7 starts of frame transmission UART3 EBLR_REG 0x08 12 Optional Set SIR pulse width to be 1 6...

Page 2926: ...able THR interrupt UART3 IER_REG 1 THR_IT 0x1 8 Set frame length to 60 bytes UART3 TXFLL_REG 0x3C 9 Optional Transmit 8 additional starts of frame MIR mode requires 2 starts anyway UART3 EBLR_REG 0x08 10 SIP will be send at the end of transmission UART3 ACREG_REG 3 0x1 11 Load THR_REG with the desired data to be transmitted 19 5 2 2 3 FIR Mode 19 5 2 2 3 1 Receive The following programming model e...

Page 2927: ...3 Enable the enhanced features EFR_REG 4 ENAHNCED_EN 0x1 UART3 EFR_REG 0x10 4 FIFO clear and enable FCR_REG 0x7 Tx Rx FIFO trigger FCR_REG 7 6 and FCR_REG 5 4 LCR_REG 7 0 5 Set FIR mode and enable auto SIP mode MDR1_REG 0x45 6 Set Frame Length TXFLL_REG 0x4 TXFLH_REG 0x0 RXFLL_REG 0xA Data CRC STO RXFLH_REG 0x0 7 Force DTR output to active UART3 MCR_REG 0 DTR 0x1 8 Optional Enable THR interrupt UA...

Page 2928: ...REG W 32 0x000 0x4806 A000 0x4806 C000 0x4902 0000 DLH_REG RW 32 0x004 0x4806 A004 0x4806 C004 0x4902 0004 IER_REG RW 32 0x004 0x4806 A004 0x4806 C004 0x4902 0004 IIR_REG R 32 0x008 0x4806 A008 0x4806 C008 0x4902 0008 FCR_REG W 32 0x008 0x4806 A008 0x4806 C008 0x4902 0008 EFR_REG RW 32 0x008 0x4806 A008 0x4806 C008 0x4902 0008 LCR_REG RW 32 0x00C 0x4806 A00C 0x4806 C00C 0x4902 000C MCR_REG RW 32 0...

Page 2929: ...68 0x4806 A068 0x4806 C068 0x4902 0068 IER2_REG RW 32 0x06C 0x4806 A06C 0x4806 C06C 0x4902 006C ISR2_REG RW 32 0x070 0x4806 A070 0x4806 C070 0x4902 0070 MDR3_REG RW 32 0x080 0x4806 A080 0x4806 C080 0x4902 0080 Table 19 40 UART IrDA CIR Register Summary Part 2 Register Width Register Name Type Address Offset UART4 Physical Address Bits DLL_REG RW 32 0x000 0x4904 2000 RHR_REG R 32 0x000 0x4904 2000 ...

Page 2930: ... 0x4904 2040 SSR_REG R 32 0x044 0x4904 2044 EBLR_REG RW 32 0x048 N A MVR_REG R 32 0x050 0x4904 2050 SYSC_REG RW 32 0x054 0x4904 2054 SYSS_REG R 32 0x058 0x4904 2058 WER_REG RW 32 0x05C 0x4904 205C CFPS_REG RW 32 0x060 N A RXFIFO_LVL_REG R 32 0x064 0x4904 2064 TXFIFO_LVL_REG R 32 0x068 0x4904 2068 IER2_REG RW 32 0x06C 0x4904 206C ISR2_REG RW 32 0x070 0x4904 2070 MDR3_REG RW 32 0x080 0x4904 2080 293...

Page 2931: ...0 RESERVED CLOCK_LSB Bits Field Name Description Type Reset 31 8 Reserved Read returns 0 R 0x000000 7 0 CLOCK_LSB Stores the 8 bit LSB divisor value RW 0x00 Table 19 42 Register Call Summary for Register DLL_REG UART IrDA CIR Functional Description FIFO DMA Mode Operation 0 Register Access Modes 1 2 3 4 UART IrDA SIR MIR FIR CIR Mode Selection 5 6 7 8 9 10 11 12 13 14 15 16 UART Mode 17 18 19 IrDA...

Page 2932: ...ter Call Summary for Register RHR_REG UART IrDA CIR Functional Description FIFO Management 0 1 Register Access Modes 2 UART IrDA SIR MIR FIR CIR Mode Selection 3 4 UART Mode 5 6 7 8 9 10 11 IrDA Mode UART3 Only 12 13 14 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 15 16 UART IrDA CIR Register Description 17 18 19 20 21 22 23 Table 19 45 THR_REG Address Offset 0x000 Physical Address...

Page 2933: ...TS_IT RTS_IT THR_IT RHR_IT XOFF_IT LINE_STS_IT SLEEP_MODE MODEM_STS_IT Bits Field Name Description Type Reset 15 8 Reserved Read returns 0x00 Write has no functional effect RW 0x00 7 CTS_IT Can be written only when EFR_REG 4 1 RW 0 0x0 Disables the nCTS interrupt 0x1 Enables the nCTS interrupt 6 RTS_IT Can be written only when EFR_REG 4 1 RW 0 0x0 Disables the interrupt 0x1 Enables the nRTS interr...

Page 2934: ...36 37 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 38 39 UART IrDA CIR Register Description 40 41 42 43 44 CIR Bit Field Details 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED THR_IT RHR_IT RESERVED RX_STOP_IT TX_STATUS_IT RX_OVERRUN_IT Bits Field Name Description Type Reset 31 6 Reserved Read returns 0 Write has no functional effect ...

Page 2935: ...tatus interrupt 5 TX_STATUS_IT TX_STATUS_IT interrupt reflects two possible conditions RW 0 The MDR2_REG 0 must be read to determine the status in the event of this interrupt 0x0 Disables the TX status interrupt 0x1 Enables the TX status interrupt 4 STS_FIFO_ TRIG_IT RW 0 0x0 Disables status FIFO trigger level interrupt 0x1 Enables status FIFO trigger level interrupt 3 RX_OVERRUN_ IT RW 0 0x0 Disa...

Page 2936: ...x00 Table 19 50 Register Call Summary for Register DLH_REG UART IrDA CIR Functional Description FIFO DMA Mode Operation 0 Register Access Modes 1 2 3 4 UART IrDA SIR MIR FIR CIR Mode Selection 5 6 7 8 9 10 11 12 13 14 15 16 UART Mode 17 18 19 IrDA Mode UART3 Only 20 UART Mode Power Management 21 22 UART IrDA CIR Basic Programming Model Quick start 23 24 25 26 27 SIR Mode 28 29 30 31 32 33 34 35 MI...

Page 2937: ...cters 0x1 16 characters 0x2 32 characters 0x3 56 characters 3 DMA_MODE Can be changed only when the baud clock is not running W 0 DLL_REG and DLH_REG set to 0 This register is considered if SCR_REG 0 0 0x0 DMA_MODE 0 No DMA 0x1 DMA_MODE 1 UART_NDMA_REQ 0 in TX UART_NDMA_REQ 1 in RX 2 TX_FIFO_CLEAR Clears the TX FIFO W 0 0x0 No change 0x1 Clears the transmit FIFO and resets its counter logic to 0 R...

Page 2938: ...source of the interrupt in a prioritized manner Note An interrupt source can be flagged only if enabled in the IER_REG register Type R UART Bit Field Details 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IT_TYPE IT_PENDING FCR_MIRROR Bits Field Name Description Type Reset 15 8 Reserved Read returns 0x00 R 0x00 7 6 FCR_MIRROR Mirror the contents of F...

Page 2939: ..._IT Bits Field Name Description Type Reset 15 8 Reserved Read returns 0x00 R 0x00 7 6 Reserved Read returns 0x0 R 0x0 5 TX_STATUS_IT R 0 0x0 TX status interrupt inactive 0x1 TX status interrupt active 4 RESERVED Not used in CIR mode R 0 3 RX_OE_IT R 0 0x0 THR interrupt inactive 0x1 THR interrupt active 2 RX_STOP_IT R 0 0x0 Receive stop interrupt is inactive 0x1 Receive stop interrupt is active 1 T...

Page 2940: ...RX FIFO interrupt active 1 THR_IT R 0 0x0 THR interrupt inactive 0x1 THR interrupt active 0 RHR_IT R 0 0x0 RHR interrupt inactive 0x1 RHR interrupt active Table 19 55 EFR_REG Address Offset 0x008 Physical Address See Table 19 39 to Table 19 40 Description Enhanced feature register This register enables or disables enhanced features Most enhanced functions apply only to UART modes but EFR_REG 4 ena...

Page 2941: ... bits 7 5 0x1 Enables writing to IER_REG bits 7 4 FCR_REG bits 5 4 and MCR_REG bits 7 5 3 0 SW_FLOW_ Combinations of software flow control can be selected by RW 0x0 CONTROL programming bit 3 0 See Table 19 32 In IrDA mode bits 1 0 select IR address to check See Section 19 2 5 2 1 7 IR Address Checking Table 19 56 Register Call Summary for Register EFR_REG UART IrDA CIR Environment IrDA Protocol an...

Page 2942: ...rced to 0 and remains in this state as long as LCR_REG 6 1 0x0 Normal operating condition 0x1 Forces the transmitter output to go low to alert the communication terminal TX line is forced to 0 and remains in this state while BREAK_EN 1 5 PARITY_TYPE2 Selects the forced parity format if LCR_REG 3 1 RW 0 UART mode only If LCR_REG 5 1and LCR_REG 4 0 the parity bit is forced to 1 in the transmitted an...

Page 2943: ...08 109 110 111 112 113 114 Table 19 59 MCR_REG Address Offset 0x010 Physical Address See Table 19 39 to Table 19 40 Description Modem control register MCR_REG 3 0 controls the interface with the modem data set or peripheral device that is emulating the modem Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RTS DTR XON_EN TCR_TLR RESERVED RI_STS...

Page 2944: ...escription Register Access Modes 2 3 4 5 6 7 8 9 10 11 UART IrDA SIR MIR FIR CIR Mode Selection 12 13 14 15 16 17 UART Mode 18 19 UART IrDA CIR Basic Programming Model Quick start 20 21 22 23 24 Hardware and Software Flow Control Configuration 25 26 27 28 29 30 31 32 33 34 35 36 SIR Mode 37 MIR Mode 38 39 40 41 42 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 43 44 UART IrDA CIR Reg...

Page 2945: ... Name Description Type Reset 31 8 Reserved Read returns 0 R 0x000000 7 RX_FIFO_STS R 0 0x0 Normal operation 0x1 At least one parity error framing error or break indication in the RX FIFO Bit 7 is cleared when no errors are present in the RX FIFO 6 TX_SR_E R 1 0x0 Transmitter hold TX FIFO and shift registers are not empty 0x1 Transmitter hold TX FIFO and shift registers are empty 5 TX_FIFO_E R 1 0x...

Page 2946: ...Polled Mode Operation 3 Register Access Modes 4 5 UART IrDA SIR MIR FIR CIR Mode Selection 6 7 8 9 10 11 UART Mode 12 13 14 15 16 17 18 19 20 IrDA Mode UART3 Only 21 22 23 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 24 25 UART IrDA CIR Register Description 26 27 CIR Bit Field Details 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RES...

Page 2947: ...It is used to determine the frame boundary It is cleared on a single read of the LSR_REG register 4 FRAME_TOO_ Frame too long R 0 LONG 0x0 No frame too long error in frame 0x1 Frame too long error in the frame at the top of the STATUS FIFO next character to be read This bit is set to 1 when a frame exceeding the maximum length set by RXFLH_REG and RXFLL_REG registers is received When this error is...

Page 2948: ...Hardware and Software Flow Control Configuration 8 9 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 10 11 Table 19 67 XOFF1_REG Address Offset 0x018 Physical Address See Table 19 39 to Table 19 40 Description UART mode XOFF1 character Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED XOFF_WORD1 Bits Field Name Description Type Rese...

Page 2949: ... 3 Register Access Modes 4 5 6 7 8 9 UART IrDA SIR MIR FIR CIR Mode Selection 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 UART Mode 28 29 30 31 32 33 UART IrDA CIR Basic Programming Model Hardware and Software Flow Control Configuration 34 35 36 37 38 39 40 41 42 43 44 45 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 46 47 UART IrDA CIR Register Description 48 49 Table 19 ...

Page 2950: ...UART Interface Description 0 1 UART IrDA CIR Functional Description Register Access Modes 2 3 UART IrDA SIR MIR FIR CIR Mode Selection 4 5 6 7 8 9 UART Mode 10 11 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 12 13 UART IrDA CIR Register Description 14 15 Table 19 73 SPR_REG Address Offset 0x01C Physical Address See Table 19 39 to Table 19 40 Description Scratchpad register This rea...

Page 2951: ...T IrDA CIR Basic Programming Model Hardware and Software Flow Control Configuration 4 5 6 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 7 8 Table 19 77 TLR_REG Address Offset 0x01C Physical Address See Table 19 39 to Table 19 40 Description Trigger level register Stores the programmable transmit and receive FIFO trigger levels used for DMA and IRQ generation Type RW 31 30 29 28 27 2...

Page 2952: ...e value of MDR1_REG 2 0 must not be changed again during normal operation Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SCT SET_TXIR IR_SLEEP SIP_MODE MODE_SELECT FRAME_END_MODE Bits Field Name Description Type Reset 31 8 Reserved Read returns 0 R 0x000000 7 FRAME_END_ IrDA mode only RW 0 MODE 0x0 Frame length method 0x1 Set EOT bit method 6...

Page 2953: ...16 17 18 19 20 21 22 23 24 25 26 UART Mode 27 28 29 IrDA Mode UART3 Only 30 31 32 33 34 35 CIR Mode UART3 Only 36 UART IrDA CIR Basic Programming Model Quick start 37 38 39 SIR Mode 40 41 42 43 44 MIR Mode 45 46 47 48 49 50 51 52 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 53 54 UART IrDA CIR Register Description 55 56 57 58 59 Table 19 81 MDR2_REG Address Offset 0x024 Physical Ad...

Page 2954: ...se width of 6 from 12 cycles 3 UART_PULSE UART mode only Used to allow pulse shaping in UART RW 0 mode 0x0 Normal UART mode 0x1 UART mode with pulse shaping 2 1 STS_FIFO_TRIG Only for IR IrDA mode RW 0x00 Frame status FIFO threshold select 0x0 1 entry 0x1 4 entries 0x2 7 entries 0x3 8 entries 0 IRTX_UNDERRUN IrDA transmission status interrupt When the IIR_REG 5 R 0 interrupt occurs the meaning of ...

Page 2955: ... Write has no functional effect W 0x000000 7 0 TXFLL LSB register used to specify the frame length W 0x00 Table 19 84 Register Call Summary for Register TXFLL_REG UART IrDA CIR Functional Description Register Access Modes 0 1 2 UART IrDA SIR MIR FIR CIR Mode Selection 3 4 5 IrDA Mode UART3 Only 6 UART IrDA CIR Basic Programming Model SIR Mode 7 MIR Mode 8 9 UART IrDA CIR Register Manual UART IrDA ...

Page 2956: ...ription FIFO Management 0 Register Access Modes 1 2 3 UART IrDA SIR MIR FIR CIR Mode Selection 4 5 6 IrDA Mode UART3 Only 7 8 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 9 10 UART IrDA CIR Register Description 11 12 Table 19 87 RESUME_REG Address Offset 0x02C Physical Address See Table 19 39 to Table 19 40 Description IR IrDA and IR CIR modes only This register is used to clear in...

Page 2957: ...ds the LSBs and TXFLH_REG holds the MSBs The frame length value is used if the frame length method of frame closing is used Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TXFLH Bits Field Name Description Type Reset 31 5 Reserved Read returns 0 R 0x0000000 4 0 TXFLH MSB register used to specify the frame length W 0x00 Table 19 90 Register Call...

Page 2958: ...CIR Functional Description Register Access Modes 0 1 2 UART IrDA SIR MIR FIR CIR Mode Selection 3 4 5 UART IrDA CIR Basic Programming Model MIR Mode 6 7 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 8 9 UART IrDA CIR Register Description 10 11 12 13 14 15 16 Table 19 93 SFREGL_REG Address Offset 0x030 Physical Address See Table 19 39 to Table 19 40 Description Status FIFO register l...

Page 2959: ...ist The LSBs are read from SFREGL_REG and the MSBs are read from SFREGH_REG Reading these registers does not alter the status FIFO read pointer These registers must be read before the pointer is incremented by reading the SFLSR_REG Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED SFREGH Bits Field Name Description Type Reset 31 4 Reserv...

Page 2960: ...Functional Description Register Access Modes 0 1 2 UART IrDA SIR MIR FIR CIR Mode Selection 3 4 5 UART IrDA CIR Basic Programming Model MIR Mode 6 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 7 8 UART IrDA CIR Register Description 9 10 11 12 13 14 15 Table 19 99 BLR_REG Address Offset 0x038 Physical Address See Table 19 39 to Table 19 40 Description BOF control register IrDA modes ...

Page 2961: ...s by characters and the type of parity in UART autobauding mode In autobauding mode the input frequency of the UART modem must be fixed to 48 MHz Any other module clock frequency results in incorrect baud rate recognition Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SPEED PARITY_TYPE BIT_BY_CHAR Bits Field Name Description Type Reset 31 8 Re...

Page 2962: ...ABORT_EN PULSE_TYPE DIS_TX_UNDERRUN Bits Field Name Description Type Reset 31 8 Reserved Read returns 0 R 0x00 7 PULSE_TYPE SIR pulse width select RW 0 0x0 3 16 of baud rate pulse width 0x1 1 6 µs 6 SD_MOD Primary output used to configure transceivers Connected to RW 0 the SD MODE input pin of IrDA transceivers 0x0 SD pin is set to high 0x1 SD pin is set to low 5 DIS_IR_RX RW 0 0x0 Normal operatio...

Page 2963: ...e MPU writes to the THR_REG TX FIFO Table 19 104 Register Call Summary for Register ACREG_REG UART IrDA CIR Environment UART3 Interface Description 0 IrDA Protocol and Data Format 1 2 3 4 CIR Interface Description 5 UART IrDA CIR Functional Description Register Access Modes 6 7 UART IrDA SIR MIR FIR CIR Mode Selection 8 9 10 11 IrDA Mode UART3 Only 12 13 14 15 16 17 18 CIR Mode UART3 Only 19 20 UA...

Page 2964: ...d when TX FIFO and TX shift register are empty 2 1 DMA_MODE_2 Specifies the DMA mode valid if SCR_REG 0 1 RW 0x0 0x0 DMA mode 0 no DMA 0x1 DMA mode 1 UARTi_DMA_TX UARTi_DMA_RX 0x2 DMA mode 2 UARTi_DMA_RX 0x3 DMA mode 3 UARTi_DMA_TX 0 DMA_MODE_ RW 0 CTL 0x0 The DMA_MODE is set with FCR_REG 3 0x1 The DMA_MODE is set with SCR_REG 2 1 Table 19 106 Register Call Summary for Register SCR_REG UART IrDA C...

Page 2965: ...ounter will be reset if corresponding FIFO is reset via FCR 1 or FCR 2 1 RX_CTS_DSR_WAKE_UP_STS Pin falling edge detection Reset only when SCR_REG 4 R 0 is reset to 0 0x0 No falling edge event on RX nCTS and nDSR 0x1 A falling edge occurred on RX nCTS or nDSR 0 TX_FIFO_FULL TX FIFO status R 0 0x0 TX FIFO is not full 0x1 TX FIFO is full Table 19 108 Register Call Summary for Register SSR_REG UART I...

Page 2966: ...6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EBLR Bits Field Name Description Type Reset 31 8 Reserved Read returns 0 R 0x000000 7 0 EBLR IR IrDA mode This register allows definition of up to 176 RW 0x00 xBOFs the maximum required by IrDA specification IR CIR mode N A 0x00 Feature disabled 0x01 Generate RX_STOP interrupt after receiving one zero bit 0xFF Generate ...

Page 2967: ...ter MVR_REG UART IrDA CIR Functional Description Register Access Modes 0 1 2 UART IrDA SIR MIR FIR CIR Mode Selection 3 4 5 6 7 8 9 10 11 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 12 13 UART IrDA CIR Register Description 14 15 Table 19 113 SYSC_REG Address Offset 0x054 Physical Address See Table 19 39 to Table 19 40 Description System configuration register The auto idle bit con...

Page 2968: ...ccess Modes 2 3 4 5 6 7 UART IrDA SIR MIR FIR CIR Mode Selection 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 UART Mode Power Management 26 UART IrDA CIR Basic Programming Model Quick start 27 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 28 29 Table 19 115 SYSS_REG Address Offset 0x058 Physical Address See Table 19 39 to Table 19 40 Description System status register Type R ...

Page 2969: ...5 4 3 2 1 0 RESERVED RESERVED RESERVED EVENT_2_RI_ACTIVITY EVENT_4_RX_ACTIVITY EVENT_0_CTS_ACTIVITY EVENT_7_TX_WAKEUP_EN EVENT_5_RHR_INTERRUPT EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT Bits Field Name Description Type Reset 31 8 Reserved Read returns 0x00 R 0x000000 7 EVENT_7_TX_WAKEUP_EN Receiver line status interrupt RW 1 0x0 Event is not allowed to wake up the system 0x1 EVENT CAN WAKE UP THE SYST...

Page 2970: ...FPS Bits Field Name Description Type Reset 31 8 Reserved Read returns 0 R 0x000000 7 0 CFPS Because the consumer IR works at modulation rates of 30 56 8 kHz the RW 0x69 48 MHz clock must be prescaled before the clock can drive the IR logic This register sets the divisor rate to give a range to accommodate remote control requirements in BAUD multiples of 12x The value of the CFPS at reset is 0105 d...

Page 2971: ...20 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 21 22 Table 19 123 TXFIFO_LVL_REG Address Offset 0x068 Physical Address Instance UART See Table 19 39 to Table 19 40 Description Level of the TX FIFO Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED TXFIFO_LVL Bits Field Name Description Type Reset 31 8 Reserved Read returns 0x00 R ...

Page 2972: ... empty corresponding interrupt RW 0 0x0 Enables EN_RXFIFO_EMPTY interrupt 0x1 Disables EN_RXFIFO_EMPTY interrupt Table 19 126 Register Call Summary for Register IER2_REG UART IrDA CIR Functional Description Register Access Modes 0 1 2 3 4 5 UART IrDA SIR MIR FIR CIR Mode Selection 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 UART IrDA CIR Register Manual UART IrDA CIR Register Summary 24 25 T...

Page 2973: ... Manual UART IrDA CIR Register Summary 24 25 Table 19 129 MDR3_REG Address Offset 0x080 Physical Address Instance UART See Table 19 39 to Table 19 40 Description Mode definition register 3 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DISABLE_CIR_RX_DEMOD Bits Field Name Description Type Reset 31 1 Reserved Read returns 0 R 0x0000000 0 DISAB...

Page 2975: ...odules Topic Page 20 1 McSPI Overview 2976 20 2 McSPI Environment 2979 20 3 McSPI Functional Interface 2982 20 4 McSPI Integration 2987 20 5 McSPI Functional Description 2991 20 6 McSPI Basic Programming Model 3012 20 7 McSPI Register Manual 3033 2975 SWPU177N December 2009 Revised November 2010 Multichannel SPI Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2976: ...als SPI2 and SPI3 support up to two peripherals and SPI4 supports only one peripheral NOTE In this chapter m 1 4 represents the module instance and x represents the channel in signal and register naming There are four McSPI instances Each module instance has different channel numbers SPI1 4 channels if m 1 x 4 SPI2 2 channels if m 2 x 2 SPI3 2 channels if m 3 x 2 SPI4 1 channel if m 4 x 1 2976 Mul...

Page 2977: ...PRCM MPU SS INT System DMA PRCM MPU SS INT System DMA PRCM L4 interconnect L4 interconnect Public Version www ti com McSPI Overview Figure 20 1 Multichannel Modules SPI1 SPI2 SPI3 and SPI4 The McSPI instances include the following main features Serial clock with programmable frequency polarity and phase for each channel Wide selection of SPI word lengths ranging from 4 bits to 32 bits Up to four m...

Page 2978: ...ement through wake up capabilities Enable the addition of a programmable start bit for SPI transfer per channel start bit mode Support start bit write command Support start bit pause and break sequence 64 bytes built in FIFO available for a single channel Force CS mode for continuous transfers 2978 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments ...

Page 2979: ...m transistor TFT liquid crystal display LCD with a light emitting diode LED front light a four wire resistive touch screen panel and LCD controllers This chipset is associated with the TSC2005 or TSC2006 touch screen controller powered by a TWL4030 power management unit and driven by the device The McSPI device interface is set to master mode the touch screen McSPI controller interface operates in...

Page 2980: ...Mode Full Duplex NOTE In this case m 1 3 Figure 20 4 shows the master single mode which can also be configured in receive only mode Figure 20 4 McSPI Master Single Mode Receive Only 20 2 2 SPI Interface in Slave Mode Figure 20 5 shows a case in slave mode full duplex NOTE Only channel 0 can be configured as slave and only spin_cs0 can be used as a chip enable in slave mode 2980 Multichannel SPI SW...

Page 2981: ...ric SPI master device SCLK MI CS Public Version www ti com McSPI Environment Figure 20 5 McSPI Slave Mode Full Duplex Figure 20 6 shows the slave single mode which can also be configured in transmit only mode Figure 20 6 McSPI Slave Single Mode Transmit Only 2981 SWPU177N December 2009 Revised November 2010 Multichannel SPI Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2982: ...le serial data master out Unknown slave input master output spim_somi I SPIm module serial data master input slave output master input spim_csx O SPIm module chip select x output Low 1 After reset the SPI modules are in slave mode by default This paragraph implies that the McSPI module is configured in slave mode See the MCSPI_MODULCTRL 2 MS bit in the module control register MCSPI_MODULCTRL 2 Thi...

Page 2983: ...spim_csx for channel x of instance m The polarity of the SPI enable signals is programmable SPIm MCSPI_CHxCONF 6 EPOL bit spim_csx signals can be active high or low The assertion of the spim_csx signals is programmable and can be manually or automatically asserted The manual assertion mode is available in single master mode only spim_csx can be kept active between words with the SPIm MCSPI_CHxCONF...

Page 2984: ...g occurs on the falling edge 1 0 Mode 2 spim_clk is active low and sampling occurs on the falling edge 1 1 Mode 3 spim_clk is active low and sampling occurs on the rising edge Figure 20 9 Phase and Polarity Combinations 20 3 3 1 Transfer Format In both master and slave modes McSPI drives the data lines when spim_csx is asserted Each word is transmitted starting with the most significant bit MSB Th...

Page 2985: ...e data output pin is valid on the following spim_clk edge one half cycle later This is the sampling edge for the master and slave A synchronization delay is added between the spim_csx activation and the first spim_clk edge The received data bit is shifted into the shift register on the third spim_clk edge This process continues for a number of pulses on the spim_clk line defined by the SPI word le...

Page 2986: ...ad 1 2 3 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D CX MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB D CX MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB Public Version McSPI Functional Interface www ti com Figure 20 11 Extended SPI Transfer With a Start Bit SBE 1 2986 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 2987: ... clock CORE_L4_ICLK L4 interconnect SPIm_FCLK is the McSPI module m functional clock and is used to clock the McSPI internal logic The source of SPIm_FCLK is the PRCM CORE_48M_FCLK output clock SPIm_ICLK is the McSPI module m interface clock and is used to synchronize the McSPI L4 port to the L4 interconnect All accesses from the interconnect are synchronous with SPIm_ICLK The source of SPIm_ICLK ...

Page 2988: ...agement see Section 20 5 7 20 4 2 2 Power Domain The McSPI modules belong to the CORE power domain see Table 20 6 Table 20 6 Power Domain Peripherals Power Domain McSPI modules CORE power domain 20 4 2 3 Hardware Reset As part of the CORE power domain CORE_RST is issued by the PRCM module for more information about the CORE power domain implementation and CORE_RST signal see Chapter 3 Power Reset ...

Page 2989: ...DMA_TX1 S_DMA_36 SPI1_DMA_RX1 S_DMA_37 SPI1_DMA_TX2 S_DMA_38 SPI1_DMA_RX2 S_DMA_39 SPI1_DMA_TX3 S_DMA_40 SPI1_DMA_RX3 S_DMA_41 SPI2 4 SPI2_DMA_TX0 S_DMA_42 Destination is sDMA SPI2_DMA_RX0 S_DMA_43 SPI2_DMA_TX1 S_DMA_44 SPI2_DMA_RX1 S_DMA_45 SPI3 4 SPI3_DMA_TX0 S_DMA_14 Destination is sDMA SPI3_DMA_RX0 S_DMA_15 SPI3_DMA_TX1 S_DMA_22 SPI3_DMA_RX1 S_DMA_23 SPI4 2 SPI4_DMA_TX0 S_DMA_69 Destination is...

Page 2990: ...tion the MPU interrupt controller SPI4 1 SPI4_IRQ M_IRQ_48 Destination is the MPU interrupt controller 20 4 3 3 Wake Up Requests Table 20 10 lists the wake up requests Table 20 10 Wake Up Requests Attributes Wake Request Name Mapping Comments SPI1 1 spi1_cs0 SPI1_ SWAKEUP Destination is the PRCM module SPI2 1 spi2_cs0 SPI2_ SWAKEUP Destination is the PRCM module SPI3 1 spi3_cs0 SPI3_ SWAKEUP Desti...

Page 2991: ...in SPI CKDIV or slave domain SPI interface 0 1 Input select SPI slave RX buffer Shift register Clock div Bit count SPI master SPIMASTERGZEN SPIDATAGZEN SPICLKI SPIENI SPICLKO SPIENO From L4 interconnect SPI status SYNCHRO FIFO spim_somi spim_csx spim_clk McSPI block digram SPIDATO SPIDATI 1 SPIDATI 0 spim_simo Public Version www ti com McSPI Functional Description 20 5 McSPI Functional Description...

Page 2992: ...the rules and searches in the rotation for the next enabled channel Rule 1 Only enabled channels the SPIm MCSPI_CHxCTRL 0 EN bit can be scheduled for transmission and or reception Rule 2 If its MCSPI_TXx transmitter register is not empty the SPIm MCSPI_CHxSTAT 1 TXS bit an enabled channel can be scheduled when the shift register is assigned If the MCSPI_TXx register is empty when the shift registe...

Page 2993: ...s not applicable In master transmit only mode the MCSPI_RXx register state FULL does not prevent transmission and the MCSPI_RXx register is always overwritten with the new SPI word This event is not significant when only transmission is meaningful Thus the RX0_OVERFLOW bit in the SPIm MCSPI_IRQSTATUS register is never set in this mode The hardware automatically disables the RX_FULL interrupt and t...

Page 2994: ...going Wait for completion of the SPI word transfer wait until the SPIm MCSPI_CHxSTAT 2 EOT bit is set to 1 before disabling the current channel and enabling a different channel Disable the current channel first and then enable the other channel 20 5 2 5 2 Force spim_csx Mode Continuous transfers are manually allowed by keeping the spim_csx signal active for successive SPI words transfer Several se...

Page 2995: ...other receive only for instance must be handled by software At the end of the last SPI word the channel must be deactivated the SPIm MCSPI_CHxCTRL 0 EN bit set to 0 and spim_csx can be forced to its inactive state using the SPIm MCSPI_CHxCONF 20 FORCE bit Figure 20 15 and Figure 20 16 show successive transfers with spim_csx maintained active low with a different configuration for each SPI word in ...

Page 2996: ...a command or as data This feature is only available in master mode The start bit mode cannot be used at the same time as turbo mode and or force spim_csx mode In this case only one channel can be used round robin arbitration is not possible This mode is programmable per channel by setting the SPIm MCSPI_CHxCONF 23 SBE bit to 1 The polarity of the extended bit is programmable per channel When the S...

Page 2997: ...2 8 1 Clock Ratio Granularity By default the clock division ratio is defined by the SPIm MCSPI_CHxCONF 5 2 CLKD bit field with power of two granularity leading to a clock division in range 1 to 4096 in this case the duty cycle is always 50 With the SPIm MCSPI_CHxCONF 29 CLKG bit clock division granularity can be changed to one clock cycle in that case the SPIm MCSPI_CHxCTRL 15 8 EXTCLK bit field i...

Page 2998: ...6 0 3 1 4 X X 41 6 41 6 83 2 50 50 12 5 0 1 81 1 0 852 8 832 1684 8 50 6 49 4 0 592 5 7 1 88 X X 915 2 915 2 1830 4 50 50 0 545 20 5 3 Slave Mode To select the McSPI slave mode set the SPIm MCSPI_MODULCTRL 2 MS bit A McSPI slave device can be connected to up to four external SPI master devices but handles transactions with one SPI master device at a time In slave mode the McSPI initiates data tran...

Page 2999: ... of channel 0 is always loaded into the shift register whether its content is updated or not The MCSPI_TXx register must be loaded before McSPI is selected by a master Its own receiver register SPIm MCSPI_RXx with x 0 on top of the common receive shift register If the MCSPI_RXx register is full the SPIm MCSPI_CHxSTAT 0 RXS bit with x 0 is set NOTE The MCSPI_TXx register and MCSPI_RXx registers of ...

Page 3000: ... it is updated or not The event TXx_UNDERFLOW is activated accordingly and does not prevent transmission When an SPI word transfer completes the SPIm MCSPI_CHxSTAT0 2 EOT bit with x 0 set to 1 the received data is transferred to the channel receive register To use McSPI as a slave transmit only device the RXx_FULL and RX0_OVERFLOW interrupts and DMA read requests must be disabled due to the MCSPI_...

Page 3001: ...revent transmission When an SPI word transfer completes the SPIm MCSPI_CHxSTAT0 2 EOT bit with x 0 is set to 1 the received data is transferred to the channel receive register To use the McSPI as a slave receive only device the TXx_EMPTY and TXx_UNDERFLOW interrupts and the DMA write requests must be disabled due to the MCSPI_TXx register state For a full duplex transmission the serial clock spim_...

Page 3002: ...EW bit to 1 If several channel are selected and several FIFO enable bit fields set to 1 the controller forces buffer not to be used it is the responsibility of the driver to set only one FIFO enable bit field The buffer can be used in the modes defined below Master or Slave mode Transmit only Receive only or Transmit Receive mode Single channel or turbo mode or in normal round robin mode In round ...

Page 3003: ...elationship SPI Word Length WL 3 WL 7 8 WL 15 16 WL 31 Number of byte written in 1 byte 2 bytes 4 bytes the FIFO The FIFO buffer pointers are reset when the corresponding channel is enabled or FIFO configuration changes 20 5 4 1 Buffer Almost Full The MCSPI_XFERLEVEL 13 8 AFL bit field is needed when the buffer is used to receive SPI word from a slave MCSPI_CHxCONF 28 FFER bit must be set to 1 It ...

Page 3004: ... transmit SPI word to a slave MCSPI_CHxCONF 27 FFEW bit must be set to 1 It defines the Almost Empty buffer status See Figure 20 25 When FIFO pointer has not reached this level an interrupt or a DMA request is sent to the MPU to enable system to write AEL 1 bytes to Transmit register Be careful AEL 1 must correspond to a multiple value of MCSPI_CHxCONF 11 7 WL bit field When DMA is used the reques...

Page 3005: ... x 0 3 that indicate if service is required Each status bit has an interrupt enable bit a mask in the SPIm MCSPI_IRQENABLE register RXx_FULL_ENABLE TXx_UNDERFLOW_ENABLE TXx_EMPTY_ENABLE When an interrupt occurs and a mask is later applied on it the interrupt line is not asserted again even if the interrupt source is not serviced The McSPI supports interrupt driven and polling operations 20 5 5 1 I...

Page 3006: ...FO This interrupt is raised when the controller had performed the number of transfer defined in the MCSPI_XFERLEVEL 31 16 WCNT bit field If WCNT is set to 0x0000 the counter is not enable and this interrupt is not generated The End of Word count interrupt also indicates that the SPI transfer is halt on channel using the FIFO buffer as soon as MCSPI_XFERLEVEL 31 16 WCNT is not reloaded and the chan...

Page 3007: ...U to perform the right number of reads 20 5 5 2 4 RX0_OVERFLOW The RX0_OVERFLOW event is activated in slave mode in either transmit and receive or receive only mode when a channel is enabled and the MCSPI_RXx register or FIFO is full when a new SPI word is received The MCSPI_RXx register is always overwritten with the new SPI word If the FIFO is enabled data within the FIFO are overwritten it must...

Page 3008: ...cesses The sDMA controller advantage is to lower the MPU charge for data transfers Each McSPI channel can issue DMA requests if they are enabled There are two DMA request lines per McSPI channel one for read and one for write The DMA read request line is asserted when the McSPI channel is enabled and new data is available in the receive register of the McSPI channel A DMA read request can be indiv...

Page 3009: ...est basing its decision on its internal activity Namely the acknowledge signal is asserted only when all pending transactions IRQs or DMA requests are treated This is the best approach for an efficient system power management When configured in smart idle mode the McSPI module also offers an additional granularity on the CORE_48M_FCLK and CORE_L4_ICLK gating The SPIm SYSCONFIG 9 8 CLOCKACTIVITY bi...

Page 3010: ...irst received SPI word must be read from the SPIm MCSPI_RXx register with x 0 before the completion of the second SPI word serialization Table 20 15 lists the supported cases in wake up mode Table 20 15 Smart Idle Mode and Wake Up Capabilities Mode Interface Clock SPI Clock Ref Functionality Wake Up Event Master Must be Must be Full functionality but the module does No wake up event maintained mai...

Page 3011: ...ally inhibited even if both the SPIm MCSPI_SYSCONFIG 2 ENAWAKEUP and SPIm MCSPI_WAKEUPENABLE 0 WKEN bits are set The transition from normal mode to idle mode does not affect the interrupt event bits of the SPIm MCSPI_IRQSTATUS register In force idle mode the module must be disabled so the interrupt and DMA request lines are likely deasserted The interface clock and SPI clock provided to the McSPI ...

Page 3012: ...ow NOTE Before the SPIm MCSPI_SYSSTATUS 0 RESETDONE bit is set the CLK and CLKSPIREF clocks must be provided to the module To avoid unpredictable behavior reset the module before changing from master mode to slave mode or vice versa 20 6 2 Transfer Procedures without FIFO In the subsections below the transfer procedures are described without FIFO using MCSPI_CHxCONF 27 28 FFER and FFEW 0 The McSPI...

Page 3013: ...tion Automatic manual For these flows the host process contains the main process and the interrupt routines The interrupt routines are called on the interrupt signals or by an internal call if the module is used in polling mode 20 6 2 1 Common Transfer Procedure Figure 20 27 shows the main sequence common to all transfers In multichannel master mode the flows of different channels can be run simul...

Page 3014: ...uence Minimum 1 1 1 1 1 1 number of words DMA transfer w w w w size 2 1 w number of words to transfer 2 w number of words to transfer The different sequences can be merged in one process to manage transfers of several types The end of transfer sequences are described from the start of the channel In these sequences and in later sections of this chapter some software variables are used WRITE_COUNT ...

Page 3015: ...SPI Basic Programming Model 20 6 2 3 Transmit and Receive Procedure Figure 20 28 shows the handling procedure for words received and transmitted by interrupt in master and slave modes The main process flow shows how the end of the transfer must be done after all words are received for this mode If the requests are configured in DMA WRITE_COUNT and READ_COUNT are assigned with the value w when the ...

Page 3016: ...ly Procedure 20 6 2 4 1 Based on Interrupt Requests Figure 20 29 shows the handling procedure for words transmitted by interrupt in transmit only mode The main process flow shows how the end of transfer must be done after all words are received for this mode Figure 20 29 Transmit Only With Interrupts Master and Slave 20 6 2 4 2 Transmit Only Based on DMA Write Requests In Figure 20 30 the main pro...

Page 3017: ...4 DMAW bit WRITE_COUNT w Yes No No Yes Yes No Public Version www ti com McSPI Basic Programming Model Figure 20 30 Transmit Only With DMA Master and Slave 20 6 2 5 Receive Only Procedure 20 6 2 5 1 Master Normal Receive Only Procedure 20 6 2 5 1 1 Based on Interrupt Requests Figure 20 31 shows the handling procedure for words received by interrupt in master normal receive only mode The main proces...

Page 3018: ...1 Read SPIm MCSPI_RXx READ_COUNT 1 Yes No mcspi 022 Public Version McSPI Basic Programming Model www ti com Figure 20 31 Receive Only With Interrupt Master Normal 20 6 2 5 1 2 Receive Only Based on DMA Read Requests In Figure 20 32 the main process shows the completion of a word transfer in receive only mode with DMA read requests When the DMA handler completes w 1 interface accesses READ_COUNT is...

Page 3019: ...te SPIm MCSPI_IRQSTATUS to reset channel status bits Yes Public Version www ti com McSPI Basic Programming Model Figure 20 32 Receive Only With DMA Master Normal 20 6 2 5 2 Master Turbo Receive Only Procedure 20 6 2 5 2 1 Based on Interrupt Requests Figure 20 33 shows the handling procedure for words received by interrupt in master turbo receive only mode The main process shows how the end of tran...

Page 3020: ...es Next command LAST_TRANSFER TRUE CHANNEL_ENABLE FALSE Interrupt routine Main process LAST_TRANSFER TRUE Public Version McSPI Basic Programming Model www ti com Figure 20 33 Receive Only With Interrupt Master Turbo 20 6 2 5 2 2 Based on DMA Read Requests In Figure 20 34 the main process shows the completion of a word reception in master turbo receive only mode with DMA write requests When the DMA...

Page 3021: ...HANNEL_ENABLE FALSE READ_COUNT w Read SPIm MCSPI_RXx READ_COUNT 1 No Yes No No Yes Yes No Yes Public Version www ti com McSPI Basic Programming Model Figure 20 34 Receive Only With DMA Master Turbo 20 6 2 5 3 Slave Receive Only Procedure Figure 20 35 shows the handling procedure for words received by interrupt in slave receive only mode The main process shows how the end of transfer must be done a...

Page 3022: ...CHxCTRL 0 EN bit to 0 RX full Read SPIm MCSPI_RXx READ_COUNT 1 Return No READ_COUNT w Yes Start the channel Set SPIm MCSPI_CHxCTRL 0 EN bit to 1 mcspi 035 Public Version McSPI Basic Programming Model www ti com Figure 20 35 Receive Only Slave 3022 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3023: ...ontrol signal active high for the exchange of 4 bit words synchronized with a SPI clock active low with a slower frequency than used with the first slave device Figure 20 36 Two SPI Transfers With PHA 0 Flexibility of McSPI This section details the steps required for this type of transmission 20 6 2 6 1 McSPI Initialization Sequence As shown in Figure 20 26 the McSPI module must first reset all re...

Page 3024: ...his section follows the flow of Figure 20 26 1 Initialize software variables WRITE_COUNT 0 and READ_COUNT 0 2 Initialize interrupts Write 0x7 in the SPI1 MCSPI_IRQSTATUS 3 0 field and set the SPI1 MCSPI_IRQENABLE 3 0 field to 0x7 3 Follow the steps described in Section 20 6 2 6 2 1 1 Mode Selection 4 If WRITE_COUNT w and READ_COUNT w write SPI1 MCSPI_CHxCTRL 0 0x0 x 0 to stop the channel This inte...

Page 3025: ...d simultaneously 20 6 3 Transfer Procedures with FIFO In the subsections below the transfer procedures are described with FIFO using MCSPI_CHxCONF 27 28 FFER or and FFEW 1 The MCSPI module allows the transfer of one or more words according to different modes Master normal master turbo slave Transmit and receive transmit only receive only Write and read requests Interrupts DMA For these flows the h...

Page 3026: ...NLY Yes No mcspi 041 Public Version McSPI Basic Programming Model www ti com Figure 20 37 Common Transfer Sequence Main Process The MCSPI module can start the transfer only after the first write request is released by writing the MCSPI_TXx register even in receive only mode only one write request occurs in this case This first write request can be managed by the IRQ routine or DMA handler as are a...

Page 3027: ...in the FIFO 1 2 or 4 bytes according to word length In these sequences the transfer to execute has a size of N words When accessing the FIFO only one word is written or read for each OCP access In these sequences the number of words written or read for each write or read FIFO request is write_request_size read_request_size If they are not submultiples of N the last request sizes are last_write_req...

Page 3028: ...t 0 Read read_request_size words from MCSPI_RXx read_count read_request_size RX full Yes No read_count 0 Yes No Read last_read_request_size words from MCSPI_RXx read_count 0 mcspi 042 Public Version McSPI Basic Programming Model www ti com Figure 20 38 Transmit Receive With Word Count 20 6 3 3 Transmit Receive Procedure Without Word Count WCNT 0 Figure 20 39 shows the flow of a transfer in transmi...

Page 3029: ...nt read_request_size RX full Yes No Read_count 0 Yes No Read last_read_request_size words from MCSPI_RXx read_count 0 read_count read_request_size Yes No last_request TRUE Read MCSPI_CHxSTAT FFxTXE and EOT Yes No Next command mcspi 046 Yes Public Version www ti com McSPI Basic Programming Model Figure 20 39 Transmit Receive Without Word Count 20 6 3 4 Transmit Only Procedure Figure 20 40 shows the...

Page 3030: ...PI_CHxSTAT FFxTXE and EOT Yes No mcspi 047 Next command Public Version McSPI Basic Programming Model www ti com Figure 20 40 Transmit Only The difference between word count enabled or not is the condition after starting the channel Word count enable Wait for EOW interrupt Word count disable Wait for write_count 0 20 6 3 5 Receive Only Procedure With Word Count WCNT 0 Figure 20 41 shows the flow of...

Page 3031: ...MCSPI_CHxCTRL ENx No Read read_request_size words from MCSPI_RXx read_count read_request_size Public Version www ti com McSPI Basic Programming Model Figure 20 41 Receive Only With Word Count 20 6 3 6 Receive Only Procedure Without Word Count WCNT 0 Figure 20 42 shows the flow of a transfer in receive only mode without word count 3031 SWPU177N December 2009 Revised November 2010 Multichannel SPI C...

Page 3032: ...request_size RX full Yes No read_count read_request_size Yes No last_request TRUE Read MCSPI_CHxSTAT RXx Yes No Next command read_count 0 Yes No Read 1 word from MCSPI_RXx read_count 1 mcspi 048 Public Version McSPI Basic Programming Model www ti com Figure 20 42 Receive Only Without Word Count 3032 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments...

Page 3033: ...809 8018 0x4809 A018 0x480B 8018 0x480B A018 MCSPI_IRQENABLE RW 0x1C 0x4809 801C 0x4809 A01C 0x480B 801C 0x480B A01C MCSPI_WAKEUPENABL RW 0x20 0x4809 8020 0x4809 A020 0x480B 8020 0x480B A020 E MCSPI_SYST RW 0x24 0x4809 8024 0x4809 A024 0x480B 8024 0x480B A024 MCSPI_MODULCTRL RW 0x28 0x4809 8028 0x4809 A028 0x480B 8028 0x480B A028 MCSPI_CHxCONF 1 RW 0x2C 0x4809 802C 0x4809 A02C 0x480B 802C 0x480B A...

Page 3034: ...ry for Register MCSPI_REVISION McSPI Register Manual McSPI Register Summary 0 Table 20 22 MCSPI_SYSCONFIG Address Offset 0x10 Physical Address 0x4809 8010 Instance MCSPI1 0x4809 A010 MCSPI2 0x480B 8010 MCSPI3 0x480B A010 MCSPI4 Description This register allows control of various parameters of the module interface It is not sensitive to software reset Type RW Write Latency Immediate 31 30 29 28 27 ...

Page 3035: ...h to wake up mode based on its internal activity and the wake up capability can be used if the bit MCSPI_SYSCONFIG ENAWAKEUP is set 0x3 Reserved do not use 2 ENAWAKEUP Wake up feature control RW 0 0x0 Wake up capability disabled 0x1 Wake up capability enabled 1 SOFTRESET Software reset Read always returns 0 RW 0 0x0 Normal mode 0x1 Trigger a module reset This bit is automatically reset by hardware...

Page 3036: ...egister Call Summary for Register MCSPI_SYSSTATUS McSPI Basic Programming Model Initialization of Modules 0 McSPI Configuration and Operations Example 1 McSPI Register Manual McSPI Register Summary 2 Table 20 26 MCSPI_IRQSTATUS Address Offset 0x18 Physical Address 0x4809 8018 Instance MCSPI1 0x4809 A018 MCSPI2 0x480B 8018 MCSPI3 0x480B A018 MCSPI4 Description The interrupt status regroups all the ...

Page 3037: ...t unchanged Read 0x0 Event false Write 0x1 Event status bit is reset Read 0x1 Event is pending 12 TX3_EMPTY MCSPI_TX3 register is empty only when channel 3 is RW 0x0 enabled 2 Write 0x0 Event status bit unchanged Read 0x0 Event false Write 0x1 Event status bit is reset Read 0x1 Event is pending 11 Reserved Read returns 0 RW 0x0 10 RX2_FULL MCSPI_RX2 register full only when channel 2 is enabled RW ...

Page 3038: ...ged Read 0x0 Event false Write 0x1 Event status bit is reset Read 0x1 Event is pending 2 RX0_FULL MCSPI_RX0 register full only when channel 0 is enabled RW 0x0 Write 0x0 Event status bit unchanged Read 0x0 Event false Write 0x1 Event status bit is reset Read 0x1 Event is pending 1 TX0_UNDERFLOW MCSPI_TX0 register underflow only when channel 0 is RW 0x0 enabled 4 Write 0x0 Event status bit unchange...

Page 3039: ...C MCSPI3 0x480B A01C MCSPI4 Description This register allows to enable disable the module internal sources of interrupt on an event by event basis Type RW Write Latency Immediate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WKE EOWKE Reserved Reserved Reserved RX3_FULL_ ENABLE RX2_FULL_ ENABLE RX1_FULL_ ENABLE RX0_FULL_ ENABLE TX3_EMPTY_ ENABLE TX2...

Page 3040: ...nterrupt disabled 0x1 Interrupt enabled 7 Reserved Read returns 0 RW 0x0 6 RX1_FULL_ ENABLE MCSPI_RX1 register full interrupt enable channel 1 RW 0x0 0x0 Interrupt disabled 0x1 Interrupt enabled 5 TX1_UNDERFLOW_ ENABLE MCSPI_TX1 register underflow interrupt enable channel RW 0x0 1 0x0 Interrupt disabled 0x1 Interrupt enabled 4 TX1_EMPTY_ ENABLE MCSPI_TX1 register empty interrupt enable channel 1 R...

Page 3041: ...diate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WKEN Bits Field Name Description Type Reset 31 1 Reserved Reads return 0 RW 0x00000000 0 WKEN Wake up functionality in slave mode when an active control signal RW 0 is detected on the spim_cs line programmed in the field MCSPI_CHxCONF SPIENSLV 0x0 The event is not allowed to wake up the system even...

Page 3042: ...atus bits contained in the MCSPI_IRQSTATUS register 10 SPIENDIR Set the direction of the spim_cs lines and spim_clk line RW 0 0x0 Output as in master mode 0x1 Input as in slave mode 9 SPIDATDIR1 Set the direction of the SPIDAT 1 spim_simo RW 0 0x0 Output 0x1 Input 8 SPIDATDIR0 Set the direction of the SPIDAT 0 spim_somi RW 0 0x0 Output 0x1 Input 7 WAKD SWAKEUP output signal data value of internal ...

Page 3043: ...direction the spim_cs2 line is driven high or low according to the value written into this register If MCSPI_SYST SPIENDIR 1 input mode direction this bit returns the value on the spim_cs2 line high or low and a write into this bit has no effect 1 SPIEN_1 spim_cs1 line signal data value RW 0 If MCSPI_SYST SPIENDIR 0 output mode direction the spim_cs1 line is driven high or low according to the val...

Page 3044: ...spim_clk and spim_cs for channel x 0x1 Slave The module receive 1 Reserved returns 0 after writing 0 returns 1 after writing 1 RW 0 0 SINGLE Single forced channel multichannel master mode only RW 0 0x0 One or more channels will be used in master mode with automatic chip select generation 0x1 Only one channel will be used in master mode and the chip select is driven by the MCSPI_CHxCONF 20 FORCE bi...

Page 3045: ...ock cycle ganularity 28 FFER FIFO enabled for Receive Only one channel can have this bit RW 0x0 field set 0x0 The buffer is not used to Receive data 0x1 The buffer is used to Receive data 27 FFEW FIFO enabled for Transmit Only one channel can have this bit RW 0x0 field set 0x0 The buffer is not used to Transmit data 0x1 The buffer is used to Transmit data 26 25 TCS Chip select time control RW 0x0 ...

Page 3046: ...MAR DMA Read request RW 0x0 The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0x0 DMA read request disabled 0x1 DMA read request enabled 14 DMAW DMA Write request RW 0x0 The DMA write request line is asserted when the c...

Page 3047: ... 31 bit long 0x1F The SPI word is 32 bit long 6 EPOL spim_csx polarity for channel x RW 0x0 0x0 spim_csx is held high during the active state 0x1 spim_csx is held low during the active state 5 2 CLKD Frequency divider for spim_clk for master device only RW 0x0 A programmable clock divider divides the SPI reference clock CLKSPIREF by a 4 bit value and results in a new spim_clk clock available to sh...

Page 3048: ... Configuration and Operations Example 58 59 60 61 62 63 64 65 66 67 Transfer Procedures with FIFO 68 McSPI Register Manual McSPI Register Summary 69 McSPI Register Description 70 71 72 73 74 75 76 77 78 79 80 81 Table 20 38 MCSPI_CHxSTAT Address Offset 0x30 0x14 x Index x 0 to 3 for MCSPI1 x 0 to 1 for MCSPI2 and MCSPI3 x 0 for MCSPI4 Physical Address 0x4809 8030 0x14 x Instance MCSPI1 0x4809 A030...

Page 3049: ...ter is loaded with the data from the MCSPI_TXx register beginning of transfer Read 0x1 This flag is automatically set to one at the end of an SPI transfer 1 TXS Channel x MCSPI_TXx register status R 0x0 Read 0x0 Register is full Read 0x1 Register is empty 0 RXS Channel x MCSPI_RXx register status R 0x0 Read 0x0 Register is empty Read 0x1 Register is full Table 20 39 Register Call Summary for Regis...

Page 3050: ...CSPI_CHxCONF 5 2 CLKD bit field for clock ratio only when granularity is one clock cycle MCSPI_CHxCONF 28 CLKG bit set to 1 Then the max value reached is 4096 clock divider ratio 0x0 Clock ratio is CLKD 1 0x1 Clock ratio is CLKD 1 16 0xFF Clock ratio is CLKD 1 4080 7 1 Reserved Read returns 0s RW 0x00 0 EN Channel enable RW 0x0 0x0 Channel x is not active 0x1 Channel x is active Table 20 41 Regist...

Page 3051: ...20 43 Register Call Summary for Register MCSPI_TXx McSPI Functional Description Master Transmit and Receive Mode Full Duplex 0 1 2 3 Master Transmit Only Mode Half Duplex 4 Master Receive Only Mode Half Duplex 5 6 7 8 9 Single Channel Master Mode 10 Dedicated Resources 11 12 13 14 15 Slave Transmit and Receive Mode 16 17 Slave Receive Only Mode 18 19 20 Interrupt Events in Master Mode 21 22 23 24 ...

Page 3052: ...000 Table 20 45 Register Call Summary for Register MCSPI_RXx McSPI Functional Description Master Transmit and Receive Mode Full Duplex 0 1 Master Transmit Only Mode Half Duplex 2 3 4 Master Receive Only Mode Half Duplex 5 6 Single Channel Master Mode 7 8 9 10 Dedicated Resources 11 12 13 Slave Transmit and Receive Mode 14 Slave Transmit Only Mode 15 16 End of Transfer Management 17 Interrupt Event...

Page 3053: ...FFFE 65534 spi word 0xFFFF 65535 spi word 15 14 Reserved Read returns 0s RW 0x0 13 8 AFL Buffer Almost Full This register holds the programmable almost RW 0x00 full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least I bytes then this bit field must be set to I 1 ...

Page 3055: ...ort of the multimedia device Topic Page 21 1 McBSP Overview 3056 21 2 McBSP Environment 3059 21 3 McBSP Integration 3069 21 4 McBSP Functional Description 3090 21 5 McBSP Basic Programming Model 3125 21 6 McBSP Register Manual 3154 3055 SWPU177N December 2009 Revised November 2010 Multi Channel Buffered Serial Port Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3056: ...1 Public Version McBSP Overview www ti com 21 1 McBSP Overview The multichannel buffered serial port McBSP provides a full duplex direct serial interface between the device and other devices in a system such as other application chips digital base band audio and voice codec TWL4030 device etc Because of its high level of versatility it can accommodate to a wide range of peripherals and clocked fra...

Page 3057: ... bus devices CAUTION McBSP modules do not offer support for m law and A law companding two partitions mode dynamic reassignment AC 97 and SPI protocol A wide selection of data sizes 8 12 16 20 24 and 32 bits Bit reordering send receive least significant bit LSB Clock and frame synchronization generation support Independent clocking and framing for reception and for transmission up to 48 MHz Suppor...

Page 3058: ... The SIDETONE core offers the following features Filter coefficients are shared between the two channels the filter coefficient is assumed to represent values in the range 1 1 Gains are independent for the two channels the gain coefficients are in the range 2 2 The filter output is multiplied with the gain and the result is rounded to output channel word width The FIR filter length is 128 samples ...

Page 3059: ...B Data McBSP1 Serial interface to transfer data Audio Data Audio Data with Audio Buffer McBSP2 Audio interface to transfer audio data with Inter IC Sound codec Audio Data with Audio Buffer and I2S SIDETONE feature Midi Data McBSP5 Voice Data Bluetooth Voice Data McBSP3 Voice interface to transfer voice data with Pulse Code Modulation Bluetooth Voice Data with codec PCM SIDETONE feature DBB Voice D...

Page 3060: ...ernal clock provided by PRCM of the device For more information see Section 21 3 McBSP Intergration Data are transmitted to external devices interfacing with McBSP modules via the mcbspi_dx pin Data from those devices are received on the mcbspi_dr pin NOTE The mcbspi_dx pin is an input output signal to use the McBSP module in half duplex mode Control information is communicated via the following p...

Page 3061: ...tions 1 Transmit and receive master mode 2 Transmit and receive slave mode 3 Transmit master mode and receive slave mode 4 Transmit slave mode and receive master mode NOTE If the McBSP module has a serial interface with 4 pins configuration McBSP2 3 4 5 only modes 1 or 2 are possible Figure 21 3 shows the connection between the McBSP1 module 6 pins configuration and an external device in transmit ...

Page 3062: ...rnal chipset allowing the device to be interfaced with a modem device Figure 21 5 shows typical connections between device and modem chipset to illustrate DBB data application Figure 21 5 DBB Data Application In Figure 21 5 the McBSP1 module is configured in transmit master mode and in receive slave mode 21 2 3 2 2 McBSP Function 2 Audio Data The McBSP module is connected to audio devices through ...

Page 3063: ...sfer voice data The voice devices can be either modem chipsets Bluetooth chipsets or others devices with voice data interface Figure 21 7 shows typical connections between device and Bluetooth chipset TI BRF6300 or TI BRF6350 to illustrate voice data application Figure 21 7 Voice Data Application In Figure 21 7 the McBSP3 module is configured in transmit and receive master mode 21 2 4 McBSP Protoc...

Page 3064: ...ronization signal the McBSP module begins receiving transmitting a frame of data When the next pulse occurs the McBSP module receives transmits the next frame and so on Frame synchronization pulse is active high or low This pulse polarity is programmable via bits field of pin control register McBSPi MCBSPLP_PCR_REG Each frame transfer can be delayed by 0 1 or 2 clock cycles depending on the value ...

Page 3065: ...al clocks CLKR and CLKX define the boundaries between bits for receive and transmit respectively Similarly frame sync signals FSR and FSX define the beginning of an element and or frame transfer The McBSP module allows the configuration of the following parameters for data and frame synchronization Polarity of FSR FSX CLKX and CLKR The number of words per frame The number of bits per word Whether ...

Page 3066: ...onization signal is low for the left phase time slot and is high for the right phase time slot In addition the frame synchronization signal is synchronous to the falling edge of the clock signal 21 2 4 3 2 Data Formats The I2S protocol supports TDM I2S left justified and right justified data formats Bits of each word sample are clocked using clock signal For each word MSB is first LSBs are padded ...

Page 3067: ...19 padding bits to 0 padding bits to 0 padding bits mcbsp 013 Public Version www ti com McBSP Environment Figure 21 11 I2S Data Format Word Width 32 Bits Data Length 24 Bits 21 2 4 3 2 3 Left Justified Data Format Figure 21 12 shows an example with 24 bits data MSB first and 8 padding bits at 0 Figure 21 12 Left Justified Data Format Word Width 32 Bits Data Length 24 Bits 21 2 4 3 2 4 Right Justif...

Page 3068: ...a Formats Two modes are available for the PCM protocol mode 1 and mode 2 For these both modes it has two types of operations Mono or stereo channels The difference between PCM mode 1 and PCM mode 2 is in the way they use either the rising or the falling edge of clock signal and the frame synchronization polarity PCM Mode 1 Input data is latched on the falling edge of the clock and the transmitted ...

Page 3069: ...sp 016 Public Version www ti com McBSP Integration 21 3 McBSP Integration This section describes the McBSP modules integration inside the device and all the details about signal source controls clocks resets power management and hardware requests McBSP modules are divided into 2 families McBSP modules that are gated in CORE domain McBSP1 and 5 and McBSP modules that are gated in PER domain McBSP2 ...

Page 3070: ...VA2_IRQ 19 IVA2_IRQ 20 IVA2_IRQ 34 M_IRQ_17 M_IRQ_62 M_IRQ_63 M_IRQ_4 Device Power reset and clock manager CLKS McBSP2_ICLK McBSP2_SWAKEUP PER_L4_ICLK PER_96M_FCLK McBSP2_SWAKEUP System control module Register CONTROL_DEVCONF0 6 mcbsp_clks McBSP2_FCLK mcbsp 018 Public Version McBSP Integration www ti com Figure 21 17 McBSP2 Integration 3070 Multi Channel Buffered Serial Port SWPU177N December 2009...

Page 3071: ...VA2_IRQ 21 IVA2_IRQ 22 IVA2_IRQ 35 M_IRQ_22 M_IRQ_89 M_IRQ_90 M_IRQ_5 Power reset and clock manager CLKS McBSP3_ICLK McBSP3_SWAKEUP PER_L4_ICLK PER_96M_FCLK McBSP3_SWAKEUP Device mcbsp_clks System control module Register CONTROL_DEVCONF1 0 McBSP3_FCLK mcbsp 019 Public Version www ti com McBSP Integration Figure 21 18 McBSP3 Integration 3071 SWPU177N December 2009 Revised November 2010 Multi Channe...

Page 3072: ... 7 IVA2_IRQ 23 IVA2_IRQ 24 IVA2_IRQ 36 M_IRQ_23 M_IRQ_54 M_IRQ_55 Power reset and clock manager CLKS McBSP4_ICLK McBSP4_SWAKEUP PER_L4_ICLK PER_96M_FCLK McBSP4_SWAKEUP mcbsp_clks System control module Register CONTROL_DEVCONF1 2 McBSP4_FCLK mcbsp 020 Public Version McBSP Integration www ti com Figure 21 19 McBSP4 Integration 3072 Multi Channel Buffered Serial Port SWPU177N December 2009 Revised No...

Page 3073: ...R and CLKS signals sources are defined by the system control module The control registers of the system control module are used to select these signals sources 21 3 1 1 McBSP1 Module 6 Pins Configuration The MCBSP1_CLKS bit of the CONTROL CONTROL_DEVCONF0 2 register is used to select the McBSP1 module CLKS signal source When set to 0 the CLKS source is from the CORE_96M_FCLK When set to 1 the CLKS...

Page 3074: ...ace clock domain Functional CLKS PER_96M_FCLK McBSP2 3 4 1 McBSP module is running using either a functional clock generated internally CORE_96M_FCLK McBSP1 5 1 master mode or supplied from its serial mcbsp_clks external source common to interface slave mode for the internal all McBSP modules logic Internal registers select the source of the functional clock and the divider Functional CLKX mcbspi_...

Page 3075: ...rovided the other modules that receive it do not require it For more information see Chapter 3 Power Reset and Clock Management At PRCM level when all the conditions to shut off CORE_L4_ICLK clock are met the PRCM automatically launches a hardware handshake protocol to ensure McBSP1 is ready to have this clock switched off Namely the PRCM asserts an idle request to McBSP1 For more details see Chap...

Page 3076: ...eset and Clock Management It is also possible to activate an autoidle mode for this clock PRCM CM_AUTOIDLE_PER 0 register AUTO_MCBSP2 bit set to 1 In this case McBSP2_ICLK follows the CORE_L4 clock domain behavior on the device For more information see Chapter 3 Power Reset and Clock Management 21 3 2 2 3 McBSP3 Clocks The McBSP3 module is clocked by a functional clock CLKS CLKX or CLKR and an int...

Page 3077: ...gnal the CLKX signal or the CLKR signal The choice between these three clocks is defined by the SCLKME bit of the MCBSP4 MCBSPLP_PCR_REG 7 register and the CLKSM bit of the MCBSP4 MCBSPLP_SRGR2_REG 13 register The CLKS signal of the McBSP4 module is linked to an internal clock PER_96M_FCLK provided by PRCM whereas the CLKS signal can also be linked to an external signal through the mcbsp_clks pin ...

Page 3078: ...nal clock CORE_96M_FCLK provided by PRCM The CLKS signal can also be linked to an external signal through the mcbsp_clks pin of the device boundary The MCBSP5_CLKS bit of the CONTROL CONTROL_DEVCONF1 4 register is used to select the McBSP5 module CLKS signal source 0 The CLKS source is from the CORE_96M_FCLK 1 The CLKS source is from the mcbsp_clks pin For more information see Chapter 13 System Co...

Page 3079: ...r when SIDETONE feature is not active or there is no activity on SIDETONE feature the McBSPi_ICLK clock supports an automatic gating that is enabled or disabled by setting the McBSPi ST_SYSCONFIG_REG 0 AUTOIDLE bit When this bit is asserted set to 1 the McBSPi_ICLK clock auto gating is enabled and this clock is disabled internally to the SIDETONE feature thus reducing power consumption but not to ...

Page 3080: ...o shut down all internal clocks Then the McBSP can continue to process during IDLE state with the external clock provided by the external component AUDIOBUFFER The McBSP can exit IDLE state only if the external serial clock is active After exiting IDLE state McBSP state machine clock is provided by the OMAP interface clock L4_ICLK NOTE Idle request and idle acknowledge are only internal signals wi...

Page 3081: ...Idle mode McBSP module also offers an additional granularity on McBSPi_FCLK and McBSPi_ICLK gating McBSPi MCBSPLP_SYSCONFIG_REG 9 8 CLOCKACTIVITY bit field is used to determine which clock will be shut down McBSPi_FCLK McBSPi_ICLK none of them or both of them CLOCKACTIVITY setting is used in the McBSP module to determine on which part of the module the conditions to acknowledge the PRCM idle reque...

Page 3082: ...enabled The McBSPi_SWAKEUP signal is the McBSP module asynchronous wake up signal sent to the PRCM module when a wake up generation is requested The wake up configurations are defined by setting the corresponding bits in the McBSPi MCBSPLP_WAKEUPEN_REG register 21 3 2 4 3 1 Receive Wake up There are 4 receive possible wake up configurations McBSPi MCBSPLP_WAKEUPEN_REG 3 RRDYEN bit The McBSP module...

Page 3083: ...g from idle mode McBSPi MCBSPLP_WAKEUPEN_REG 8 XFSXEN bit The McBSP module sends a McBSPi_SWAKEUP request when a transmit frame sync pulse is detected while the module is in idle mode If the McBSPi MCBSPLP_IRQENABLE_REG 8 XFSXEN bit is set to 1 the McBSP module sends an interrupt McBSPi_IRQ request to the MPU or IVA 2 2 subsystems when exiting from idle mode McBSPi MCBSPLP_WAKEUPEN_REG 7 XSYNCERRE...

Page 3084: ...nly when wake up event is set on transmit receive threshold reached CLKR outside 0bXX The module acknowledges the idle request as soon as there is no pending DMA interrupt request or transmit receive buffer threshold synchronization only when wake up event is set on transmit receive threshold reached regardless of the CLOCKACTIVITY settings 1 0 Receive McBSPi_ICLK 0b0X The McBSP will not acknowled...

Page 3085: ...te that no wake up event is available in this mode since the entire McBSP and remote device activity is frozen McBSPi_ICLK 0b1X The module acknowledges the idle request as soon as there is no pending DMA interrupt CLKS 0bX1 request or transmit receive buffer threshold synchronization only when wake up event is set on transmit receive threshold reached NOTE The RFSREN XFSXEN mode is suitable for wa...

Page 3086: ...e or transmit request S_DMA_18 system DMA controller McBSP4_DMA_RX EDMA_REQ 7 IVA2 2 subsystem DMA controller read or receive request S_DMA_19 system DMA controller McBSP5_DMA_TX EDMA_REQ 8 IVA2 2 subsystem DMA controller write or transmit request S_DMA_20 system DMA controller McBSP5_DMA_RX EDMA_REQ 9 IVA2 2 subsystem DMA controller read or receive request S_DMA_21 system DMA controller 21 3 3 2 ...

Page 3087: ...interrupt controller McBSP5_IRQ_RX IVA2_IRQ 26 IVA2 2 subsystem interrupt controller M_IRQ_82 MPU subsystem interrupt controller An event can generate an interrupt request when the corresponding mask bit in the McBSPi MCBSPLP_IRQENABLE_REG register is set to 1 Table 21 11 and Table 21 12 summarize the events causing the generation of an interrupt request Table 21 11 McBSP Transmit Interrupt Events...

Page 3088: ...rame TATUS_REG 2 REG 2 REOF REOFLEN Frame McBSPi MCBSPLP_IRQS McBSPi MCBSPLP_IRQENABLE_ This event happens when a new receive frame sync TATUS_REG 1 REG 1 synchronization is asserted RFSR RFSREN Frame McBSPi MCBSPLP_IRQS McBSPi MCBSPLP_IRQENABLE_ This event happens when a receive frame synchronization sync error TATUS_REG 0 REG 0 error is detected RSYNCERR RSYNCERREN Once an interrupt request is g...

Page 3089: ...n and acknowledge each processed event by writing a 1 to the corresponding bit in the McBSPi ST_IRQSTATUS_REG register NOTE The McBSPi ST_IRQSTATUS_REG 0 OVRRERROR status bit can be cleared in two ways If the McBSPi ST_IRQENABLE_REG 0 OVRRERROREN mask bit is set to 1 interrupt generation enabled the status bit is cleared by writing a 1 If the McBSPi ST_IRQENABLE_REG 0 OVRRERROREN mask bit is clear...

Page 3090: ...RX McBSPi_DMA_TX Receive buffer RB FIFO 128 32 bit words Transmit buffer XB FIFO 128 32 bit words McBSPi_ICLK McBSPi_SWAKEUP PRCM CLKS Clock and frame logic FSR_int FSX_int FSR_int CLKX_int CLKR_int L4 interfac e mcbsp 021 Pin block Public Version McBSP Functional Description www ti com 21 4 McBSP Functional Description This section is a functional description of the McBSP module 21 4 1 Block Diag...

Page 3091: ...r RB Transmit buffer XB 256 32 bits Audio buffer Audio buffer 1024 32 bits SFIRCR_REG Receive shift register RSR Interrupt to CPU Synchronization events to DMA controller McBSP2_IRQ_TX McBSP2_IRQ_RX McBSP2_IRQ McBSP2_DMA_RX McBSP2_DMA_TX McBSP2_ICLK McBSP2_SWAKEUP PRCM Interrupt to CPU Sample rate generator CLKX CLKR FS generated CLK generated CLKR FSR FSX CLKX CLKS Clock and frame logic FSX_int F...

Page 3092: ... FSR_int FSR_int CLKR_int CLKX_int L4 interconnect L4 interfac e L4 interface L4 interconnect Transmit buffer XB FIFO 128 32 bit words mcbsp 023 Pin block Public Version McBSP Functional Description www ti com Figure 21 23 McBSP3 Block Diagram 21 4 2 McBSP Data Transfer Process For McBSP1 McBSP3 McBSP4 and McBSP5 modules receive and transmit operations are triple buffered 512 bytes buffers organiz...

Page 3093: ...bits Long Words CAUTION For each data word length one data occupies one 32 bit buffer word Receive data arrives on the mcbspi_dr pin and is shifted into the receive shift register RSR When a full word depending on the data length configuration is received the content of the shift register is copied into the receive buffer RB if it is not full When the RB threshold is reached the McBSP module asser...

Page 3094: ...ata This section explains basic concepts and terminology important for understanding how McBSP data transfers are timed and delimited Figure 21 26 Conceptual Block Diagram for Clock and Frame Generation 21 4 2 3 1 Clocking Data is shifted one bit at a time from the mcbspi_dr pin to the RSRs or from the XSRs to the mcbspi_dx pin The time for each bit transfer is controlled by the rising or falling ...

Page 3095: ...each bit transfer on the pin Figure 21 27 Clock Signal Control of Bit Transfer Timing NOTE The McBSP module is constrained to operate at an internal functional frequency of up to L4 interface frequency divided by 2 When driving CLKX or CLKR at the pin choose an appropriate input clock frequency When using the internal sample rate generator for CLKX CLKR CLKS choose an appropriate input clock frequ...

Page 3096: ...tively When the McBSPi MCBSPLP_PCR_REG 11 FSXM bit transmitter frame sync mode is set to 0 FSX_int is derived from an external source and mcbspi_fsx is an input pin 1 FSX_int is determined by the McBSPi MCBSPLP_SRGR2_REG 12 FSGM bit and mcbspi_fsx is an output pin For the McBSPi MCBSPLP_PCR_REG 10 FSRM bit receiver frame sync mode is set to 0 FSR_int is generated by an external source and mcbspi_f...

Page 3097: ...21 4 4 3 or Section 21 4 4 6 21 4 2 3 6 Frame Frequency The frame frequency is determined by the period between frame synchronization pulses and is defined as shown in the following equation Frame frequency Clock frequency Number of clock cycles between two rising edges or falling edges of two consecutive frame synchronization pulses The frame frequency can be increased by decreasing the time betw...

Page 3098: ...rds per frame is limited to 2 when using dual phase frames one word for each phase and to 128 for a single phase frame The number of bits per word can be 8 12 16 20 24 or 32 bits The following legend applies to the table RPHASE McBSPi MCBSPLP_RCR2_REG 15 RPHASE bit XPHASE McBSPi MCBSPLP_XCR2_REG 15 XPHASE bit RFRLEN1 McBSPi MCBSPLP_RCR1_REG 14 8 RFRLEN1 field RFRLEN2 McBSPi MCBSPLP_RCR2_REG 14 8 R...

Page 3099: ...gure 21 30 below shows an example of a frame The first phase consists of one word of 16 bits followed by a second phase of one word of 8 bits The entire bit stream in the frame is contiguous There are no gaps between words phases Table 21 18 shows the assumptions used to the example in Figure 21 30 Table 21 18 Assumptions for the Dual Phase Frame Example Assumption Value Bit or Field name Single p...

Page 3100: ...owing process describes how data travels from the mcbspi_dr pin to the MPU IVA2 2 subsystem or to the sDMA controller 1 The McBSP module waits for a receive frame synchronization pulse on FSR_int 2 When the pulse arrives the McBSP module inserts the appropriate data delay that is selected with the McBSPi MCBSPLP_RCR2_REG 1 0 RDATDLY bits In the preceding timing diagram a 1 bit data delay is select...

Page 3101: ... that the transmitter is not ready for new data For details on choosing a word length see Section 21 5 1 6 2 2 2 2 When new data arrives in McBSPi MCBSPLP_DXR_REG register the McBSP module copies the content of the data transmit register to the XB In addition the transmit ready bit McBSPi MCBSPLP_SPCR2_REG 1 XRDY bit is set as long as the buffer contains at least the transmit threshold number of f...

Page 3102: ...ter is an interface clock McBSPi_ICLK synchronous register and does not reflect the exact number of occupied free locations available on the functional clock domain 21 4 2 8 MCBSP Data Transfer Mode NOTE For all examples in this section the configured CLKX edge is the rising edge McBSPi MCBSPLP_PCR_REG 1 CLKXP bit 0x0 and the configured CLKR edge is the falling edge McBSPi MCBSPLP_PCR_REG 0 CLKRP ...

Page 3103: ...eset value the FSX signal is sampled on the opposite configured CLKX edge and the data is driven on the next configured edge See Figure 21 36 Figure 21 36 Transmit Half Cycle Timing Diagram 21 4 2 8 3 Receive Full Cycle Mode When configured in full cycle mode McBSPi MCBSPLP_RCCR_REG 11 RFULL_CYCLE bit 0x1 reset value the FSR signal is sampled on the configured CLKR edge and the data is driven on t...

Page 3104: ...cBSPi MCBSPLP_PCR_REG 1 CLKXP bit or McBSPi MCBSPLP_PCR_REG 0 CLKRP bit The SRG has a three stage clock divider that gives CLKG and FSG programmability The three stages provide Clock divide down The source clock CLKSRG is divided according to the McBSPi MCBSPLP_SRGR1_REG 7 0 CLKGDV field to produce CLKG signal Frame period divide down CLKG is divided according to the McBSPi MCBSPLP_SRGR2_REG 11 0 ...

Page 3105: ...rolled by input signals These signals are defined by the control registers of the System Control Module more details refer Section 21 3 1 When using the SRG as a clock source make sure the SRG is enabled McBSPi MCBSPLP_SPCR2_REG 6 GRST bit 1 Table 21 19 Effects of DLB and ALB Bits on Clock Modes Mode Bit Settings Effect CLKRM 1 DLB 0 and ALB 0 Digital and analog loop back mode mcbsp1_clkr is an ou...

Page 3106: ...ization you must set McBSPi MCBSPLP_PCR_REG 11 FSXM 1 This indicates that transmit frame synchronization is supplied by the McBSP module itself rather than from the mcbspi_fsx pin MCBSPLP_SRGR2_REG 12 FSGM 1 This indicates that when FSXM 1 transmit frame synchronization is supplied by the SRG NOTE When FSGM 0 and FSXM 1 the transmit frame sync signal FSX is generated when XB is not empty When FSGM...

Page 3107: ...ways detected at the same edge of the input clock signal that generates CLKG signal no matter how long the FSR pulse is The McBSPi MCBSPLP_SRGR2_REG 11 0 FPER field are ignored because the frame synchronization period on FSG is determined by the arrival of the next frame synchronization pulse on the mcbspi_fsr pin If the McBSPi MCBSPLP_SRGR2_REG 15 GSYNC bit 0 CLKG signal runs freely and is not re...

Page 3108: ...n Error Conditions 21 4 4 1 Introduction There are several serial port events that can constitute a system error Any error conditions can be a source of an interrupt Receiver overrun McBSPi MCBSPLP_IRQSTATUS_REG 5 ROVFLSTAT bit is set to 1 and legacy mode McBSPi MCBSPLP_SPCR1_REG 2 RFULL bit is set to 1 This occurs when RB is full and RSR are full with another new word shifted in from mcbspi_dr Th...

Page 3109: ... frame transfer before all the bits of the current frame have been transferred Such a pulse is ignored by the transmitter but sets the McBSPi MCBSPLP_SPCR2_REG 3 XSYNCERR bit For more details see Section 21 4 4 6 Transmitter overflow McBSPi MCBSPLP_IRQSTATUS_REG 12 XOVFLSTAT bit is set to 1 This occurs when sDMA controller or MPU IVA2 2 subsystem writes data to a full XB For more details about und...

Page 3110: ...Pi MCBSPLP_SPCR1_REG 3 RSYNCERR bit can be cleared only by a receiver reset or by writing 0 to this bit If you want the McBSP module to notify the MPU IVA2 2 subsystem of receive frame synchronization errors set the legacy mode receive interrupt with the McBSPi MCBSPLP_SPCR1_REG 5 4 RINTM field When RINTM 0b11 the McBSP module sends a receive interrupt legacy mode request to the MPU IVA2 2 subsyst...

Page 3111: ...LSTAT bit Also the legacy mode McBSPi MCBSPLP_SPCR2_REG 2 XEMPTY bit is cleared Either of the following events activates XEMPTY bit XEMPTY 0 McBSPi MCBSPLP_DXR_REG has not been loaded and XB is empty and all bits of the data word in the XSR have been shifted out on the mcbspi_dx pin The transmitter is reset by forcing McBSPi MCBSPLP_SPCR2_REG 0 XRST 0 or by an global reset and is then restarted XE...

Page 3112: ...CERR bit According to the McBSPi MCBSPLP_IRQENABLE_REG register settings this condition can generate the McBSPi_IRQ line to be asserted low Writing 1 to the corresponding bit in status register clears the interrupt Using the legacy mode McBSPi MCBSPLP_SPCR2_REG 3 XSYNCERR bit can be cleared only by a transmitter reset or by a write of 0 to this bit If you want the McBSP module to notify the MPU IV...

Page 3113: ... reset the default DMA threshold and length is one The receive and transmit DMA requests can be individually disabled by setting the McBSPi MCBSPLP_RCCR_REG 3 RDMAEN McBSPi MCBSPLP_XCCR_REG 3 XDMAEN bits to 0 When disabling the DMA the DMA request line is de asserted even if a DMA transfer is pending and the DMA state machine is not reset The DMA threshold and length configuration is done through ...

Page 3114: ...els 96 111 Block 7 Channels 112 127 The blocks are assigned to partitions according to the selected partition mode In the two partition mode described in Section 21 4 6 6 you assign one even numbered block 0 2 4 or 6 to partition A and one odd numbered block 1 3 5 or 7 to partition B In the 8 partition mode Section 21 4 6 4 blocks 0 through 7 are automatically assigned to partitions A through H re...

Page 3115: ...red and the 16 channel blocks are assigned to the partitions as shown in Table 21 20 through Table 21 21 These assignments cannot be changed The tables also show the registers used to control the channels in the partitions Table 21 20 Eight Partitions Receive Channel Assignment and Control Receive Partition Assigned Block of Receive Channels Register Used for Channel Control A Block 0 Channels 0 t...

Page 3116: ...nel selection mode suppose you enable only channels 0 15 and 39 and that the frame length is 40 The McBSP module 1 Accepts bits shifted in from the mcbspi_dr pin in channel 0 2 Ignores bits received in channels 1 14 3 Accepts bits shifted in from the mcbspi_dr pin in channel 15 4 Ignores bits received in channels 16 38 5 Accepts bits shifted in from the mcbspi_dr pin in channel 39 21 4 6 6 Using T...

Page 3117: ...The McBSP module has three transmit multichannel selection modes XMCM 0b01 XMCM 0b10 and XMCM 0b11 which are described in Table 21 22 Table 21 22 Selecting a Transmit Multichannel Selection Mode With the XMCM Bit Field XMCM Transmit Multichannel Selection Mode 0b00 No transmit multichannel selection mode is on All channels are enabled and unmasked No channels can be disabled or masked 0b01 All cha...

Page 3118: ... be disabled on a shared serial bus A similar feature is not needed for reception because multiple receptions cannot cause serial bus contention Disabled channel A channel that is not enabled A disabled channel is also masked Because no DXR to XB copy occurs the McBSPi MCBSPLP_SPCR2_REG 1 XRDY bit is not set Therefore no DMA synchronization event is generated and if the transmit interrupt mode dep...

Page 3119: ...led and unmasked Words W0 W1 W2 and W3 are written to the XB then from the XB there are transferred by mcbspi_dx Figure 21 50 Activity on McBSP Pins When XMCM 0b01 In Figure 21 50 if XMCM 0b01 XPABLK 0b00 and XCERA 0b1010 only channels 1 and 3 are enabled and unmasked Words W1 and W3 are written to the XB then from the XB there are transferred by mcbspi_dx Figure 21 51 Activity on McBSP Pins When ...

Page 3120: ...an be configured to be input in the external SIDETONE core After filtering the data from digital microphone data is mixed and sent out to the speaker output channels using two out of eight configured output channels separate configuration bits are used The McBSP module synchronizes the incoming data filtered by the external SIDETONE core The transmit and receive part of the McBSP module are not re...

Page 3121: ...nnel mode enable Set a frame length in McBSPi MCBSPLP_RCR1_REG 14 8 RFRLEN1 bit field and in McBSPi MCBSPLP_XCR1_REG 14 8 XFRLEN1 bit field that includes the highest numbered channel to be used a maximum of 4 channels can be used in this configuration Set a word length in McBSPi MCBSPLP_RCR1_REG 7 5 RWDLEN1 bit field and in McBSPi MCBSPLP_XCR1_REG 7 5 XWDLEN1 bit field to be either 16 24 or 32 see...

Page 3122: ... should be equal to McBSPi MCBSPLP_SSELCR_REG 3 2 ICH1ASSIGN The McBSP module does not support two input channels to be assigned to only one SIDETONE output channel 21 4 7 3 Data Processing Path The SIDETONE core receives the data to be processed through two 24 bits parallel data interfaces one for each audio channel When enabled through McBSPi ST_SSELCR_REG 0 SIDETONEEN bit field the module appli...

Page 3123: ...lock cycles The ST_CH0_VALIDR and ST_CH1_VALIDR are 1 bit inputs and their toggling information is used to signal that new data is valid for sampling from ST_CH0_DATAR ST_CH1_DATAR The ST_CH0_VALIDX and ST_CH1_VALIDX are 1 bit outputs and their toggling information is used to signal that new data is valid on the output data bus ST_CH0_DATAX ST_CH1_DATAX 21 4 7 4 Data Processing The processing cons...

Page 3124: ...ved through the data interface without returning any sample or toggling any of the ST_CH0 CH1_VALIDX outputs The first 127 samples for each channel are only accumulated no processed data is provided The first processed frame comes after receiving the 128th sample with the specific delay When the SIDETONE operation is disabled data is output through the data interface as it comes on the data input ...

Page 3125: ...L_CYCLE bit are their reset value XFULL_CYCLE bit 0 and RFULL_CYCLE bit 1 21 5 1 1 McBSP Initialization Procedure This procedure for reset initialization can be applied in general when the Receiver or Transmitter has to be reset during its normal operation and also when the Sample Rate Generator is not used for either operation Figure 21 57 shows the serial port initialization procedure for master...

Page 3126: ...P_DXR_REG Set McBSPi MCBSPLP_SPCR1_REG 0 RRST bit to 1 WAIT for 2 SRG clock cycles Do you want the other bits in these registers modified Enable the serial port Is internally generated frame sync required Set McBSPi MCBSPLP_SPCR2_REG 7 FRST bit to 1 WAIT for 2 clock cycles Step 1 Step 2 Step 3 Step 4 Step 5 mcbsp 062 WAIT for 2 SRG clock cycles Public Version McBSP Basic Programming Model www ti c...

Page 3127: ... McBSPi MCBSPLP_PCR_REG McBSPi MCBSPLP_RCR1_REG McBSPi MCBSPLP_RCR2_REG McBSPi MCBSPLP_XCR1_REG McBSPi MCBSPLP_XCR2_REG Set up data acquisition as required such as writing to McBSPi MCBSPLP_DXR_REG Set McBSPi MCBSPLP_SPCR1_REG 0 RRST bit to 1 Do you want the other bits in these registers modified Enable the serial port Step 1 Step 2 Step 3 Step 4 mcbsp 074 Public Version www ti com McBSP Basic Pro...

Page 3128: ...iver and the Transmitter reset bits GRST RRST and XRST are automatically forced to 0 Otherwise during normal operation the Sample Rate Generator can be reset by making McBSPi MCBSPLP_SPCR2_REG 6 GRST 0 provided that CLKG and or FSG internal signal is not used by any portion of the McBSP module Depending on the system needs the software may also to reset the Receiver McBSPi MCBSPLP_SPCR1_REG 0 RRST...

Page 3129: ...ed wait for 2 CLKG cycles for the Sample Rate Generator logic to stabilize On the next rising edge of CLKSRG the CLKG signal transitions to 1 and starts clocking with a frequency equal to input clock frequency CLKGDV 1 If necessary enable the receiver and or the transmitter If necessary remove the receiver and or transmitter from reset by setting McBSPi MCBSPLP_SPCR1_REG 0 RRST bit and or McBSPi M...

Page 3130: ...0 FPER field Configure MCBSPLP_SRGR1_REG 15 8 FWID field Configure MCBSPLP_SRGR1_REG 7 0 CLKGDV field GSYNC bit 1 Yes No End mcbsp 073 Public Version McBSP Basic Programming Model www ti com Figure 21 59 Flow Diagram for the SRG Registers Programmation The input clock is selected with the McBSPi MCBSPLP_PCR_REG 7 SCLKME bit and the McBSPi MCBSPLP_SRGR2_REG 13 CLKSM bit in one of the following conf...

Page 3131: ...equest will be de asserted and reasserted as soon as the conditions are met again NOTE In case of a number of transfers that exceed the number of the programmed DMA length the McBSP module will respond to the command and will perform the transfer regardless of the transmit buffer full condition When the transmit buffer is full a data transfer access will trigger a transmit overflow interrupt if en...

Page 3132: ...only The McBSPi MCBSPLP_SPCR1_REG 5 4 RINTM bit field determines which event generates a receive interrupt request McBSPi_IRQ_RX to the MPU IVA2 2 subsystem The receive interrupt informs the MPU IVA2 2 subsystem of changes to the serial port status Four options exist for configuring this interrupt RINTM 0b00 The receive interrupt generated when the McBSPi MCBSPLP_SPCR1_REG 1 RRDY bit changes from ...

Page 3133: ...ynchronization error Regardless of the value of XINTM XSYNCERR bit can be read to detect this condition For information on using XSYNCERR bit see Section 21 4 4 6 The McBSP module provides also a common interrupt line McBSPi_IRQ which can be used by setting the McBSPi MCBSPLP_IRQENABLE register All the above settings have equivalent enable bits in the McBSPi MCBSPLP_IRQENABLE register to enable th...

Page 3134: ...ectly using the McBSPi MCBSPLP_SPCR1_REG 0 RRST bit If the SRG needs to be used SRG must be reset directly using the McBSPi MCBSPLP_SPCR2_REG 6 GRST bit Similar operations with frame synchronization generator also require using the McBSPi MCBSPLP_SPCR2_REG 7 FRST bit when the frame sync signal must be generated To enable the receiver the preceding bits cleared to 0 must be set to 1 21 5 1 5 2 Prog...

Page 3135: ... Section 21 5 1 7 which describes how to use McBSP pins as GPIO pins 21 5 1 5 2 1 2 Enable Disable the Digital Loop Back Mode The McBSPi MCBSPLP_XCCR_REG 5 DLB bit determines whether the digital loopback mode is on or off In the digital loopback mode the receive signals are connected internally through multiplexers to the corresponding transmit signals DR signal is connected on DX signal to receiv...

Page 3136: ...e Disable the Receive Multichannel Selection Mode The McBSPi MCBSPLP_MCR1_REG 0 RMCM bit determines whether the receive multichannel selection mode is on or off For further details see Section 21 4 6 5 21 5 1 5 2 2 Data Behavior 21 5 1 5 2 2 1 Choose 1 or 2 Phases for the Receive Frame The McBSPi MCBSPLP_RCR2_REG 15 RPHASE bit determines whether the receive data frame has one Single phase or two p...

Page 3137: ...et the Receive Data Delay The McBSPi MCBSPLP_RCR2_REG 1 0 RDATDLY bit field determines the length of the data delay for the receive frame The start of a frame is defined by the first clock cycle in which frame synchronization is active The beginning of actual data reception or transmission with respect to the start of the frame can be delayed if required This delay is called data delay McBSPi MCBS...

Page 3138: ... Bit 21 5 1 5 2 2 6 Set the Receive Sign Extension and Justification Mode The McBSPi MCBSPLP_SPCR1_REG 14 13 RJUST bit field determines whether data received by the McBSP module is sign extended or not and how it is justified RJUST bit selects whether data in RB is right or left justified with respect to the MSB in McBSPi MCBSPLP_DRR_REG register and whether unused bits in McBSPi MCBSPLP_DRR_REG a...

Page 3139: ... shows how you can select various sources to provide the receive frame synchronization signal and the effect on the mcbsp_fsr pin The polarity of the signal on the mcbsp_fsr pin is determined by the McBSPi MCBSPLP_PCR_REG 2 FSRP bit Table 21 29 FSRM and GSYNC Effects on Frame Sync Signal and mcbsp_fsr Pin FSRM GSYNC Source of Receive Frame Synchronization MCBSPLP FSR Pin Status 0 0 or 1 An externa...

Page 3140: ...nal FSX Similarly if internal synchronization FSR FSX are output pins and GSYNC 0 is selected the internal active high frame synchronization signals are inverted if the polarity bit FS R X P 1 before being sent to the FS R X pin Figure 21 64 shows how data clocked by an external serial device using a rising edge can be sampled by the McBSP receiver on the falling edge of the same clock Figure 21 6...

Page 3141: ...bit before being used 1 The SRG clock CLKG drives internal CLKR Output CLKG inverted as determined by CLKRP is driven out on the mcbsp_clkr pin In the digital loop back mode DLB 1 or analog loop back mode ALB 1 the transmit clock signal is used as the receive clock signal For more details on clock configuration see Section 21 4 3 1 21 5 1 5 2 4 2 Set the Receive Clock Polarity McBSPi MCBSPLP_PCR_R...

Page 3142: ...from an external clock on the mcbsp_clks mcbsp_clkx or mcbsp_clkr pin If you use a pin choose a polarity for that pin by using the appropriate polarity bit CLKSP for the mcbsp_clks pin CLKXP for the mcbsp_clkx pin CLKRP for the mcbsp_clkr pin The polarity determines whether the rising or falling edge of the input clock generates transitions on CLKG and FSG 21 5 1 6 Transmitter Configuration To con...

Page 3143: ...nterrupt mode Set the transmit DMA mode Global Behavior Data Behavio r B Set the transmit reverse mode mcbsp 065 Public Version www ti com McBSP Basic Programming Model 21 5 1 6 2 Programming the McBSP Registers for the Desired Transmitter Operation Step 2 Figure 21 66 and Figure 21 67 list important tasks to be performed when configuring the McBSP transmitter Each task corresponds to one or more ...

Page 3144: ...Pins McBSPi MCBSPLP_PCR_REG 13 XIOEN bit determines whether the transmitter pins are McBSP pins XIOEN 0 or general purpose I O pins XIOEN 1 See Section 21 5 1 7 which describes how to use McBSP pins as GPIO pins 21 5 1 6 2 1 2 Enable Disable the Digital Loop Back Mode See Section 21 5 1 5 2 1 2 21 5 1 6 2 1 3 Enable Disable the Analog Loop Back Mode See Section 21 5 1 5 2 1 3 21 5 1 6 2 1 4 Enable...

Page 3145: ...ase 1 one word plus the length of phase 2 one word Others values must not be used The 7 bit XFRLEN fields allow up to 128 words per phase See Table 21 31 for a summary of how to calculate the frame length This length corresponds to the number of words or logical time slots or channels per frame synchronization pulse Program the XFRLEN fields with W minus 1 where W represents the number of words pe...

Page 3146: ...ta is sampled on the first falling edge of CLKR where an active high internal FSR is detected However data transmission must begin on the rising edge of the internal CLKX clock that generated the frame synchronization Therefore the first data bit is assumed to be present in XSR1 and thus on mcbspi_dx The transmitter then asynchronously detects the frame synchronization signal FSX going active high...

Page 3147: ...equest is deasserted and then reasserted as soon as the conditions are met again 21 5 1 6 2 3 Frame Synchronization Behavior 21 5 1 6 2 3 1 Set the Transmit Frame Sync Mode McBSPi MCBSPLP_PCR_REG 11 FSXM bit and McBSPi MCBSPLP_SRGR2_REG 12 FSGM bit are used to set the transmit frame sync mode Table 21 32 shows how FSXM and FSGM select the source of transmit frame synchronization pulses The three c...

Page 3148: ...ted transition to their active state on the rising edge of internal clock CLK R X Similarly data on the mcbsp_dx pin is output on the rising edge of internal CLKX FSRP FSXP CLKRP and CLKXP in the pin control register PCR_REG configure the polarities of the FSR FSX CLKR and CLKX signals respectively All FSG internal FSR internal FSX that are internal to the serial port are active high If the serial...

Page 3149: ...ut pin the external rising edge triggered input clock on CLKR is inverted to a falling edge triggered clock before being sent to the receiver If CLKRP 1 and internal clocking is selected CLKRM 1 the internal falling edge triggered clock is inverted to a rising edge triggered clock before being sent out on the mcbsp_clkr pin NOTE CLKRP CLKXP in a system where the same clock internal or external is ...

Page 3150: ...Table 21 34 Using McBSP Pins for General Purpose I O Pin General Purpose Selected as output Output value Selected as input Input value read use enabled by this when driven from this bit when from this bit bit combination XRST 0 mcbsp_clkx CLKXM 1 CLKXP CLKXM 0 CLKXP XIOEN 1 XRST 0 mcbsp_fsx FSXM 1 FSXP FSXM 0 FSXP XIOEN 1 XRST 0 mcbsp_dx Always DX_STAT Never Does not apply XIOEN 1 RRST 0 mcbsp_clk...

Page 3151: ...LP_DXR_REG are necessary for each frame This results in only half the number of transfers as compared to the previous case This manipulation reduces the percentage of bus time required for serial port data movement Figure 21 71 One 32 bit Data Word Transferred To From McBSP Module 21 5 1 8 2 Data Packing Using Word Length and the Frame Sync Ignore Function When there are multiple words per frame d...

Page 3152: ...andwidth needed to transfer four 8 bit words Figure 21 73 Configuring the Data Stream as a Continuous 32 bit Word 21 5 2 SIDETONE Feature 21 5 2 1 SIDETONE Activation Procedure Before you enable a SIDETONE selection mode make sure you properly configure the data frame for multichannel mode of the McBSP module Select a single phase frame McBSPi MCBSPLP_RCR2_REG 15 RPHASE bit and McBSPi MCBSPLP_XCR2...

Page 3153: ...e accesses to McBSPi ST_SFIRCR_REG 15 0 FIRCOEFF bit field the McBSPi ST_SFIRCR_REG 0 FIRCOEFF bit is loaded first To ensure the completion of loading check the status bit field McBSPi ST_SSELCR_REG 2 COEFFWRDONE bit 3 Set up gain values for both channels writing desired values inside McBSPi ST_SGAINCR_REG 31 16 CH1GAIN bit field for the second sidetone channel and McBSPi ST_SGAINCR_REG 15 0 CH0GA...

Page 3154: ...R2_REG RW 32 0x0000 0010 0x4807 4010 MCBSPLP_SPCR1_REG RW 32 0x0000 0014 0x4807 4014 MCBSPLP_RCR2_REG RW 32 0x0000 0018 0x4807 4018 MCBSPLP_RCR1_REG RW 32 0x0000 001C 0x4807 401C MCBSPLP_XCR2_REG RW 32 0x0000 0020 0x4807 4020 MCBSPLP_XCR1_REG RW 32 0x0000 0024 0x4807 4024 MCBSPLP_SRGR2_REG RW 32 0x0000 0028 0x4807 4028 MCBSPLP_SRGR1_REG RW 32 0x0000 002C 0x4807 402C MCBSPLP_MCR2_REG RW 32 0x0000 0...

Page 3155: ...4807 40BC MCBSPLP_STATUS_REG R 32 0x0000 00C0 0x4807 40C0 Table 21 38 McBSP5 Registers Mapping Summary Register Name Type Register Address Offset Physical Address Width Bits MCBSPLP_DRR_REG R 32 0x0000 0000 0x4809 6000 MCBSPLP_DXR_REG W 32 0x0000 0008 0x4809 6008 MCBSPLP_SPCR2_REG RW 32 0x0000 0010 0x4809 6010 MCBSPLP_SPCR1_REG RW 32 0x0000 0014 0x4809 6014 MCBSPLP_RCR2_REG RW 32 0x0000 0018 0x480...

Page 3156: ... 60B4 MCBSPLP_RBUFFSTAT_REG R 32 0x0000 00B8 0x4809 60B8 MCBSPLP_SSELCR_REG RW 32 0x0000 00BC 0x4809 60BC MCBSPLP_STATUS_REG R 32 0x0000 00C0 0x4809 60C0 Table 21 39 McBSP2 Registers Mapping Summary Register Name Type Register Address Offset Physical Address Width Bits MCBSPLP_DRR_REG R 32 0x0000 0000 0x4902 2000 MCBSPLP_DXR_REG W 32 0x0000 0008 0x4902 2008 MCBSPLP_SPCR2_REG RW 32 0x0000 0010 0x49...

Page 3157: ...0AC MCBSPLP_RCCR_REG RW 32 0x0000 00B0 0x4902 20B0 MCBSPLP_XBUFFSTAT_REG R 32 0x0000 00B4 0x4902 20B4 MCBSPLP_RBUFFSTAT_REG R 32 0x0000 00B8 0x4902 20B8 MCBSPLP_SSELCR_REG RW 32 0x0000 00BC 0x4902 20BC MCBSPLP_STATUS_REG R 32 0x0000 00C0 0x4902 20C0 Table 21 40 McBSP3 Registers Mapping Summary Register Name Type Register Address Offset Physical Address Width Bits MCBSPLP_DRR_REG R 32 0x0000 0000 0...

Page 3158: ... MCBSPLP_WAKEUPEN_REG RW 32 0x0000 00A8 0x4902 40A8 MCBSPLP_XCCR_REG RW 32 0x0000 00AC 0x4902 40AC MCBSPLP_RCCR_REG RW 32 0x0000 00B0 0x4902 40B0 MCBSPLP_XBUFFSTAT_REG R 32 0x0000 00B4 0x4902 40B4 MCBSPLP_RBUFFSTAT_REG R 32 0x0000 00B8 0x4902 40B8 MCBSPLP_SSELCR_REG RW 32 0x0000 00BC 0x4902 40BC MCBSPLP_STATUS_REG R 32 0x0000 00C0 0x4902 40C0 Table 21 41 McBSP4 Registers Mapping Summary Register N...

Page 3159: ...REG RW 32 0x0000 0094 0x4902 6094 MCBSPLP_IRQSTATUS_REG RW 32 0x0000 00A0 0x4902 60A0 MCBSPLP_IRQENABLE_REG RW 32 0x0000 00A4 0x4902 60A4 MCBSPLP_WAKEUPEN_REG RW 32 0x0000 00A8 0x4902 60A8 MCBSPLP_XCCR_REG RW 32 0x0000 00AC 0x4902 60AC MCBSPLP_RCCR_REG RW 32 0x0000 00B0 0x4902 60B0 MCBSPLP_XBUFFSTAT_REG R 32 0x0000 00B4 0x4902 60B4 MCBSPLP_RBUFFSTAT_REG R 32 0x0000 00B8 0x4902 60B8 MCBSPLP_SSELCR_...

Page 3160: ...02 4000 McBSP3 0x4902 6000 McBSP4 Description McBSPLP data receive register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRR Bits Field Name Description Type Reset 31 0 DRR Data receive register R 0x00000000 Table 21 45 Register Call Summary for Register MCBSPLP_DRR_REG McBSP Functional Description Data Transfer Process for 8 12 16 20 24 32 bits Long...

Page 3161: ...ds 0 McBSP Transmission 1 2 Introduction 3 Underflow in the Transmitter 4 5 6 7 Transmit Multichannel Selection Modes 8 McBSP Basic Programming Model McBSP Initialization Procedure 9 Data Packing Examples 10 11 McBSP Register Manual McBSP Register Mapping Summary 12 13 14 15 16 Table 21 48 MCBSPLP_SPCR2_REG Address Offset 0x0000 0010 Physical Address 0x4807 4010 Instance McBSP1 0x4809 6010 McBSP5 ...

Page 3162: ...G is reset 0x1 SRG is pulled out of reset CLKG is driven as per programmed value in SRG registers SRGR 1 2 5 4 XINTM Transmit Interrupt Mode legacy RW 0x0 0x0 Transmit interrupt is driven by XRDY 0x1 Transmit interrupt generated by end of frame 0x2 Transmit interrupt generated by a new frame synchronization 0x3 Transmit interrupt generated by XSYNCERR 3 XSYNCERR Transmit Synchronization Error RW 0...

Page 3163: ...acy Only 49 50 McBSP Register Manual McBSP Register Mapping Summary 51 52 53 54 55 Table 21 50 MCBSPLP_SPCR1_REG Address Offset 0x0000 0014 Physical Address 0x4807 4014 Instance McBSP1 0x4809 6014 McBSP5 0x4902 2014 McBSP2 0x4902 4014 McBSP3 0x4902 6014 McBSP4 Description McBSPLP serial port control register 1 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 3164: ...ot ready 0x1 Receiver is ready with data to be read from DRR 0 RRST Receiver reset This resets and enables the receiver RW 0x0 0x0 The serial port receiver is disabled and in reset state 0x1 The serial port receiver is enabled Table 21 51 Register Call Summary for Register MCBSPLP_SPCR1_REG McBSP Integration Hardware and Software Reset 0 McBSP Functional Description McBSP Reception 1 2 3 Clock Gen...

Page 3165: ...RLEN2 Receive Frame Length 2 RW 0x00 Single phase frame selected RFRLEN2 don t care Dual phase frame selected RFRLEN2 000 0000 1 word per second phase other values are reserved 7 5 RWDLEN2 Receive Word Length 2 RW 0x0 0x0 8 bits 0x1 12 bits 0x2 16 bits 0x3 20 bits 0x4 24 bits 0x5 32 bits 0x6 Reserved do not use 0x7 Reserved do not use 4 3 RREVERSE Receive reverse mode RW 0x0 0x0 Data transfer star...

Page 3166: ...sical Address 0x4807 401C Instance McBSP1 0x4809 601C McBSP5 0x4902 201C McBSP2 0x4902 401C McBSP3 0x4902 601C McBSP4 Description McBSPLP receive control register 1 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RFRLEN1 RWDLEN1 RESERVED Bits Field Name Description Type Reset 31 15 RESERVED Read returns 0x0 R 0x00000 14 8 RFRLEN1 Receive Frame...

Page 3167: ...020 McBSP2 0x4902 4020 McBSP3 0x4902 6020 McBSP4 Description McBSPLP transmit control register 2 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED XFRLEN2 XWDLEN2 XPHASE XDATDLY XREVERSE RESERVED Bits Field Name Description Type Reset 31 16 RESERVED Read returns 0x0 R 0x0000 15 XPHASE Transmit Phases RW 0x0 0x0 Single phase frame 0x1 Dual phase ...

Page 3168: ... 8 9 10 11 12 13 14 15 16 McBSP Transmission 17 MCBSP Data Transfer Mode 18 Unexpected Transmit Frame sync Pulse 19 Configuring a Frame for Multichannel Selection 20 SIDETONE Interface 21 McBSP Basic Programming Model McBSP Initialization Procedure 22 Transmitter Configuration 23 24 25 26 27 SIDETONE Activation Procedure 28 McBSP Register Manual McBSP Register Mapping Summary 29 30 31 32 33 Table ...

Page 3169: ...Phases Definitions 0 1 McBSP Functional Description Clocking and Framing Data 2 3 Frame Phases Dual Phase Frame I2S Support 4 5 6 7 8 9 10 Configuring a Frame for Multichannel Selection 11 SIDETONE Interface 12 13 McBSP Basic Programming Model McBSP Initialization Procedure 14 Transmitter Configuration 15 16 SIDETONE Activation Procedure 17 18 McBSP Register Manual McBSP Register Mapping Summary 1...

Page 3170: ...nchronization RW 0x0 Mode Used when FSXM 1 in the PCR 0x0 Transmit frame sync signal FSX is generated when transmit buffer is not empty When FSGM 0 FPER and FWID are used to determine the frame synchronization period and width external FSX is gated by the buffer empty condition 0x1 Transmit frame sync signal driven by the SRG frame sync signal FSG 11 0 FPER Frame Period This value 1 determines whe...

Page 3171: ...requency Default value is 1 Table 21 63 Register Call Summary for Register MCBSPLP_SRGR1_REG McBSP Functional Description Clocking and Framing Data 0 McBSP SRG 1 2 3 Frame Sync Generation in the SRG 4 5 Synchronizing SRG Outputs to an External Clock 6 7 Underflow in the Transmitter 8 McBSP Basic Programming Model McBSP Initialization Procedure 9 Receiver Configuration 10 11 McBSP Register Manual M...

Page 3172: ...nnel enable registers XCERA Channels in partition A XCERB Channels in partition B 0x1 8 partition mode All partitions A through H are used You can control up to 128 channels in the transmit multichannel selection mode selected with the XMCM bits You control the channels with the appropriate transmit channel enable registers XCERA Channels 0 through 15 XCERB Channels 16 through 31 XCERC Channels 32...

Page 3173: ...nd XCER A B This mode is used for symmetric transmit and receive operation Table 21 65 Register Call Summary for Register MCBSPLP_MCR2_REG McBSP Functional Description Using Eight Partitions 0 1 2 Using Two Partitions Legacy Only 3 4 Transmit Multichannel Selection Modes 5 6 7 8 9 10 McBSP Basic Programming Model McBSP Initialization Procedure 11 Transmitter Configuration 12 McBSP Register Manual ...

Page 3174: ... RCERD Channels 48 through 63 RCERE Channels 64 through 79 RCERF Channels 80 through 95 RCERG Channels 96 through 111 RCERH Channels 112 through 127 8 7 RPBBLK Receive Partition B Block RW 0x0 legacy 0x0 Block 1 Channel 16 to channel 31 0x1 Block 3 Channel 48 to channel 63 0x2 Block 5 Channel 80 to channel 95 0x3 Block 7 Channel 112 to channel 127 6 5 RPABLK Receive Partition A Block RW 0x0 legacy...

Page 3175: ...in an even numbered block in partition A RCERA n 1 Enables reception of n th channel in an even numbered block in partition A Table 21 69 Register Call Summary for Register MCBSPLP_RCERA_REG McBSP Functional Description Using Eight Partitions 0 Receive Multichannel Selection Mode 1 2 Using Two Partitions Legacy Only 3 Transmit Multichannel Selection Modes 4 5 McBSP Register Manual McBSP Register M...

Page 3176: ... McBSP3 0x4902 6040 McBSP4 Description McBSPLP transmit channel enable register partition A Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED XCERA Bits Field Name Description Type Reset 31 16 RESERVED Read returns 0x0 R 0x0000 15 0 XCERA Transmit Channel Enable RW 0x0000 XCERA n 0 Disables transmission of n th channel in an event numbered block...

Page 3177: ...nsmission of n th channel in an even numbered block in partition B Table 21 75 Register Call Summary for Register MCBSPLP_XCERB_REG McBSP Functional Description Using Eight Partitions 0 Using Two Partitions Legacy Only 1 McBSP Register Manual McBSP Register Mapping Summary 2 3 4 5 6 Table 21 76 MCBSPLP_PCR_REG Address Offset 0x0000 0048 Physical Address 0x4807 4048 Instance McBSP1 0x4809 6048 McBS...

Page 3178: ... Synchronization Mode RW 0x0 0x0 Frame synchronization signal derived from an external source 0x1 Frame synchronization is determined by the SRG frame synchronization mode bit FSGM in SRGR2 10 FSRM Receive Frame Synchronization Mode RW 0x0 0x0 Frame Synchronization pulses generated by an external device FSR is an input pin 0x1 Frame synchronization generated internally by SRG FSR is an output pin ...

Page 3179: ...s active high 0x1 Frame synchronization pulse FSX is active low 2 FSRP Receive Frame Synchronization Polarity RW 0x0 0x0 Frame synchronization pulse FSR is active high 0x1 Frame synchronization pulse FSR is active low 1 CLKXP Transmit Clock Polarity RW 0x0 0x0 Transmit data driven on rising edge of CLKX 0x1 Transmit data driven on falling edge of CLKX 0 CLKRP Receive Clock Polarity RW 0x0 0x0 Rece...

Page 3180: ...McBSP2 0x4902 404C McBSP3 0x4902 604C McBSP4 Description McBSPLP receive channel enable register partition C Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RCERC Bits Field Name Description Type Reset 31 16 RESERVED Read returns 0x0 R 0x0000 15 0 RCERC Receive Channel Enable RW 0x0000 RCERC n 0 Disables reception of n th channel in an even nu...

Page 3181: ...egister MCBSPLP_RCERD_REG McBSP Functional Description Using Eight Partitions 0 McBSP Register Manual McBSP Register Mapping Summary 1 2 3 4 5 Table 21 82 MCBSPLP_XCERC_REG Address Offset 0x0000 0054 Physical Address 0x4807 4054 Instance McBSP1 0x4809 6054 McBSP5 0x4902 2054 McBSP2 0x4902 4054 McBSP3 0x4902 6054 McBSP4 Description McBSPLP transmit channel enable register partition C Type RW 31 30 ...

Page 3182: ...ansmit Channel Enable RW 0x0000 XCERD n 0 Disables transmission of n th channel in an even numbered block in partition D XCERD n 1 Enables transmission of n th channel in an even numbered block in partition D Table 21 85 Register Call Summary for Register MCBSPLP_XCERD_REG McBSP Functional Description Using Eight Partitions 0 McBSP Register Manual McBSP Register Mapping Summary 1 2 3 4 5 Table 21 ...

Page 3183: ...P5 0x4902 2060 McBSP2 0x4902 4060 McBSP3 0x4902 6060 McBSP4 Description McBSPLP receive channel enable register partition F Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RCERF Bits Field Name Description Type Reset 31 16 RESERVED Read returns 0x0 R 0x0000 15 0 RCERF Receive Channel Enable RW 0x0000 RCERF n 0 Disables reception of n th channe...

Page 3184: ... for Register MCBSPLP_XCERE_REG McBSP Functional Description Using Eight Partitions 0 McBSP Register Manual McBSP Register Mapping Summary 1 2 3 4 5 Table 21 92 MCBSPLP_XCERF_REG Address Offset 0x0000 0068 Physical Address 0x4807 4068 Instance McBSP1 0x4809 6068 McBSP5 0x4902 2068 McBSP2 0x4902 4068 McBSP3 0x4902 6068 McBSP4 Description McBSPLP transmit channel enable register partition F Type RW ...

Page 3185: ... Receive Channel Enable RW 0x0000 RCERG n 0 Disables reception of n th channel in an even numbered block in partition G RCERG n 1 Enables reception of n th channel in an even numbered block in partition G Table 21 95 Register Call Summary for Register MCBSPLP_RCERG_REG McBSP Functional Description Using Eight Partitions 0 McBSP Register Manual McBSP Register Mapping Summary 1 2 3 4 5 Table 21 96 M...

Page 3186: ...074 Instance McBSP1 0x4809 6074 McBSP5 0x4902 2074 McBSP2 0x4902 4074 McBSP3 0x4902 6074 McBSP4 Description McBSPLP transmit channel enable register partition G Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED XCERG Bits Field Name Description Type Reset 31 16 RESERVED Read returns 0x0 R 0x0000 15 0 XCERG Transmit Channel Enable RW 0x0000 XCERG...

Page 3187: ... H Table 21 101 Register Call Summary for Register MCBSPLP_XCERH_REG McBSP Functional Description Using Eight Partitions 0 Transmit Multichannel Selection Modes 1 2 3 4 5 6 McBSP Register Manual McBSP Register Mapping Summary 7 8 9 10 11 Table 21 102 MCBSPLP_REV_REG Address Offset 0x0000 007C Physical Address 0x4807 407C Instance McBSP1 0x4809 607C McBSP5 0x4902 207C McBSP2 0x4902 407C McBSP3 0x49...

Page 3188: ...ster Call Summary for Register MCBSPLP_RINTCLR_REG McBSP Register Manual McBSP Register Mapping Summary 0 1 2 3 4 Table 21 106 MCBSPLP_XINTCLR_REG Address Offset 0x0000 0084 Physical Address 0x4807 4084 Instance McBSP1 0x4809 6084 McBSP5 0x4902 2084 McBSP2 0x4902 4084 McBSP3 0x4902 6084 McBSP4 Description McBSPLP transmit interrupt clear legacy Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ...

Page 3189: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ROVFLCLR Bits Field Name Description Type Reset 31 0 ROVFLCLR Read from this register will clear the IRQ generated by RW 0x00000000 the receive overflow condition Write to this register has no effect legacy Table 21 109 Register Call Summary for Register MCBSPLP_ROVFLCLR_REG McBSP Register Manual McBSP Register Mapping Summary 0 1 2 3 4 3189 SWPU...

Page 3190: ... clock must be maintained during wakeup 0x3 The McBSPi_ICLK clock must be maintained during wakeup The PRCM functional clock must be maintained during wakeup 7 5 RESERVED Read returns 0x0 R 0x0 4 3 SIDLEMODE Slave interface power management idle request RW 0x0 acknowledge control 0x0 Force idle An idle request is acknowledged unconditionally 0x1 No idle An idle request is never acknowledged 0x2 Sm...

Page 3191: ...f interrupt assertion if enabled is triggered if the number of free locations in the transmit buffer are above or equal to the XTHRESHOLD value 1 Also this value XTHRESHOLD value 1 indicates the number of words transferred during a transmit data DMA request if transmit DMA is enabled 1 XTHRESHOLD is an 11 bit field for McBSP2 only For other McBSPs XTHRESHOLD is an 8 bit field bits 7 to 10 are rese...

Page 3192: ...McBSP2 only For other McBSPs RTHRESHOLD is an 8 bit field bits 7 to 10 are reserved In other words the other McBSPs are limited to a FIFO width of 0x7F Table 21 115 Register Call Summary for Register MCBSPLP_THRSH1_REG McBSP Integration Power Management 0 McBSP Functional Description McBSP Reception 1 McBSP DMA Configuration 2 McBSP Basic Programming Model Data Transfer DMA Request Configuration 3...

Page 3193: ...uffer Threshold Reached XRDY bit is set to RW 0x0 one when the transmit buffer free locations are equal or above the THRSH2_REG value Writing 1 to this bit clears the bit 0x0 Transmit buffer occupied locations are below the THRSH2_REG value 0x1 Transmit buffer occupied locations are equal or above the THRSH2_REG value Writing 1 to this bit clears the bit 9 XEOF Transmit End Of Frame XEOF is set to...

Page 3194: ...me REOF is set to one when a RW 0x0 complete frame was received Writing 1 to this bit clears the bit 0x0 complete frame was NOT received 0x1 complete frame was received Writing 1 to this bit clears the bit 1 RFSR Receive Frame Synchronization RFSR bit is set to one RW 0x0 when a new receive frame synchronization is asserted Writing 1 to this bit clears the bit 0x0 new receive frame synchronization...

Page 3195: ...r Empty at end of frame NOT enabled 0x1 Transmit buffer Empty at end of frame enabled 13 RESERVED Read returns 0x0 R 0x0 12 XOVFLEN Transmit Buffer Overflow enable bit RW 0x0 0x0 Transmit Buffer Overflow NOT enabled 0x1 Transmit Buffer Overflow enabled 11 XUNDFLEN Transmit Buffer Underflow enable bit RW 0x0 0x0 Transmit Buffer Underflow NOT enabled 0x1 Transmit Buffer Underflow enabled 10 XRDYEN T...

Page 3196: ...nchronization Error NOT enabled 0x1 Receive Frame Synchronization Error enabled Table 21 119 Register Call Summary for Register MCBSPLP_IRQENABLE_REG McBSP Integration Power Management 0 1 2 3 4 5 6 7 8 Interrupt Requests 9 10 11 12 13 14 15 16 17 18 19 20 21 22 McBSP Functional Description Overrun in the Receiver 23 Unexpected Receive Frame sync Pulse 24 Underflow in the Receiver 25 Underflow in ...

Page 3197: ...s active 7 XSYNCERREN Transmit Frame Synchronization Error WK enable bit RW 0x0 0x0 Transmit Frame Synchronization Error WK enable is NOT active 0x1 Transmit Frame Synchronization Error WK enable is active 6 4 RESERVED Read returns 0x0 R 0x0 3 RRDYEN Receive Buffer Threshold wake up enable bit RW 0x0 0x0 Receive Buffer Threshold WK enable is NOT active 0x1 Receive Buffer Threshold WK enable is act...

Page 3198: ...CLKRM FSRM settings When using this mode the frame synchronization signal must be active during reception of the entire frame FWID must be programmed accordingly to ensure the proper receive process which requires at least 3 cycles after the frame complete to transfer the data into the receive buffer 0x0 External clock gating disabled 0x1 External clock gating enable 14 PPCONNECT Pair to pair conn...

Page 3199: ...e external transmit DMA request 0x1 When set to one this bit will NOT gate the external transmit DMA request 2 1 RESERVED Read returns 0x0 R 0x0 0 XDISABLE Transmit Disable bit When this bit is set the transmit RW 0x0 process will stop at the next frame boundary 0x0 The transmit process will NOT stop at the next frame boundary 0x1 The transmit process will stop at the next frame boundary Table 21 ...

Page 3200: ... Receive DMA Enable bit When set to zero this bit will RW 0x1 gate the external transmit DMA request without resetting the DMA state machine It is recommended to change this bit value only during receive reset 0x0 When set to zero this bit will gate the external transmit DMA request 0x1 When set to one this bit will NOT gate the external transmit DMA request 2 1 RESERVED Read returns 0x0 R 0x0 0 R...

Page 3201: ...ry for Register MCBSPLP_XBUFFSTAT_REG McBSP Functional Description Enable Disable the Transmit and Receive Processes 0 McBSP DMA Configuration 1 McBSP Register Manual McBSP Register Mapping Summary 2 3 4 5 6 Table 21 128 MCBSPLP_RBUFFSTAT_REG Address Offset 0x0000 00B8 Physical Address 0x4807 40B8 Instance McBSP1 0x4809 60B8 McBSP5 0x4902 20B8 McBSP2 0x4902 40B8 McBSP3 0x4902 60B8 McBSP4 Descripti...

Page 3202: ...00 10 SIDETONEEN Sidetone mode enable RW 0x0 0x0 Sidetone disabled 0x1 Sidetone enabled 9 7 OCH1ASSIGN Map the data for the speaker out channels to one of the RW 0x1 McBSP channels 1 out of 8 channels 6 4 OCH0ASSIGN Map the data for the speaker out channels to one of the RW 0x0 McBSP channels 1 out of 8 channels 3 2 ICH1ASSIGN Map the data from digital microphone channels to one of RW 0x1 the McBS...

Page 3203: ...switching and accesses to the McBSP registers are delayed during clock switching To avoid such a situation polling can be performed to status register to evaluate when McBSPLP is ready This information is relevant only for the McBSPLPoperating in slave mode serial clock provided by external component 0 McBSP registers can be accessed 1 The response to a different register access is delayed until t...

Page 3204: ... Mapping Summary 0 1 Table 21 136 ST_SYSCONFIG_REG Address Offset 0x0000 0010 Physical Address 0x4902 8010 Instance SIDETONE_McBSP2 0x4902 A010 SIDETONE_McBSP3 Description SIDETONE System Configuration register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AUTOIDLE Bits Field Name Description Type Reset 31 1 RESERVED Read returns 0x0 R 0x000...

Page 3205: ... 21 139 Register Call Summary for Register ST_IRQSTATUS_REG McBSP Integration Interrupt Requests 0 1 2 3 McBSP Functional Description Interrupt Operation 4 McBSP Register Manual SIDETONE Register Mapping Summary 5 6 Table 21 140 ST_IRQENABLE_REG Address Offset 0x0000 001C Physical Address 0x4902 801C Instance SIDETONE_McBSP2 0x4902 A01C SIDETONE_McBSP3 Description SIDETONE Interrupt enable registe...

Page 3206: ...pe Reset 31 16 CH1GAIN Second sidetone channel gain RW 0x0000 15 0 CH0GAIN First sidetone channel gain RW 0x0000 Table 21 143 Register Call Summary for Register ST_SGAINCR_REG McBSP Functional Description Data Processing 0 McBSP Basic Programming Model SIDETONE Initialization Procedure 1 2 McBSP Register Manual SIDETONE Register Mapping Summary 3 4 Table 21 144 ST_SFIRCR_REG Address Offset 0x0000 ...

Page 3207: ... 0 to 1 The read coefficient address is set to 0 by the change of COEFFWREN from 1 to 0 Table 21 145 Register Call Summary for Register ST_SFIRCR_REG McBSP Basic Programming Model SIDETONE Initialization Procedure 0 1 SIDETONE FIR Coefficients Writing 2 SIDETONE FIR Coefficients Reading 3 McBSP Register Manual SIDETONE Register Mapping Summary 4 5 Table 21 146 ST_SSELCR_REG Address Offset 0x0000 0...

Page 3208: ... 0 all coefficients can be read from SFIRCR_REG by performing 128 read accesses with SIDETONEEN 0 First access reads coefficient index 0 0 SIDETONEEN Sidetone mode enable RW 0x0 0x0 Sidetone disabled 0x1 Sidetone enabled Table 21 147 Register Call Summary for Register ST_SSELCR_REG McBSP Functional Description Data Processing Path 0 Data Processing 1 2 3 McBSP Basic Programming Model SIDETONE Acti...

Page 3209: ...gh speed universal serial bus USB host subsystem and the high speed USB On The Go OTG controller of the device Topic Page 22 1 High Speed USB OTG Controller 3211 22 2 High Speed USB Host Subsystem 3233 3209 SWPU177N December 2009 Revised November 2010 High Speed USB Host Subsystem and High Speed USB OTG Controller Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3210: ...ublic Version www ti com Overview The device contains two USB modules A High Speed USB OTG Controller see Section 22 1 High Speed USB OTG Controller A High Speed USB Host Subsystem see Section 22 2 High Speed USB Host Subsystem Figure 22 1 USB Modules Overview 3210 High Speed USB Host Subsystem and High Speed USB OTG Controller SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas...

Page 3211: ...gh Speed USB OTG Controller Overview The High Speed USB OTG dual role device DRD link controller supports the following modes USB 2 0 peripheral function controller in high full speed 480 12 Mbps respectively USB 2 0 host in high full low speed 480 12 1 5 Mbps respectively with one downstream port but multipoint capability when a hub is connected to it split transaction support etc USB 2 0 OTG DRD...

Page 3212: ...ion 15 transmit endpoints and 15 receive endpoints in addition to control endpoint 0 Each endpoint has its own FIFO with the following properties Implemented within a single 16K byte internal RAM Can be dynamically sized by software Can be configured to hold multiple packets up to 8192 bytes per FIFO Can be accessed either by direct access or by DMA controller Software connect disconnect option fo...

Page 3213: ... manual software controlled generation of PHY side register accesses supporting the following features Access to vendor specific or optional PHY side registers Carkit operation including interrupt PHY side registers Access to vendor ID product ID scratch and debug registers NOTE In the carkit mode the interface must connect to the TI TWL5030 companion chip for proper use The 12 pin ULPI interface ...

Page 3214: ...22 1 Input Output Description Signal Name I O 1 Description Reset Value hsusb0_clk I 60 MHz clock input from ULPI PHY 2 n a hsusb0_dir I Data direction control from ULPI PHY n a hsusb0_stp O Stop signal to ULPI PHY 1 hsusb0_nxt I Next signal from ULPI PHY n a hsusb0_data0 I O Bidirectional DATA0 n a hsusb0_data1 I O Bidirectional DATA1 n a hsusb0_data2 I O Bidirectional DATA2 n a hsusb0_data3 I O ...

Page 3215: ...fic within the device The L4 Core interconnect is a configuration port for register setting Figure 22 5 highlights the high speed USB controller integration in the device Figure 22 5 High Speed USB Controller Integration 22 1 3 1 Clocking Reset and Power Management Scheme 22 1 3 1 1 Clocks 22 1 3 1 1 1 Module Clocks Three clocks are provided to the high speed USB controller as shown in Table 22 2 ...

Page 3216: ...nfiguration bit software reset in the module 22 1 3 1 2 1 Hardware Reset The high speed USB controller is attached to the CORE power domain The CORE_RST signal resets the module see Chapter 3 Power Reset and Clock Management The hardware reset signal has a global reset action on the high speed USB controller 22 1 3 1 2 2 Software Reset The high speed USB controller has a software reset through the...

Page 3217: ...d on the USBOTG OTG_SYSCONFIG 13 12 MIDLEMODE field Smart standby The high speed USB controller is configured in smart standby mode USBOTG OTG_SYSCONFIG 13 12 MIDLEMODE field 0x2 The module is ready to enter standby mode MSTANDBY is asserted when there is no more activity on the USB master interface of the interconnect MSTANDBY is asserted when the module is idle and deasserted when the module is ...

Page 3218: ... activity The idle acknowledge then is asserted and the module waits for active system clock gating by the PRCM module this occurs only when all peripherals supplied by the same L3 clock domain are also ready for idle Once in idle mode when the PRCM module gates the interface clock the module has no activity the interface clock paths are gated no interrupt request can be generated and the module i...

Page 3219: ...PRCM module register bit PM_WKST1_CORE 4 Read 0 Wakeup has not occurred or was masked Read 1 Wakeup has occurred Write 0 Status bit unchanged Write 1 Status bit is cleared to 0 22 1 3 1 3 3 Local Power Management The high speed USB controller has local power management by internal clock gating features Internal interface clock autogating Clock for the L3 interconnect logic can be gated when the mo...

Page 3220: ...CM requiring the high speed USB controller to enter idle mode The high speed USB controller acknowledges when it is ready 22 1 3 2 3 MSTANDBY Handshake Protocol The PRCM module handles an MSTANDBY handshake protocol for the high speed USB controller which initiates the MSTANDBY handshake to inform the PRCM module when it enters standby mode and does not generate traffic on interconnect 22 1 3 2 4 ...

Page 3221: ...e adaptation integration of this IP to comply with TI requirements The high speed USB controller includes the following MUSBMHDRC USB 2 0 controller Master and slave bridges for conversion AHB to L3 interconnect and L3 interconnect to AHB Two memories total of 16Kbytes available for various endpoints Reset and clock generation Figure 22 6 shows the high speed USB controller Figure 22 6 High Speed ...

Page 3222: ...ng steps are performed 22 1 4 3 1 Module Initialization First the firmware must do the overall initialization of the module by configuring the interrupts the DMA controller and the individual endpoints The specific items of a configuration are for each endpoint Direction TX RX Speed High full low Special host settings when used in host mode function address hub parameters etc Transaction protocol ...

Page 3223: ...acket When the packet is successfully sent scheduled according to the protocol rules the appropriate TX interrupt is generated 22 1 4 4 Optional Features This section gives a quick overview of the optional features that are available depending on the endpoint configuration 22 1 4 4 1 Double Packet Buffering When double packet buffering is enabled by setting the MSB of the FIFOSZ register two data ...

Page 3224: ...quired in the control path slave interface The OCP master interface a submodule within the OCP wrapper supports big endian conversion by setting the OTG_BIGENDIAN 0 BIG_ENDIAN bit to 0x1 For interconnect write transactions the data word is swapped as shown in Table 22 7 before its output on the interconnect master interface In case of an interconnect read transaction the received data is swapped b...

Page 3225: ...interrupts DMA request mode 0 is especially advisable for isochronous transfers but can also be used for bulk and interrupt transfers DMA request mode 1 is mainly valuable for bulk transfers where typically a large block of data is split into a series of packets of the maximum size 22 1 4 4 3 1 DMA Request Mode 0 For RX endpoints the DMA transfer is initiated when a data packet is available in the...

Page 3226: ...ata transfer rate of up to 3072 bytes per microframe see Universal Serial Bus Specification Revision 2 0 For TX endpoints the high speed USB controller supports this by allowing loading data packets of up to 3072 bytes that is 3 x 1024 bytes into the associated endpoint FIFO which is then automatically split into USB packets of the maximum payload or smaller to be transmitted in one microframe For...

Page 3227: ...bling the internal clock autogating feature cuts off the module internal interface clock as soon as it is no longer required This is done by setting the USBOTG OTG_SYSCONFIG 0 AUTOIDLE bit to 1 The optimal configuration when the high speed USB controller is not used by the application is as follows Master interface power management is in force standby mode USBOTG OTG_SYSCONFIG 13 12 MIDLEMODE fiel...

Page 3228: ... power management in smart standby mode Slave interface power management in smart idle mode Internal clock autogating feature enabled MSTANDBY signal assertion disabled See Section 22 1 5 4 2 and Section 22 1 5 4 3 for the programming sequence As an application required to disable the master interface the high speed USB controller can also be programmed as follows Master interface power management...

Page 3229: ...G_REVISION R 32 0x400 0x480A B400 OTG_SYSCONFIG RW 32 0x404 0x480A B404 OTG_SYSSTATUS R 32 0x408 0x480A B408 OTG_INTERFSEL RW 32 0x40C 0x480A B40C OTG_SIMENABLE RW 32 0x410 0x480A B410 OTG_FORCESTDBY RW 32 0x414 0x480A B414 OTG_BIGENDIAN RW 32 0x418 0x480A B418 22 1 6 1 2 High Speed USB Register Description Table 22 10 OTG_REVISION Address Offset 0x0000 0400 Physical Address Instance USBHS See Tab...

Page 3230: ...ol Req ack control RW 0X0 0x0 Force Idle mode Sidleack asserted after Midlereq assertion 0x1 No idle mode Sidleack never asserted 0x2 SmartIdle mode Sidleack asserted after Midlereq assertion when no more activity on the USB 2 ENABLEWAKEUP Enable wakeup capability RW 0 0x0 Wakeup disabled 0x1 Wakeup enabled 1 SOFTRESET Software reset bit RW 0 0x1 Starts softreset sequence 0 AUTOIDLE Autoidle bit R...

Page 3231: ...e USBHS See Table 22 9 Description USB OTG HS interface selection Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PHYSEL Bits Field Name Description Type Reset 31 2 RESERVED Reserved R 0x0000 0000 1 0 PHYSEL PHY interface selection RW 0x1 0x0 PHY interface is 8 bit UTMI level 3 Not supported in the device 0x1 PHY interface is 12 pin 8 bit SDR ...

Page 3232: ...ler Registers 1 Table 22 20 OTG_FORCESTDBY Address Offset 0x0000 0414 Physical Address Instance USBHS See Table 22 9 Description Enabling MSTANDBY in FORCESTANDBY mode Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ENABLEFORCE Bits Field Name Description Type Reset 31 1 RESERVED Reserved R 0x0000 0000 0 ENABLEFORCE Enabling MSTANDBY to go hig...

Page 3233: ...CI controller based on the Enhanced Host Controller Interface EHCI specification for USB Release 1 0 is in charge of high speed traffic 480M bit s over the ULPI UTMI interface The OHCI controller based on the Open Host Controller Interface OHCI specification for USB Release 1 0a is in charge of full speed low speed traffic 12 1 5M bit s respectively over a serial interface Each of the three device...

Page 3234: ...t Subsystem www ti com Figure 22 8 High Speed USB Host Subsystem Highlight 22 2 1 1 Main Features The high speed USB host subsystem includes the following features Multiport high speed USB host controller Complies with the USB 2 0 standard for high speed 480 Mbps functions USB 2 0 low speed 1 5M bit s full speed 12M bit s and high speed 480M bit s operations Three downstream ports 3 port root hub ...

Page 3235: ...odes or a serial PHY PHY interface modes Supports 6 pin unidirectional 4 pin bidirectional 3 pin bidirectional 2 pin bidirectional modes All modes are supported for TLL or PHY interface configuration Supports sideband signals pullup down control speed suspend enable etc An interrupt line USB port signal pins interface supporting External USB transceivers ULPI interface 12 pin 8 bit data SDR versio...

Page 3236: ... ULPI transceivers are not supported on port 3 WARNING The three channels when in ULPI mode are always ULPI clock providers an input clock is not accepted 3236 High Speed USB Host Subsystem and High Speed USB OTG Controller SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3237: ... pin mode DAT SE0 bidirectional mode and 2 pin mode DAT SE0 and DP DM bidirectional modes 22 2 2 1 Standard USB Implementation Transceiver Connection From a logical point of view a point to point USB connection is composed of several blocks organized in protocol layers and shown in Figure 22 9 Figure 22 9 USB Connection The host system USB master and the peripheral system USB slave connected throu...

Page 3238: ...mpared to a typical USB implementation The top portion of Figure 22 10 shows the a transceiver based solution and the bottom portion shows a transceiverless solution using TLL Figure 22 10 High Speed USB Host Controller Connection With and Without TLL NOTE The USB bus lines D D no longer appear in subsequent figures They are emulated by the TLL 22 2 2 3 ULPI Interfaces The high speed USB host subs...

Page 3239: ...ULPI transceiver HS ULPI transceiver ULPI Interfaces USBTLL is bypassed and high speed USB host controller ports 1 and 2 are connected directly to external transceivers Public Version www ti com High Speed USB Host Subsystem Figure 22 11 and Figure 22 12 show typical applications using the high speed USB host subsystem with the ULPI and the ULPI TLL respectively Figure 22 11 High Speed USB Host Co...

Page 3240: ...pheral controller DDR High speed USB peripheral controller SDR High speed USB peripheral controller DDR ULPI TLL Interfaces The high speed USB host controller is coupled with the USBTLL module to compose the ULPITLL interface modes usb 032 Public Version High Speed USB Host Subsystem www ti com Figure 22 12 High Speed USB Host Subsystem Typical Application System ULPI TLL Interfaces The current im...

Page 3241: ...8 bit data SDR version of the ULPI interface mode NOTE In the device only the ULPI ports 1 and 2 of the high speed USB host controller are mapped and can be connected directly to external transceivers Figure 22 13 shows USB ports using the 12 pin 8 bit data SDR version of the ULPI interface mode Figure 22 13 ULPI Interfaces 12 Pin 8 Bit Data SDR Version 22 2 2 3 2 TLL Configurations The high speed...

Page 3242: ...t hsusbx_tll_dir hsusbx_tll_stp hsusbx_tll_data0 hsusbx_tll_data1 hsusbx_tll_data2 hsusbx_tll_data4 hsusbx_tll_data3 hsusbx_tll_data5 hsusbx_tll_data6 hsusbx_tll_clk hsusbx_tll_data7 NXT DATA1 DATA0 CLK STP DIR Public Version High Speed USB Host Subsystem www ti com Figure 22 14 ULPI TLL Interfaces 12 Pin 8 Bit Data SDR Version Figure 22 15 shows USB ports using the 8 pin 4 bit data DDR version of...

Page 3243: ... hsusb1_data2 hsusb1_data4 hsusb1_data3 hsusb1_data5 hsusb1_data6 hsusb1_clk hsusb1_data7 hsusb3_tll_nxt hsusb3_tll_dir hsusb3_tll_stp hsusb3_tll_data0 hsusb3_tll_data1 hsusb3_tll_data2 hsusb3_tll_data4 hsusb3_tll_data3 hsusb3_tll_data5 hsusb3_tll_data6 hsusb3_tll_clk hsusb3_tll_data7 High speed USB Host Controller Public Version www ti com High Speed USB Host Subsystem 22 2 2 3 3 High Speed USB H...

Page 3244: ...irectional DATA0 0 hsusb1_tll_data1 I O Bidirectional DATA1 0 hsusb1_tll_data2 I O Bidirectional DATA2 0 hsusb1_tll_data3 I O Bidirectional DATA3 0 hsusb1_tll_data4 I O Bidirectional DATA4 0 hsusb1_tll_data5 I O Bidirectional DATA5 0 hsusb1_tll_data6 I O Bidirectional DATA6 0 hsusb1_tll_data7 I O Bidirectional DATA7 0 HSUSB2 hsusb2_clk O 60 MHz clock output to ULPI transceiver 2 0 hsusb2_dir I Dat...

Page 3245: ...I O Bidirectional DATA3 0 hsusb3_tll_data4 I O Bidirectional DATA4 0 hsusb3_tll_data5 I O Bidirectional DATA5 0 hsusb3_tll_data6 I O Bidirectional DATA6 0 hsusb3_tll_data7 I O Bidirectional DATA7 0 ULPI PHY Interfaces and ULPI TLL Interfaces can not be used together Either the ULPI PHY Interfaces or the ULPI TLL Interfaces are selected 22 2 2 4 Serial Interfaces The high speed USB host subsystem s...

Page 3246: ...m Figure 22 17 High Speed USB Host Subsystem Typical Application System The high speed USB host controller is coupled with the USBTLL module to compose the serial interface modes The USBTLL module translates the parallel synchronous UTMI Level 3 protocol to a serial asynchronous one The benefit of the conversion is a simplified interface to the transceiver CAUTION Only full and low speed data tran...

Page 3247: ...eed USB Host Subsystem and 6 Pin Unidirectional USB Transceiver DAT SE0 Signaling Logical Signal Name Device Pin Transceiver Pin Description Direction Direction TXEN Output Input When low the USB transceiver drives D and D DAT and SE0 Output Input Controls the values output by the USB transceiver on D and D when TXEN is low high ignored when TXEN is high low depending on the TXEN signal polarity s...

Page 3248: ...D D 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 X X Undriven Undriven RCV Input Output Output from transceiver differential receiver D D RCV 0 0 X 0 1 0 1 0 1 1 1 X DP Input Output Output from transceiver single ended D signal receiver D DP 0 0 1 1 DM Input Output Output from transceiver single ended D signal receiver D DM 0 0 1 1 22 2 2 4 1 2 Bidirectional When a USB or USB OTG transceiver is connected to th...

Page 3249: ...aling using DP DM signals When a USB or USB OTG transceiver is connected to the device and is used in 4 pin bidirectional DP DM encoding mode the encoding described in Table 22 29 is used Table 22 29 Signaling Between High Speed USB Host Subsystem and 4 Pin Bidirectional USB Transceiver Using DP DM Signaling Logical Signal Device Pin Transceiver Pin Description Name Direction Direction TXEN Output...

Page 3250: ...ntroller to transceiver in the two figures the sideband information flow is bidirectional that is it flows from controller to transceiver control but also from transceiver to controller status Figure 22 18 shows the transceiver configuration where each side connects the sideband signals to its own transceiver On the device containing the USBTLL module the sideband is decoded re encoded The sideban...

Page 3251: ...speed USB subsystem in the serial interface mode and the external USB transceiver for monitoring and controlling the differential USB signal can be done through a 6 4 or 3 wire signaling interface with two or more control signals provided either by additional signals or through an I2 C link The following subsections describe the transceiver interface modes supported by the high speed USB host subs...

Page 3252: ...using DP DM encoding Figure 22 21 6 Pin Unidirectional Using DP DM Signaling 22 2 2 4 3 2 Bidirectional Transceiver Interface Modes 3 Pin 4 Pin The bidirectional transceiver interface modes are pin count optimizations of the unidirectional modes They take advantage of the fact that a USB port is either sending or receiving at any given time but never both The TX and RX paths of the unidirectional ...

Page 3253: ...idirectional signaling using DP DM signals Figure 22 22 shows a USB port using DAT SE0 encoding Figure 22 22 3 Pin Bidirectional Using DAT SE0 Signaling The signaling listed in Table 22 29 is used when a USB transceiver is connected to the device and is used in 4 pin bidirectional DP DM signaling mode NOTE The device does not support 4 pin bidirectional signaling using DAT SE0 signals Figure 22 23...

Page 3254: ...y Transceiver interface is serial its frequency is that of the actual USB line and combinatorial no clock is passed 22 2 2 4 4 1 Unidirectional TLL Modes The 6 pin TLL configurations are mirror images of the 6 pin transceiver configurations presented above The same signals are mapped on the same physical pins but in the opposite directions Two possible modes exist depending on the TX data encoding...

Page 3255: ...ling 22 2 2 4 4 2 Bidirectional TLL Modes The 3 pin 4 pin TLL configurations are mirror images of the 3 pin 4 pin transceiver configurations presented above The same signals are mapped on the same physical pins but in the opposite directions bidirectional lines remain bidirectional Two possible modes exist depending on the TX data encoding used by the external device Figure 22 26 shows an external...

Page 3256: ...7 4 Pin Bidirectional TLL Using DP DM Signaling The 2 pin TLL configurations have unique specifications They require pullups pulldowns to operate because the bidirectional lines are not driven at all times like the other serial transceiver interfaces described above The connection of pull resistors depends on the speed of the controller The module supports explicit 2 pin TLL modes with either DAT ...

Page 3257: ...peed Low Speed Device Full Speed Device DP Pulldown Pulldown Pullup DM Pulldown Pullup Pulldown Figure 22 29 shows a USB port using DAT SE0 encoding Figure 22 29 2 Pin Bidirectional TLL Using DAT SE0 Encoding With 3 Pin Bidirectional USB Device Table 22 31 shows pullup pulldown configuration for DAT SE0 encoding Table 22 31 Pullup Pulldown Configuration for DAT SE0 Encoding Nonconnected Device Con...

Page 3258: ...bidirectional DP DM TLL or 6 pin unidirectional TLL modes not used in the 3 pin bidirectional DAT SE0 TLL or 2 pin bidirectional TLL modes mm1_rxdp I Single ended DP receiver signal input in 6 pin unidirectional modes not used in n a the 3 pin bidirectional DAT SE0 or 4 pin bidirectional DP DM modes O Single ended DP receiver signal output in 6 pin unidirectional TLL modes not used in the 3 pin bi...

Page 3259: ...ectional DAT SE0 TLL or 4 pin bidirectional DP DM TLL or 2 pin bidirectional TLL modes Multiple mode FS LS serial interface Port 3 mm3_txse0 I O SE0 function in 3 pin bidirectional DAT SE0 mode 0 I O DM function in 4 pin bidirectional DP DM mode O SE0 output in 6 pin unidirectional DAT SE0 mode O DM output in 6 pin unidirectional DP DM mode I O SE0 TLL in 2 3 pin bidirectional DAT SE0 TLL mode I O...

Page 3260: ...idirectional DP DM TLL or 2 pin bidirectional TLL modes 22 2 3 High Speed USB Host Subsystem Integration This section describes the integration of the high speed USB host subsystem The high speed USB host controller is connected to the L3 interconnect master initiator and L4 Core interconnect slave target interfaces The USBTLL module is connected to the L4 Core interconnect slave target interface ...

Page 3261: ..._IRQ EHCI_IRQ EHCI controller Channel 2 Channel 1 Channel 0 ULPI ULPI UTMI UTMI UTMI Public Version www ti com High Speed USB Host Subsystem Figure 22 30 High Speed USB Subsystem Integration 22 2 3 1 Reset Clocking and Power Management Scheme The high speed USB host controller belongs to the USBHOST power domain As part of the USBHOST power domain it is sensible to the USBHOST_RST reset signal iss...

Page 3262: ...ware reset signal has a global reset action on the high speed USB host controller see Chapter 3 Power Reset and Clock Management Hardware USBTLL_RESET PRCM USBTLL_RST Active low The USBTLL_RST signal resets signal asynchronously the module The hardware reset signal has a global reset action on the USBTLL module see Chapter 3 Power Reset and Clock Management 22 2 3 1 1 1 Hardware Resets The high sp...

Page 3263: ...K output clock UBTLL_FCLK is controlled by the PRCM CM_FCLKEN3_CORE 2 EN_USBTLL bit 0 Disabled 1 Enabled USBTLL_ICLK is the USBTLL module interface clock It is used to synchronize USBTLL module L4 port to L4 interconnect All accesses from the interconnect are synchronous to USBTLL_ICLK Its source is the PRCM CORE_L4_ICLK output clock USBTLL_ICLK is controlled by the PRCM CM_ICLKEN3_CORE 2 EN_USBTL...

Page 3264: ... by the USBTLL module USBTLL_ICLK in the subsystem and comes from the PRCM module This clock is controlled by the PRCM register bits PRCM CM_ICLKEN3_CORE 2 0 Disabled 1 Enabled and PRCM CM_AUTOIDLE3_CORE 2 enables disables automatic control of the interface clock see Table 22 36 Table 22 36 USBTLL Module Interface Clock PRCM CM_AUTOIDLE3_CORE 2 PRCM CM_ICLKEN3_CORE 2 Interface Clock 0 0 Disabled 0...

Page 3265: ...anagement is applied only to the interface clock domain The high speed USB host controller has both master initiator and slave target interfaces As an initiator the high speed USB host controller implements the standby handshake protocol to inform the PRCM module when it enters standby mode and does not generate traffic on the interconnect As a target the high speed USB host controller implements ...

Page 3266: ...ocedure to turn off the interface clock if needed This procedure must be implemented using the slave power management protocol The handshake mechanism lets the module go to standby mode based on the USBHOST UHH_SYSCONFIG 13 12 MIDLEMODE field Table 22 38 High Speed USB Host Controller MIDLEMODE Settings MIDLEMODE Selected Description Value Mode 0x0 Force The high speed USB host controller enters s...

Page 3267: ...Clock Effect Description Value 0 OFF Interface clock is considered for generating the acknowledgment This setting also means the interface clock is shut down upon PRCM IDLE request 1 ON Interface clock is not shut down upon PRCM IDLE request The high speed USB host controller can potentially acknowledge the IDLE request without checking the internal functionalities linked to its clock CAUTION The ...

Page 3268: ...owledges unconditionally the IDLE request from the PRCM regardless of its internal operations Because such a mode does not prevent any loss of data when the clock is switched off the mode must be used carefully 0x1 No idle The USBTLL module never acknowledges any IDLE request from the PRCM This mode is safe from a module point of view as it ensures the clocks remain active however it is not effici...

Page 3269: ...ontroller HS USB EHCI Host Controller Interrupt EHCI_IRQ M_IRQ_77 Destination is MPU subsystem interrupt controller USBTLL Module Interrupt TLL_IRQ M_IRQ_78 Destination is MPU subsystem interrupt controller 22 2 3 2 2 IDLE Handshake Protocol The PRCM handles an IDLE handshake protocol for the high speed USB host controller and the USBTLL module The IDLE handshake protocol allows the PRCM requiring...

Page 3270: ... 22 31 shows an overview of the high speed USB host controller internal architecture It contains two independent 3 port host controllers that operate in parallel EHCI and OHCI Each of the three external ports is owned by exactly one of the controllers at any point in time Each port can work in several modes When the port is owned by the OHCI full speed host controller the serial 6 pin interface mo...

Page 3271: ... reflected in the register descriptions see Section 22 2 6 4 3 OHCI Registers For all standard features see the Open Host Controller Interface OHCI specification for USB Release 1 0a USBHOST HCFMINTERVAL 30 16 FSMPS field FullSpeedMaxPacketSize 0x0000 Host will stop scheduling new packets 0 bit times before the end of the frame that is there is no scheduling overrun protection by default To be upd...

Page 3272: ... from 1 through N In USB terminology port 0 is necessarily an upstream port and because the host is on top of the USB topological tree it has none In the current implementation N 3 that is available ports are 1 2 3 The high speed USB host controller is configured to be either in UTMI or in ULPI mode see each port configuration with the USBHOST UHH_HOSTCONFIG 12 P3_ULPI_BYPASS USBHOST UHH_HOSTCONFI...

Page 3273: ...rotocol has been selected during an initial configuration phase USB operation should take place seamlessly that is as if actual transceivers were present To ensure maximum compatibility as many features as possible have been included as described in the rest of this document The basic principle is that all the software handles should be available and behave in a proper way even if there is no actu...

Page 3274: ...llel synchronous high speed capable interfaces Line arrows represent serial combinatorial full speed low speed only interfaces Arrows always point toward the PHY layer actual transceiver or TLL in yellow away from the link controller The arrow marked ULPI represents the entire ULPI protocol synchronous or not except the 3 6 pin serial TLL modes which are reoriented toward the serial TLL block The ...

Page 3275: ...SB data and control injected on one side or port comes out on the other side or port after a certain amount of processing depending on the mode Table 22 46 lists the modes All configurations connect the PHY UTMI port attached to the high speed USB host controller to one of the other two ports attached to a variety of transceivers or controllers on the pads side Table 22 46 describes the available ...

Page 3276: ... only also serial PHY i f UTMI 6pin TLL Phy if D 6pin test 6p UTMI A 6pin C ULPI 3 6p ULPI 2 3 4 6pin 2 3 4 6pin usb 031 Splitter only 1 active port 2 Sync UTMI to sync ULPI TLL config HS FS LS 4 Serial UTMI to serial ULPI TLL config FS LS 6 Serial UTMI to serial ULPI TLL or PHY config Public Version High Speed USB Host Subsystem www ti com Figure 22 33 Per Configuration Datapath Through USBTLL 32...

Page 3277: ...d to be taken care of separately from the USBTLL module that is by software and straight to the power IC which can be the transceiver itself especially in OTG cases VBUS status must be sampled by the appropriate hardware again most of the time the transceiver itself and reported by software to the USBTLL module using the USBHOST TLL_CHANNEL_CONF_i DRVVBUS and CHRGVBUS bits as indicated in Table 22...

Page 3278: ...et to 1 to drive VBUS to 5 V for A device or host CHRGVBUS Set to 1 to pullup VBUS for SRP There is no pulldown discharge control because the emulated VBUS has no latency and VBUS level goes to the session end level as soon as it is neither driven nor pulled up Alternatively VBUS drive can also be hardware controlled through a dedicated input DRVVBUS register bit and input signal are actually ORed...

Page 3279: ...er and RXRCV kept unused 2 Same remark on TXDAT for outputs and RXRCV TXDAT only is enough 22 2 4 2 6 Attach Connect Emulation for Serial TLL Modes This section applies to all serial TLL modes In UTMI to serial mode USBHOST TLL_CHANNEL_CONF_i 2 1 CHANMODE field 0x1 for all TLL values of USBHOST TLL_CHANNEL_CONF_i 27 24 FSLSMODE field 0x4 to 0x7 0xA to 0xB In UTMI to ULPI TLL mode USBHOST TLL_CHANN...

Page 3280: ...ore switching off save save it to an external always on memory and reinject it later after the module has been switched on again and reset restore seamlessly for the USB Part of that context is composed of the register fields described in the current chapter The rest of the context is composed of the buried flip flops and memories not accessible by software like FSM states buffer contents and misc...

Page 3281: ... hsusbi usb 034 i 1 2 or 3 TLL_CHANNEL_CONF_i 27 24 FSLSMODE field Public Version www ti com High Speed USB Host Subsystem Table 22 51 USBTLL Registers Impacted by the SAR Context continued Register Name Comments on SAR Policy ULPI_VENDOR_INT_EN_i ULPI_VENDOR_INT_STATUS_i 22 2 5 High Speed USB Host Subsystem Basic Programming Model 22 2 5 1 Selecting and Configuring USB Connectivity Perform the fo...

Page 3282: ...LL interface selection and serial interface selection there is no restriction and port 3 can be configured in any ULPI TLL or serial mode When the USBHOST UHH_HOSTCONFIG 11 P2_ULPI_BYPASS bit is 1 the ULPI TLL interface selection and serial interface selection there is no restriction and port 2 can be configured in any ULPI TLL or serial mode When the USBHOST UHH_HOSTCONFIG 0 P1_ULPI_BYPASS bit is...

Page 3283: ...s TLL configurations Serial 6 pin TLL interfaces 6 pin unidirectional TX DAT SE0 or TX DP DM 4 pin bidirectional 3 pin bidirectional and 2 pin bidirectional modes The high speed USB host controller is coupled with the USBTLL module to compose the serial interface modes The high speed USB host controller uses its UTMI ports bypassing the ULPI ports The USBHOST UHH_HOSTCONFIG 12 P3_ULPI_BYPASS USBHO...

Page 3284: ...Y side registers per ULPI specification Those registers are All ULPI mandatory standard registers and fields A selection of ULPI optional standard registers and fields when relevant to the TLL context Vendor specific registers mapped at the addresses specified for that purpose in ULPI specification Those registers are accessed by the external that is off chip link controller over the ULPI port of ...

Page 3285: ...d Extended accesses to this address have no effect Some physical registers are accessible at more than one address where write accesses perform different actions on the register value over write set clear A read to any of the addresses returns the register value The names of the set and clear registers are the write name postfixed with respectively _SET and _CLR The register fields are described o...

Page 3286: ..._CONF_i 1 RW 32 0x0000 0040 0x04 i 0x4806 2040 0x04 i ULPI_VENDOR_ID_LO_i 1 R 8 0x0000 0800 0x100 i 0x4806 2800 0x100 i ULPI_VENDOR_ID_HI_i 1 R 8 0x0000 0001 0x100 i 0x4806 2801 0x100 i ULPI_PRODUCT_ID_LO_i 1 R 8 0x0000 0002 0x100 i 0x4806 2802 0x100 i ULPI_PRODUCT_ID_HI_i 1 R 8 0x0000 0003 0x100 i 0x4806 2803 0x100 i ULPI_FUNCTION_CTRL_i 1 RW 8 0x0000 0004 0x100 i 0x4806 2804 0x100 i ULPI_FUNCTIO...

Page 3287: ...00 i ULPI_UTMI_VSTATUS_CLR_i 2 RW 8 0x0000 0037 0x100 i 0x4806 2837 0x100 i ULPI_USB_INT_LATCH_NOCLR_i 2 R 8 0x0000 0038 0x100 i 0x4806 2838 0x100 i ULPI_VENDOR_INT_EN_i 2 RW 8 0x0000 003B 0x100 i 0x4806 283B 0x100 i ULPI_VENDOR_INT_EN_SET_i 2 RW 8 0x0000 003C 0x100 i 0x4806 283C 0x100 i ULPI_VENDOR_INT_EN_CLR_i 2 RW 8 0x0000 003D 0x100 i 0x4806 283D 0x100 i ULPI_VENDOR_INT_STATUS_i 2 R 8 0x0000 0...

Page 3288: ...e OHCI USB standard Open Host controller Interface Specification for USB Release 1 0a For more information about these registers or for new specification releases search OHCI on www usb org Table 22 59 EHCI Registers Mapping Summary Register Name Type Register Address Offset Physical Address Width Bits HCCAPBASE R 32 0x0000 0000 0x4806 4800 HCSPARAMS R 32 0x0000 0004 0x4806 4804 HCCPARAMS R 32 0x0...

Page 3289: ...encoded Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MAJOR MINOR Bits Field Name Description Type Reset 31 8 RESERVED Reserved R 0x000000 7 4 MAJOR Major revision number R 0x0 3 0 MINOR Minor revision number R 0x1 Table 22 61 Register Call Summary for Register USBTLL_REVISION High Speed USB Host Subsystem High Speed USB Host Subsystem Regist...

Page 3290: ...reset W 0x0 0x0 No effect 0x1 Starts softreset sequence 0 AUTOIDLE Internal autogating control RW 0x1 0x0 Clock always running 0x1 When no activity on L3 interconnect clock is cut off Table 22 63 Register Call Summary for Register USBTLL_SYSCONFIG High Speed USB Host Subsystem Reset Clocking and Power Management Scheme 0 1 2 3 USBTLL Module Functionality 4 High Speed USB Host Subsystem Register Su...

Page 3291: ...t pending 0x1 Event pending 1 FCLK_END Functional clock is no longer requested for USB clocking RW 0x0 When TLL_SHARED_CONF 1 FCLK_REQ 0 and TLL_SHARED_CONF 0 FCLK_IS_ON 1 IRQ is generated to request the clock to be switched OFF and FCLK_END is set to 1 0x0 No event pending 0x1 Event pending 0 FCLK_START Functional clock is requested for USB clocking RW 0x0 When TLL_SHARED_CONF 1 FCLK_REQ 1 and TL...

Page 3292: ... 1 0x0 IRQ event is masked 0x1 IRQ event is enabled 0 FCLK_START_EN IRQ event mask for FCLK_START interrupt see RW 0x0 USBTLL_IRQSTATUS 0 0x0 IRQ event is masked 0x1 IRQ event is enabled Table 22 69 Register Call Summary for Register USBTLL_IRQENABLE High Speed USB Host Subsystem USBTLL Module Functionality 0 High Speed USB Host Subsystem Register Summary 1 Table 22 70 TLL_SHARED_CONF Address Offs...

Page 3293: ...s 2 5 32 0x6 Div ratio is 2 6 64 0x7 Div ratio is 2 7 128 1 FCLK_REQ Functional clock request ORed from all channels R 0x0 depending on their respective USB bus state Combined with the Fclk_is_on status to generate fclk_start end IRQs 0x0 Func clock input is not requested by TLL 0x1 Func clock input is requested by TLL 0 FCLK_IS_ON Status of the functional clock input provided by the RW 0x0 system...

Page 3294: ...ct in other main modes 0x0 6pin unidirectional PHY i f mode TX encoding is Dat Se0 default 0x1 6 pin unidirectional PHY i f mode TX encoding is Dp Dm 0x2 3 pin bidirectional PHY i f mode 0x3 4 pin bidirectional PHY i f mode 0x4 6pin unidirectional TLL mode TX encoding is Dat Se0 0x5 6pin unidirectional TLL mode TX encoding is Dp Dm 0x6 3 pin bidirectional TLL mode 0x7 4 pin bidirectional TLL mode ...

Page 3295: ...delays non standard 10 ULPIAUTOIDLE For ChanMode ULPI TLL only Allow the ULPI output RW 0x1 clock to be stopped when ULPI goes into asynchronous mode low power 3 pin serial 6 pin serial No effect in ULPI input clock mode 0x0 ULPI output clock always on 0x1 ULPI output clock stops during asynchronous ULPI modes 9 UTMIAUTOIDLE For ChanMode ULPI TLL only Allow the UTMI clock RW 0x1 output to be stopp...

Page 3296: ...2 Transparent UTMI mode To UTMI PHY 0x3 No mode selected 0 CHANEN Active high channel enable A disabled channel is RW 0x0 unclocked and kept under reset 0x0 Channel N disabled 0x1 Channel N enabled Table 22 73 Register Call Summary for Register TLL_CHANNEL_CONF_i High Speed USB Host Subsystem USBTLL Module Functionality 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Selecting and Configuring USB Connect...

Page 3297: ...2 0x100 i Instance USBTLL Description Lower byte of vendor chosen 16 bit product ID Value is set for all channels by HDL generic ULPI_PRODUCTID Type R 7 6 5 4 3 2 1 0 PRODUCT_ID_LO Bits Field Name Description Type Reset 7 0 PRODUCT_ID_LO R 0x00 Table 22 79 Register Call Summary for Register ULPI_PRODUCT_ID_LO_i High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22...

Page 3298: ...r set 0x0 No ongoing reset no action 0x1 Ongoing reset apply reset 4 3 OPMODE Select the required bit encoding style during transmit RW 0x0 0x0 Normal operation 0x1 Non driving 0x2 Disable bit stuff and NRZI encoding 0x3 Reserved 2 TERMSELECT Controls the internal 1 5Kohms pull up resistor and RW 0x0 45ohms HS terminations Control over bus resistors changes depending on XcvrSelect OpMode DpPulldow...

Page 3299: ... RW 0x0 Write 0x0 No effect on bit value Write 0x1 Set the bit to 1 2 TERMSELECT Controls the internal 1 5Kohms pull up resistor and RW 0x0 45ohms HS terminations Control over bus resistors changes depending on XcvrSelect OpMode DpPulldown and DmPulldown Write 0x0 No effect on bit value Write 0x1 Set the bit to 1 1 0 XCVRSELECT Select the required transceiver speed RW 0x0 Write 0x0 No effect on bi...

Page 3300: ...0 XCVRSELECT Select the required transceiver speed RW 0x0 Write 0x0 No effect on bit value Write 0x1 Clear the bit to 0 Table 22 87 Register Call Summary for Register ULPI_FUNCTION_CTRL_CLR_i High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 88 ULPI_INTERFACE_CTRL_i Address Offset 0x0000 0007 0x100 i Index i 0 to 2 Physical Address 0x4806 2807 0x100 i Instance...

Page 3301: ...FACE_CTRL_i High Speed USB Host Subsystem USBTLL Module Functionality 0 1 2 High Speed USB Host Subsystem Register Summary 3 Table 22 90 ULPI_INTERFACE_CTRL_SET_i Address Offset 0x0000 0008 0x100 i Index i 0 to 2 Physical Address 0x4806 2808 0x100 i Instance USBTLL Description Enables alternative interfaces and PHY features Read set address write 1 to a bit to set it to 1 writing 0 has no effect o...

Page 3302: ...tem Register Summary 0 Table 22 92 ULPI_INTERFACE_CTRL_CLR_i Address Offset 0x0000 0009 0x100 i Index i 0 to 2 Physical Address 0x4806 2809 0x100 i Instance USBTLL Description Enables alternative interfaces and PHY features Read clear address write 1 to a bit to clear it to 0 writing 0 has no effect on bit value See fields description at the read write address of the same register Type RW 7 6 5 4 ...

Page 3303: ...00 i Index i 0 to 2 Physical Address 0x4806 280A 0x100 i Instance USBTLL Description Controls UTMI OTG functions of the PHY Read Write address Type RW 7 6 5 4 3 2 1 0 RESERVED DRVVBUS CHRGVBUS DPPULLDOWN IDPULLUP DMPULLDOWN DISCHRGVBUS Bits Field Name Description Type Reset 7 6 RESERVED Reserved R 0x0 5 DRVVBUS Drive 5 V on VBUS RW 0x0 0x0 No action 0x1 Drive VBUS 4 CHRGVBUS Charge VBUS through a ...

Page 3304: ...ESERVED Reserved R 0x0 5 DRVVBUS Drive 5 V on VBUS RW 0x0 Write 0x0 No effect on bit value Write 0x1 Set the bit to 1 4 CHRGVBUS Charge VBUS through a resistor for VBUS pulsing SRP RW 0x0 Write 0x0 No effect on bit value 0x1 Set the bit to 1 3 DISCHRGVBUS Discharge VBUS through a resistor until the session end RW 0x0 VBUS state is reached Write 0x0 No effect on bit value Write 0x1 Set the bit to 1...

Page 3305: ... SRP RW 0x0 Write 0x0 No effect on bit value Write 0x1 Clear the bit to 0 3 DISCHRGVBUS Discharge VBUS through a resistor until the session end RW 0x0 VBUS state is reached Write 0x0 No effect on bit value Write 0x1 Clear the bit to 0 2 DMPULLDOWN Enables the 15k pull down resistor on D RW 0x0 Write 0x0 No effect on bit value Write 0x1 Clear the bit to 0 1 DPPULLDOWN Enables the 15k pull down resi...

Page 3306: ...x1 changes from low to high SessValid is the same as UTMI AValid 1 VBUSVALID_RISE Generate an interrupt event notification when VbusValid RW 0x1 changes from low to high 0 HOSTDISCONNECT_RISE Generate an interrupt event notification when RW 0x1 Hostdisconnect changes from low to high Applicable only in host mode DpPulldown and DmPulldown both set to 1b Table 22 101 Register Call Summary for Regist...

Page 3307: ...ication when VbusValid RW 0x0 changes from low to high Write 0x0 No effect on bit value Write 0x1 Set the bit to 1 0 HOSTDISCONNECT_RISE Generate an interrupt event notification when RW 0x0 Hostdisconnect changes from low to high Applicable only in host mode DpPulldown and DmPulldown both set to 1b Write 0x0 No effect on bit value Write 0x1 Set the bit to 1 Table 22 103 Register Call Summary for R...

Page 3308: ...o 0 1 VBUSVALID_RISE Generate an interrupt event notification when VbusValid RW 0x0 changes from low to high Write 0x0 No effect on bit value Write 0x1 Clear the bit to 0 0 HOSTDISCONNECT_RISE Generate an interrupt event notification when RW 0x0 Hostdisconnect changes from low to high Applicable only in host mode DpPulldown and DmPulldown both set to 1b Write 0x0 No effect on bit value Write 0x1 C...

Page 3309: ...errupt event notification when RW 0x1 Hostdisconnect changes from high to low Applicable only in host mode DpPulldown and DmPulldown both set to 1b Table 22 107 Register Call Summary for Register ULPI_USB_INT_EN_FALL_i High Speed USB Host Subsystem USBTLL Module Functionality 0 High Speed USB Host Subsystem Register Summary 1 Table 22 108 ULPI_USB_INT_EN_FALL_SET_i Address Offset 0x0000 0011 0x100...

Page 3310: ...down and DmPulldown both set to 1b Write 0x0 No effect on bit value Write 0x1 Set the bit to 1 Table 22 109 Register Call Summary for Register ULPI_USB_INT_EN_FALL_SET_i High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 110 ULPI_USB_INT_EN_FALL_CLR_i Address Offset 0x0000 0012 0x100 i Index i 0 to 2 Physical Address 0x4806 2812 0x100 i Instance USBTLL Descript...

Page 3311: ...tem High Speed USB Host Subsystem Register Summary 0 Table 22 112 ULPI_USB_INT_STATUS_i Address Offset 0x0000 0013 0x100 i Index i 0 to 2 Physical Address 0x4806 2813 0x100 i Instance USBTLL Description Indicates the current value of the interrupt source signal Type R 7 6 5 4 3 2 1 0 RESERVED IDGND SESSEND SESSVALID VBUSVALID HOSTDISCONNECT Bits Field Name Description Type Reset 7 5 RESERVED Reser...

Page 3312: ...CH VBUSVALID_LATCH HOSTDISCONNECT_LATCH Bits Field Name Description Type Reset 7 5 RESERVED Reserved R 0x0 4 IDGND_LATCH Set to 1 by the PHY when an unmasked event occurs on R 0x0 IdGnd Cleared when this register is read 3 SESSEND_LATCH Set to 1 by the PHY when an unmasked event occurs on R 0x0 SessEnd Cleared when this register is read 2 SESSVALID_LATCH Set to 1 by the PHY when an unmasked event ...

Page 3313: ... SE1 LS FS Invalid HS Chirp Table 22 117 Register Call Summary for Register ULPI_DEBUG_i High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 118 ULPI_SCRATCH_REGISTER_i Address Offset 0x0000 0016 0x100 i Index i 0 to 2 Physical Address 0x4806 2816 0x100 i Instance USBTLL Description Register byte for register access testing purposes Value has no functional effec...

Page 3314: ...ess 0x4806 2818 0x100 i Instance USBTLL Description Register byte for register access testing purposes Value has no functional effect on PHY Read clear address write 1 to a bit to clear it to 0 writing 0 has no effect on bit value See fields description at the read write address of the same register Type RW 7 6 5 4 3 2 1 0 SCRATCH Bits Field Name Description Type Reset 7 0 SCRATCH Scratch data RW ...

Page 3315: ...ertion upon vcontrol_status bit change RW 0x0 2 VC2_EN Enable alt_int assertion upon vcontrol_status bit change RW 0x0 1 VC1_EN Enable alt_int assertion upon vcontrol_status bit change RW 0x0 0 VC0_EN Enable alt_int assertion upon vcontrol_status bit change RW 0x0 Table 22 127 Register Call Summary for Register ULPI_UTMI_VCONTROL_EN_i High Speed USB Host Subsystem High Speed USB Host Subsystem Reg...

Page 3316: ...ILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes Read clear address write 1 to a bit to clear it to 0 writing 0 has no effect on bit value See fields description at the read write address of the same register Type RW 7 6 5 4 3 2 1 0 VC7_EN VC6_EN VC5_EN VC4_EN VC3_EN VC2_EN VC1_EN VC0_EN Bits Field Name Description Type Reset 7 VC7_EN Enable alt_i...

Page 3317: ...TROL_STATUS_i High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 134 ULPI_UTMI_VCONTROL_LATCH_i Address Offset 0x0000 0034 0x100 i Index i 0 to 2 Physical Address 0x4806 2834 0x100 i Instance USBTLL Description Part of non standard UTMI to ULPI mailbox system implemented if HDL generic VCS_MAILBOX bit is 1 Set by unmasked changes on the corresponding vcontrol_s...

Page 3318: ... Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 138 ULPI_UTMI_VSTATUS_SET_i Address Offset 0x0000 0036 0x100 i Index i 0 to 2 Physical Address 0x4806 2836 0x100 i Instance USBTLL Description Part of non standard UTMI to ULPI mailbox system implemented if HDL generic VCS_MAILBOX bit is 1 UTMI standard Vstatus vector byte is sent by the PHY emulated here by the TL...

Page 3319: ...PI_USB_INT_LATCH_NOCLR_i Address Offset 0x0000 0038 0x100 i Index i 0 to 2 Physical Address 0x4806 2838 0x100 i Instance USBTLL Description Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt Debug non standard address to the standard register Register is not cleared on read See fields description at the clear on read address of the same register Type UNDEFINED_...

Page 3320: ...Functionality 0 High Speed USB Host Subsystem Register Summary 1 Table 22 146 ULPI_VENDOR_INT_EN_SET_i Address Offset 0x0000 003C 0x100 i Index i 0 to 2 Physical Address 0x4806 283C 0x100 i Instance USBTLL Description Vendor specific interrupt enable bit mask for miscellaneous ULPI alt_int events Read set address write 1 to a bit to set it to 1 writing 0 has no effect on bit value See fields descr...

Page 3321: ...R_INT_EN_CLR_i High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 150 ULPI_VENDOR_INT_STATUS_i Address Offset 0x0000 003E 0x100 i Index i 0 to 2 Physical Address 0x4806 283E 0x100 i Instance USBTLL Description Vendor specific interrupt sources for miscellaneous ULPI alt_int events Type R 7 6 5 4 3 2 1 0 RESERVED UTMI_SUSPENDM Bits Field Name Description Type Re...

Page 3322: ...ister Call Summary for Register ULPI_VENDOR_INT_LATCH_i High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 22 2 6 4 2 UHH_config Registers Table 22 154 UHH_REVISION Address Offset 0x0000 0000 Physical Address 0x4806 4000 Instance UHH_config Description Standard revision number BCD encoded Revision maj min Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1...

Page 3323: ...wer bit Interface clock Upper bits if any Functional clocks 1 Clock is kept on during idle 0 Clock is switched off during idle 7 5 RESERVED Reserved R 0x0 4 3 SIDLEMODE Slave interface power management control Idle Req ack RW 0x0 control 0x0 Force Idle mode Sidleack asserted after Idlereq assertion 0x1 No idle mode Sidleack never asserted 0x2 Smart idle mode Sidleack asserted upon Idlereq assertio...

Page 3324: ... High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 160 UHH_HOSTCONFIG Address Offset 0x0000 0040 Physical Address 0x4806 4040 Instance UHH_config Description Static configuration of the OTG controller host Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED ENA_INCR8 ENA_INCR4 ENA_INCR16 P3_ULPI_BYPAS...

Page 3325: ...e of INCR8 type bursts in AHB sense RW 0x0 0x0 Disable burst type 0x1 Enable burst type 2 ENA_INCR4 Control the use of INCR4 type bursts in AHB sense RW 0x0 0x0 Disable burst type 0x1 Enable burst type 1 AUTOPPD_ON_OVERCUR_EN Configure reaction upon port overcurrent condition RW 0x0 0x0 Port remains on upon overcurrent 0x1 Port is powered down automatically upon overcurrent Note The bit must not b...

Page 3326: ...eriph connected 16 OHCI_GLOBALSUSPEND OHCI global suspend status asserted 5ms after the R 0x0 suspend order 0x0 Host is not suspended 0x1 Host is suspended 15 8 RESERVED Reserved R 0x00 7 OCHI_CNTSEL Selection of a shorter 1 ms counter in OHCI host to RW 0x0 speed up long USB phases like reset resume etc Used only for simulation 0x0 Functional mode 1ms 12 000 x 12 MHz cycles 0x1 Simulation mode 1m...

Page 3327: ...66 HCCONTROL Address Offset 0x0000 0004 Physical Address 0x4806 4404 Instance OHCI Description HC Operating Mode Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IR HCFS IE CBSR BLE PLE CLE RWE RWC Bits Field Name Description Type Reset 31 11 RESERVED Reserved R 0x000000 10 RWE Remote wake up enable RW 0 This bit is used to enable or d...

Page 3328: ...between RW 0x0 control and bulk EDs processed in a frame 0x0 One control ED per bulk ED 0x1 Two control ED per bulk ED 0x2 Three control ED per bulk ED 0x3 Four control ED per bulk ED Table 22 167 Register Call Summary for Register HCCONTROL High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 168 HCCOMMANDSTATUS Address Offset 0x0000 0008 Physical Address 0x4806...

Page 3329: ... High Speed USB Host Subsystem Register Summary 0 High Speed USB Host Subsystem Register Description 1 Table 22 170 HCINTERRUPTSTATUS Address Offset 0x0000 000C Physical Address 0x4806 440C Instance OHCI Description HC Interrupt Status Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SF UE RD SO OC FNO WDH RHSC RESERVED Bits Field Name Descript...

Page 3330: ...Table 22 172 HCINTERRUPTENABLE Address Offset 0x0000 0010 Physical Address 0x4806 4410 Instance OHCI Description HC Interrupt Enable Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SF UE RD SO OC MIE FNO WDH RHSC Bits Field Name Description Type Reset 31 MIE Master interrupt enable RW 0 When 0x1 Allows other enabled OHCI interrupt sources to p...

Page 3331: ...x1 Allows WDH interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0 WDH interrupts do not propagate Write 0x0 No effect Write 0x1 Sets this bit 0 SO Scheduling overrun RW 0 When 0x1 and MIE is 0x1 Allows SO interrupts to propagate to the device interrupt controller When 0x0 or MIE is 0x0 SO interrupts do not propagate Write 0x0 No effect Write 0x1 Sets this bit Table 22...

Page 3332: ...lways reads 0x0 Write 0x0 No effect Write 0x1 Clears the HCINTERRUPTENABLE WDH bit 0 SO Scheduling overrun RW 0 Always reads 0x0 Write 0x0 No effect Write 0x1 Clears the HCINTERRUPTENABLE SO bit Table 22 175 Register Call Summary for Register HCINTERRUPTDISABLE High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 176 HCHCCA Address Offset 0x0000 0018 Physical Add...

Page 3333: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHED RESERVED Bits Field Name Description Type Reset 31 4 CHED Physical address of head ED on the control ED list RW 0x0000000 3 0 RESERVED Reserved R 0x0 Table 22 181 Register Call Summary for Register HCCONTROLHEADED High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 182 HCCO...

Page 3334: ...le 22 186 HCBULKCURRENTED Address Offset 0x0000 002C Physical Address 0x4806 442C Instance OHCI Description HC Current Bulk Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCED RESERVED Bits Field Name Description Type Reset 31 4 BCED Physical address of current ED on the bulk ED list RW 0x0000000 3 0 RESERVED Reserved R 0x0 Table 22 187 Regis...

Page 3335: ...gest data packet size for full speed packets bit times RW 0x0000 This field specifies a value which is loaded into the largest data packet counter at the beginning of each frame 15 14 RESERVED Reserved R 0x0 13 0 FI Frame interval Number of 12 MHz clocks in the USB RW 0x2EDF frame The nominal value is set to 11 999 to give a 1 ms frame Table 22 191 Register Call Summary for Register HCFMINTERVAL H...

Page 3336: ...fset 0x0000 003C Physical Address 0x4806 443C Instance OHCI Description HC Frame Number Register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED FN Bits Field Name Description Type Reset 31 16 RESERVED Reserved R 0x0000 15 0 FN Frame Number R 0x0000 This is incremented when USBHOST HCFMREMAINING is reloaded It is rolled over to 0x0000 after 0xF...

Page 3337: ...ter HCLSTHRESHOLD High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 Table 22 200 HCRHDESCRIPTORA Address Offset 0x0000 0048 Physical Address 0x4806 4448 Instance OHCI Description HC Root Hub A Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POTPG RESERVED NDP DT NPS PSM NOCP OCPM Bits Field Name Description Type Re...

Page 3338: ...dress Offset 0x0000 004C Physical Address 0x4806 444C Instance OHCI Description HC Root Hub B Register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PPCM DR Bits Field Name Description Type Reset 31 16 PPCM Port power control mask Each bit defines whether a RW 0x0000 corresponding downstream port has port power controlled by the global power control ...

Page 3339: ...r switching mode is 1 15 DRWE Device remote wake up enable Enables a connect status RW 0 change event as a resume event causing a USB suspend to USB resume state transition and sets the resume detected interrupt status bit Read 0x1 Connect status change is a remote wake up event Read 0x0 Connect status change is not a remote wake up event Write 0x0 No effect Write 0x1 Sets the device remote wake u...

Page 3340: ...rent connect status is 0 when a set port reset set port enable or set port suspend write occurs this bit is set Write 0x0 No effect Write 0x1 Clears this bit Note If the DR bit HCRHDESCRIPTORB 1 is set this bit is set only after a root hub reset to inform the system that the device is attached 15 10 RESERVED Reserved R 0x00 9 LSDA_CPP Port 1 low speed device attached clear port power This RW 0 bit...

Page 3341: ...it When port 1 current status is 0 has no effect 0 CCS_CPE Port 1 current connection status clear port enable RW 0 Read 0x0 No USB device is attached to port 1 Read 0x1 Port 1 currently has a USB device attached Write 0x0 No effect Write 0x1 Clears the port 1 port enable bit Note This bit is set to 1 if the DR bit HCRHDESCRIPTORB 1 is set to indicate a non removable device on port 1 Table 22 207 R...

Page 3342: ...erved R 0x0 4 PRS_SPR Port 2 port reset status set port reset RW 0 Read 0x0 USB reset is not being sent to port 2 Read 0x1 Port 2 is signaling the USB reset Write 0x0 No effect Write 0x1 Sets the port 2 port reset status bit and causes the USB host controller to begin signaling USB reset to port 2 3 RESERVED Reserved RW 0 2 PSS_SPS Port 2 port suspend status set port suspend This bit is RW 0 clear...

Page 3343: ...ite 0x0 No effect Write 0x1 Clears this bit 19 RESERVED Reserved RW 0 18 PSSC Port 3 suspend status change This bit is set when the RW 0 Port 3 port suspend status has changed Write 0x0 No effect Write 0x1 Clears this bit 17 PESC Port 3 enable status change This bit is set when the Port RW 0 3 port enable status has changed Write 0x0 No effect Write 0x1 Clears this bit 16 CSC Port 3 connect status...

Page 3344: ... 0 sets instead connect status change to inform the USB host controller driver of an attempt to suspend a disconnected port 1 PES_SPE Port 3 enable status set port enable This bit is RW 0 automatically set at completion of port 3 USB reset if it was not already set before the USB reset completed and is automatically set at the end of a USB suspend if the port was not enabled when the USB resume co...

Page 3345: ...nstance EHCI Description Host Controller Structural Parameters Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED N_CC N_PCC N_PORTS PPC PRR RESERVED RESERVED P_INDICATOR Bits Field Name Description Type Reset 31 20 RESERVED Reserved R 0x000 19 17 RESERVED Reserved R 0x0 16 P_INDICATOR Port indicator support indication R 0 This bit indicates wheth...

Page 3346: ...field indicates whether the host controller implementation includes port power control 0x0 The ports do not have port power switches 0x1 The ports have port power switches 3 0 N_PORTS Number of downstream ports R 0x3 This field specifies the number of physical downstream ports implemented on this host controller Table 22 215 Register Call Summary for Register HCSPARAMS High Speed USB Host Subsyste...

Page 3347: ...ry 0 BIT64AC 64 bit addressing capability R 0 This field documents the addressing range capability of this implementation 0x0 Data structures using 32 bit address memory pointers 0x1 Data structures using 64 bit address memory pointers Table 22 217 Register Call Summary for Register HCCPARAMS High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 High Speed USB Host Subsyst...

Page 3348: ...itialize the host controller Read 0x1 Light host controller reset is still ongoing 6 IAAD Interrupt on Async Advance Doorbell RW 0 This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule Write 0x1 Ring the doorbell Software should not write a 1 to this bit when the asynchronous schedule is disabled Doing so may yi...

Page 3349: ... USB Host Subsystem Register Description 1 2 3 4 5 Table 22 220 USBSTS Address Offset 0x0000 0014 Physical Address 0x4806 4814 Instance EHCI Description USB status Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED IAA FLR ASS PSS HSE REC PCD HCH USBI USBEI Bits Field Name Description Type Reset 31 16 RESERVED Reserved R 0x0000 15 ASS As...

Page 3350: ... PORTSC_i 6 FPR bit transition from a 0 to a 1 This bit is also set as a result of the USBHOST PORTSC_i 1 CSC bit being set to 1 after system software has relinquished ownership of a connected port by writing a 1 to a USBHOST PORTSC_i 13 PO bit 1 USBEI USB Error Interrupt RW 0 The host controller sets this bit to 1 when completion of a USB transaction results in an error condition 0 USBI USB Inter...

Page 3351: ...host controller issues an interrupt at the next interrupt threshold The interrupt is acknowledged by software clearing the USBHOST USBSTS 1 USBEI bit 0 USBIE USB Interrupt Enable RW 0 0x1 When the USBHOST USBSTS 0 USBI bit is 1 the host controller issues an interrupt at the next interrupt threshold The interrupt is acknowledged by software clearing the USBHOST USBSTS 0 USBI bit Table 22 223 Regist...

Page 3352: ...8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAL RESERVED Bits Field Name Description Type Reset 31 12 BAL Base address low RW 0x00000 These bits correspond to memory address signals 11 0 RESERVED Reserved R 0x000 Table 22 229 Register Call Summary for Register PERIODICLISTBASE High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 High Speed USB Host Subsystem Register De...

Page 3353: ...x1 Port routing control logic default routes all ports to this host controller Table 22 233 Register Call Summary for Register CONFIGFLAG High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 High Speed USB Host Subsystem Register Description 1 2 Table 22 234 PORTSC_i Address Offset 0x0000 0054 0x04 i Index i 0 to 2 Physical Address 0x4806 4854 0x04 i Instance EHCI Descrip...

Page 3354: ...o power 0x1 N A Host controller has port power control switches This bit represents the current setting of the switch 0 Off 1 On When an overcurrent condition is detected on a powered port and the USBHOST HCSPARAMS 4 PPC bit is a 1 the PP bit in each affected port may be transitioned by the host controller from 1 to 0 11 10 LS Line Status R 0x0 These bits reflect the current logical levels of the ...

Page 3355: ...0x0 Disable 0x1 Enable 1 CSC Connect Status Change RW 0 Indicates a change has occurred in the port CCS bit This field is 0 if the PP bit is 0 Read 0x0 No change Read 0x1 Change in current connect status Write 0x1 Clears this bit to 0 0 CCS Current Connect Status R 0 This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set Thi...

Page 3356: ...RW 0x0020 words 15 0 IN_THRESHOLD Programmable input packet buffer threshold in 32 bit RW 0x0020 words Table 22 239 Register Call Summary for Register INSNREG01 High Speed USB Host Subsystem High Speed USB Host Subsystem Register Summary 0 High Speed USB Host Subsystem Register Description 1 Table 22 240 INSNREG02 Address Offset 0x0000 0098 Physical Address 0x4806 4898 Instance EHCI Description Im...

Page 3357: ... 22 244 INSNREG04 Address Offset 0x0000 00A0 Physical Address 0x4806 48A0 Instance EHCI Description Implementation specific register 4 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED NAK_FIX_DIS HCSPARAMS_WRE HCCPARAMS_WRE SHORT_PORT_ENUM Bits Field Name Description Type Reset 31 5 RESERVED Reserved R 0x0000000 4 NAK_FIX_DIS Disable N...

Page 3358: ...ce selected 0x2 Port 2 vendor interface selected 0x3 Port 3 vendor interface selected 12 VCONTROLLOADM UTMI VcontrolLoadM output active low RW 0 0x0 Load Vcontrol value into PHY 0x1 No Action 11 8 VCONTROL UTMI Vcontrol output to be loaded into the PHY RW 0x0 7 0 VSTATUS UTMI Vstatus input image from PHY R 0x00 Table 22 247 Register Call Summary for Register INSNREG05_UTMI High Speed USB Host Subs...

Page 3359: ...is Write 0x3 Register access is Read 21 16 REGADD ULPI direct register address for any value different than RW 0x00 0x2F 0x2F Triggers an extended address 15 8 EXTREGADD Address for extended register accesses Don t care for RW 0x00 direct accesses 7 0 WRDATA Read Write data of register access RW 0x00 Table 22 249 Register Call Summary for Register INSNREG05_ULPI High Speed USB Host Subsystem High ...

Page 3361: ...Controller This chapter presents an overview of the Memory Stick PRO host controller in the device Topic Page 23 1 Memory Stick PRO Host Controller Overview 3362 3361 SWPU177N December 2009 Revised November 2010 Memory Stick PRO Host Controller Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3362: ...e interconnect Figure 23 1 shows an overview of the Memory Stick PRO host controller Figure 23 1 Memory Stick PRO Host Controller Overview 23 1 1 Main Features The Memory Stick PRO host controller includes the following main features Supports Memory Stick v1 x and Memory Stick PRO Data transmit receive internal first in first out FIFO 64 bits x 4 Cyclic redundancy check CRC circuit Memory Stick se...

Page 3363: ...Topic Page 24 1 MMC SD SDIO Overview 3364 24 2 MMC SD SDIO Environment 3367 24 3 MMC SD SDIO Integration 3375 24 4 MMC SD SDIO Functional Description 3383 24 5 MMC SD SDIO Basic Programming Model 3396 24 6 MMC SD SDIO Use Cases and Tips 3412 24 7 MMC SD SDIO Register Manual 3423 3363 SWPU177N December 2009 Revised November 2010 MMC SD SDIO Card Interface Copyright 2009 2010 Texas Instruments Incor...

Page 3364: ...ion interface manages transaction semantics The MMC SD SDIO host controller deals with MMC SD SDIO protocol at transmission level data packing adding cyclic redundancy checks CRC start end bit and checking for syntactical correctness The application interface can send every MMC SD SDIO command and either poll for the status of the adapter or wait for an interrupt request which is sent back in case...

Page 3365: ...ce with SDIO command response sets and interrupt read wait mode as defined in the SDIO Card Specification Part E1 v1 10 Compliance with sets as defined in the SD Card Specification Part A2 SD Host Controller Standard Specification v1 00 Full compliance with MMC bus testing procedure as defined in the Multimedia Card System Specification v4 2 Full compliance with CE ATA command response sets as def...

Page 3366: ... can be written while the other part is read For 512 to 1024 byte transfers the entire buffer is dedicated to the transfer read only or write only The differences between the MMC SD SDIO host controllers and a Standard SD host controller are defined by the SD Card Specification Part A2 SD Host Controller Standard Specification v1 00 as follows The MMC SD SDIO host controllers support MMC cards The...

Page 3367: ...command It supports 1 bit 4 bit and 8 bit data transfer modes Using an external transceiver device precludes 8 bit transfer mode The third controller MMC SD SDIO3 allows connecting MMC SD SDIO cards only 1 8V cards or an external device that uses the MMC SD SDIO interface Wireless USB card for example This interface is used without external transceiver It supports 1 bit 4 bit and 8 bit data transf...

Page 3368: ...ithout External Transceiver Figure 24 5 shows the MMC SD SDIOi host controller interface signals instance 1 2 or 3 Figure 24 5 MMC SD SDIOi Interface Signals Table 24 1 describes the MMC SD SDIOi inputs outputs Table 24 1 MMC SD SDIOi I O Description Signal Name I O 1 Description Reset Value mmci_clk O External clock for MMC SD SDIO 0 card 2 mmci_cmd I O Command signal 0 mmci_dat 3 0 I O Data sign...

Page 3369: ...ignal when an external 0 transceiver is used high when transmit low when receive mmc2_dir_dat3 O Direction control for mmc2_dat 7 4 signal when an external 0 transceiver is used high when transmit low when receive Unusable on the device because mmci_dat 7 4 are muxed with other direction control signals See Chapter 13 System Control Module for further details on the pin multiplexing 24 2 3 3 MMC S...

Page 3370: ...on There are specific commands for each type of operation sequential or block oriented See the Multimedia Card System Specification v4 2 the SD Memory Card Specifications v2 0 and the SDIO Card Specification Part E1 August 2004 for details about commands and programming sequences supported by the MMC SD and SDIO cards Figure 24 7 and Figure 24 8 show how sequential operations are defined Sequentia...

Page 3371: ...9 Multiple Block Read Operation Figure 24 10 Multiple Block Write Operation with Card Busy Signal NOTE 1 The card busy signal is not always generated by the card the previous examples show a particular case 2 It is software responsibility to do a software reset set MMCi MMCHS_SYSCTL 26 SRD bit to 0x1 after data timeout to ensure mmci_clk is stopped 3 For multiblock transfer and especially for MMC ...

Page 3372: ... second bit is a transmitter bit 0 for a card response The content is different for each type of response R1 R2 R3 R4 and R5 R6 for SDIO and the content is protected by 7 bit CRC checksum see Figure 24 12 and Figure 24 13 Depending on the type of commands sent to the card the MMCHS_CMD register must be configured differently to avoid false CRC or index errors to be flagged on command response see ...

Page 3373: ...Response Type MMCi MMCHS_CMD 17 16 MMCi MMCHS_CMD 20 MMCi MMCHS_CMD 19 RSP_TYPE CICE CCCE 00 0 0 No Response 01 0 1 R2 10 0 0 R3 R4 for SD cards 10 1 1 R1 R6 R5 11 1 1 R1b R5b 1 The MMC SD SDIOi host controller assumes that both clocks may be switched off whatever the value set in the MMCi MMCHS_SYSCONFIG 9 8 CLOCKACTIVITY bit Coding Scheme for Data Token Data tokens always start with 0 and end wi...

Page 3374: ...5 1 0 mmci_dat7 b7 b7 b7 b7 CRC 1 0 b6 b6 b6 b6 CRC mmci_dat6 1 0 b5 b5 b5 b5 CRC mmci_dat5 1 0 b4 b4 b4 b4 CRC mmci_dat4 Public Version MMC SD SDIO Environment www ti com Figure 24 16 Data Token Format for 8 Bit Transfers 3374 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3375: ...MMC SD SDIO Integration 24 3 MMC SD SDIO Integration Figure 24 17 shows the internal connections between the three instances of the MMC SD SDIO host controller and the other modules Figure 24 17 MMC SD SDIO1 Integration 24 3 1 Clocking Reset and Power Management Scheme 24 3 1 1 Clocks 24 3 1 1 1 Module Clocks The MMC SD SDIO receives three clocks A fixed functional clock of 96 MHz the MMCi_FCLK in...

Page 3376: ...ost controller complies with the PRCM module handshaking protocol Idle request from the system power manager Idle acknowledgment from the MMC SD SDIO host controller Wake up request from the MMC SD SDIO host controller The idle acknowledgment varies according to the MMCi MMCHS_SYSCONFIG 4 3 SIDLEMODE bit field 0x0 Force idle mode The MMC SD SDIO host controller acknowledges the system power manage...

Page 3377: ...ITY bit Transition From Smart Idle Mode to Normal Mode The MMC SD SDIO host controller detects the end of the idle period when the PRCM deasserts the idle request For the wake up event there is a corresponding interrupt status in the MMCi MMCHS_STAT register The MMC SD SDIOi host controller operates the conversion between wake up and interrupt or DMA request upon exit from smart idle mode if the a...

Page 3378: ...it can be monitored by the software to check if the module is ready to use after a hardware reset NOTE Functional clock MMCi_FCLK interface clock MMCi_ICLK and debounce clock MMCi_32K must be provided to the module to allow the RESETDONE status bit to be set This hardware reset signal has a global reset action on the module All configuration registers and all state machines are reset in all clock ...

Page 3379: ...There is enough space in the buffer of the MMC SD SDIOi host controller to write an entire block BLEN writes DMA request lines are connected on the system DMA sDMA inputs S_DMA_60 MMC1_DMA_TX S_DMA_61 MMC1_DMA_RX S_DMA_46 MMC2_DMA_TX S_DMA_47 MMC2_DMA_RX S_DMA_76 MMC3_DMA_TX S_DMA_77 MMC3_DMA_RX 24 3 2 1 1 DMA Receive Mode In a DMA block read operation single or multiple the request signal MMCi_DM...

Page 3380: ...tive level when a complete block is to be written to the buffer The block size transfer is specified in the MMCi MMCHS_BLK 10 0 BLEN field The MMCi_DMA_TX signal is deasserted to its inactive level when the sDMA has written one single word to the buffer Only one request is sent per block the DMA controller can make a 1 shot write access or multiple write DMA bursts in which case the DMA controller...

Page 3381: ...egister on an event by event basis The interrupt signal enable bits of the MMCi MMCHS_ISE register enable disable the transmission of an interrupt request on the interrupt line MMCi_IRQ from the MMC SD SDIOi host controller to the MPU subsystem interrupt controller on an event by event basis If an interrupt status is disabled in the MMCi MMCHS_IE register then the corresponding interrupt request i...

Page 3382: ...red Write 1 into the corresponding bit of the MMCi MMCHS_STAT register to clear the interrupt status and release the interrupt line if a read is done after this write this would return 0 NOTE In the MMCi MMCHS_STAT register Card Interrupt CIRQ and Error Interrupt ERRI bits cannot be cleared The MMCi MMCHS_STAT 8 CIRQ status bit must be masked by disabling the MMCi MMCHS_IE 8 CIRQ_ENABLE bit set to...

Page 3383: ... Any two domains are considered asynchronous to each other and exchanges between the two domains are synchronized through a synchronization stage and an asynchronous buffer Data are transferred from one domain to other through the buffer 2 512 RAM Figure 24 20 shows a block diagram of the MMC SD SDIO host controller 3383 SWPU177N December 2009 Revised November 2010 MMC SD SDIO Card Interface Copyr...

Page 3384: ...ngle transfer Status registers Bus status Transfer status Buffer status Interrupt status Error status CMD12 status Status management Buffer status CMD12 status Error status Bus status Status management Transfer status Write stream Read stream Read block Timer CRC Data process Write block Reset control MMCHS_SYSCTL Power management Wake up event control Auto idle control Clocks control MMCHS_HCTL M...

Page 3385: ... respecting the protocol of the connected card Writes and reads to the card must respect the appropriate protocol of that card 24 4 3 Buffer Management 24 4 3 1 Data Buffer The MMC SD SDIOi host controller uses a data buffer divided into two 512 byte portions that are 32 bits wide by 128 words deep This buffer transfers data from one data bus Interconnect to another data bus SD SDIO or MMC card bu...

Page 3386: ...is less than or equal to 512 bytes meaning the value written in BLEN is less than or equal to 0x200 two data transfers can occur from one data bus to the other data bus and vice versa at the same time The MMC SD SDIOi host controller uses the two portions of the data buffer in a ping pong manner so that storing and reading of the first and second portions of the data buffer are automatically inter...

Page 3387: ... B 512 bytes 32 bits 128 words 128 words Write to MMCHS_DATA Write to card are two different transfers that occur at the same time and Write to the card MMCHS_CMD DDIR 0 mmchs 047 L4 interconnect bus L4 interconnect bus Card bus Card bus Public Version www ti com MMC SD SDIO Functional Description Figure 24 21 Buffer Management for a Write 3387 SWPU177N December 2009 Revised November 2010 MMC SD S...

Page 3388: ...BLEN is 0x201 or larger only one data transfer can occur from one data bus to the other data bus at a time The MMC SD SDIOi host controller uses the entire data buffer as a single 1024 byte portion In this mode a bad access MMCi MMCHS_STAT 29 BADA is signaled when two data transfers occur from one data bus to the other data bus and vice versa at the same time 24 4 3 1 1 Data Buffer Status The data...

Page 3389: ...MMCHS_RSP32 31 0 MMCHS_RSP10 31 0 1 RESP refers to the command response format described in the specifications mentioned above When the host controller modifies part of the MMCHS_RSPxx registers it preserves the unmodified bits The host controller stores the Auto CMD12 response in the MMCHS_RSP76 31 0 register because the Host Controller may have a multiple block data DAT line transfer executing c...

Page 3390: ...asserted in the following conditions busy timeout for R1b R5b response type busy timeout after write CRC status write CRC status timeout read data timeout boot acknowledge timeout 24 4 5 1 Busy Timeout For R1b R5b Response Type Figure 24 23 shows DCRC event condition asserted when there is busy timeout for Rb1 R5b response Figure 24 23 Busy Timout for R1b R5b Response Type t1 Data timeout counter ...

Page 3391: ...fter Write CRC Status t1 Data timeout counter is loaded and starts after CRC Status t2 Data timeout counter stops and if it is 0 MMCHS_STAT 21 DCRC is generated 24 4 5 3 Write CRC Status Timeout Figure 24 25 shows DCRC event condition asserted when there is write CRC status timeout Figure 24 25 Write CRC Status Timeout t1 Data timeout counter is loaded and starts after Data block CRC t2 Data timeo...

Page 3392: ...ta block CRC transmission t4 Data timeout counter stops and if it is 0 MMCHS_STAT 21 DCRC is generated 24 4 5 5 Boot Acknowledge Timeout Figure 24 28 shows DCRC event condition asserted when there is boot acknoledge timeout and CMD0 is used Figure 24 27 Boot Acknowledge Timeout When Using CMD0 t1 Data timeout counter is loaded and starts after CMD0 t2 Data timeout counter stops and if it is 0 MMCH...

Page 3393: ...ata CRC transmission t6 Data timeout counter stops and if it is 0 MMCHS_STAT DCRC is generated 24 4 6 Autocommand 12 Timings With the UHS definition of SD cards with higher frequency for MMC clock up to 208 SD standard imposes a specific timing for Auto CMD12 end bit arrival 24 4 6 1 Autocommand 12 Timings During Write Transfer A margin named Ncrc in range of 2 to 8 cycles has been defined for SDR...

Page 3394: ...te length NOTE Since the MMC SD SDIOi controller manages transfers based on a block granularity the buffer will accept a block only if there is enough space to completely store it Consequently if a block is pending in the buffer no command will be sent to the card because the card clock will be shut off by the controller The MMC SD SDIOi controller includes two features which makes a transfer stop...

Page 3395: ...MMCHS_CMD 2 ACEN set to 1 is launched host system is no longer allowed to emit a new command in parallel of data transfer unless it is a command completion disable The settings to emit a command completion disable token follow MMCHS_CON 12 CEATA is set to 1 MMCHS_CON 2 HR set to 1 Clear the MMCHS_ARG register Write into MMCHS_CMD register with value 0x00000000 When a command completion disable tok...

Page 3396: ...lization Flow Figure 24 31 shows the general boot process Figure 24 31 MMC SD SDIO Controller Meta Initialization Steps 24 5 1 1 Enable Interface and Functional clock for MMC Controller Prior to any MMCHS register access one must enable MMCHS interface clock and functional clock in PRCM module registers PRCM CM_ICLKEN1_CORE and PRCM CM_FCLKEN1_CORE See Chapter 3 Power Reset and Clock Management 24...

Page 3397: ...low 24 5 1 3 Set MMCHS Default Capabilities Software must read capabilities in boot ROM for instance and is allowed to set write MMCi MMCHS_CAPA 26 24 and MMCi MMCHS_CUR_CAPA 23 0 registers before the MMC SD SDIO host driver is started 24 5 1 4 Wake Up Configuration Figure 24 33 details MMCHS controller wake up configuration 3397 SWPU177N December 2009 Revised November 2010 MMC SD SDIO Card Interf...

Page 3398: ...bit to enable the card interrupt for SDIO card only mmchs 027 Public Version MMC SD SDIO Basic Programming Model www ti com Figure 24 33 MMC SD SDIO Controller Wake Up Configuration 24 5 1 5 MMC Host and Bus Configuration Figure 24 34 details MMC bus configuration process 3398 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated...

Page 3399: ...eld Read the MMCi MMCHS_SYSCTL 1 ICS bit ICS 0x1 Yes Clock is stable Write the MMCi MMCHS_SYSCONFIG CLOCKACTIVITY SIDLEMODE and AUTOIDLE fields to configure the behavior of the module in idle mode No Write MMCi MMCHS_CON register to configure specific data and command transfer OD DW8 CEATA mmchs 028 Public Version www ti com MMC SD SDIO Basic Programming Model Figure 24 34 MMC SD SDIO Controller B...

Page 3400: ...ater to identify the card type High Capacity Standard Capacity Set MMCi MMCHS_CON 1 INIT bit to 0x0 to end the initialization sequence Wait 1 ms Clear MMCHS_STAT register write 0xFFFF FFFF Change clock frequency to fit protocol Send a CMD0 command mmchs 030 Public Version MMC SD SDIO Basic Programming Model www ti com The host controller requires transfers to run on a block by block basis rather t...

Page 3401: ...here more than one MMC connected to the same bus and are they all indentified End unknown type of card Yes Send an CMD55 command Yes It is a MMC card Yes The card is not busy No The card is busy Yes It is a MMC card No The card is busy Yes The card is not busy 108 031 With OCR 0 In case of a CMD1 with OCR 0 a second CMD1 must be sent to the card with the negociated voltage Public Version www ti co...

Page 3402: ...MMCi MMCHS_SYSCTL 26 SRD bit to 0x1 and wait until it returns to 0x0 Return End Wait for interrupt interrupt occurs Read the MMCi MMCHS_STAT A Transfer type End A Interrupt handler mmchs 032 Configure and enable the DMA channel see the DMA chapter Yes Disable the DMA channel see the DMA chapter Public Version MMC SD SDIO Basic Programming Model www ti com Figure 24 37 MMC SD SDIO Controller Read W...

Page 3403: ...d CMD12 for MMC and SD cards CMD52 for SDIO cards No or for SDIO Yes The STOP command is automatically sent to the card End Do you want to interrupt the transfer No Send CMD12 for MMC and SD cards CMD52 for SDIO cards Read the MMCi MMCHS_STAT 1 TC bit TC 0x1 No Yes Disable the DMA channel see the DMA chapter End Yes A STOP command can be sent to interrupt the data transfer Disable the DMA channel ...

Page 3404: ...Ci MMCHS_STAT Poll BWR if a write command Poll BRR if a read command No Repeat MMCHS_DATA access BLEN 3 4 times Read the MMCi MMCHS_STAT DEB or DCRC or DTO interrupt occurred No Set MMCi MMCHS_SYSCTL 26 SRD bit to 0x1 and wait until it returns to 0x0 End No event rises in MMCHS_STAT End End Yes There was an error during the data transfer No mmchs 034 Public Version MMC SD SDIO Basic Programming Mo...

Page 3405: ...data transfer Set MMCi MMCHS_SYSCTL 26 SRD bit to 0x1 and wait until it returns to 0x0 End Clear MMCi MMCHS_CON 2 HR bit to 0x0 Transfer type Finite Is it the last block Infinite No This count is done by software Read the MMCi MMCHS_STAT register TC 0x1 Is CCSD activated Yes Yes No Set MMCi MMCHS_SYSCTL 26 SRD bit to 0x1 and wait until it returns to 0x0 DEB or DCRC or DTO 0x1 Yes There was an erro...

Page 3406: ...SBGR and set CR in MMCi MMCHS_HCTL register with the same write action End BS 0x1 Read the BR bit from the card BR 0x1 Yes Yes Send a cancel suspend command Read the BS bit from the card BS 0x1 Yes Save the MMCi MMCHS_BLK register No Clear the MMCi MMCHS_HCTL 16 SBGR bit No No This value will be restored during the resume flow see the corresponding flowchart mmchs 038 Public Version MMC SD SDIO Ba...

Page 3407: ...was read during the suspend flow see the corresponding flowchart mmchs 039 Public Version www ti com MMC SD SDIO Basic Programming Model Figure 24 42 MMC SD SDIO Controller Resume Flow 24 5 2 7 Basic Operations Step Details 24 5 2 7 1 Command Transfer Flow Figure 24 43 describes how to send a command to the card using polling instead of interrupts for event signaling 3407 SWPU177N December 2009 Re...

Page 3408: ...ard specifications Bitfields in MMCHS_CON should be configured according to command features stream or multiblock with or without timeout Write MMCi MMCHS_BLK Write MMCi MMCHS_SYSCTL to set DTO bitfield MMCHS_BLK must be configured with block size and number of blocks if data are present Write MMCi MMCHS_IE and MMCi MMCHS_ISE registers to enable required interrupts In order to use interrupts MMCHS...

Page 3409: ...gured with block size and number of blocks if data are present Write MMCi MMCHS_IE and MMCi MMCHS_ISE registers to enable required interrupts In order to use interrupts MMCHS_ISE must be configured If polling is used configuring MMCHS_IE is enough Start Read the MMCi MMCHS_PSTATE 0 CMDI bit wait for interrupt CC 0x1 Read MMCi MMCHS_RSP register No No response Yes Yes A response is waiting No No CM...

Page 3410: ...ernal bias voltage reference to operate The PBIAS_LITE module supplies this bias voltage depending on the CONTROL CONTROL_PBIAS_LITE register settings See Section 13 4 5 Extended Drain I O Pin and PBIAS Cell for more information about the PBIAS_LITE cell Section 13 5 2 Extended Drain I Os and PBIAS Cell Basic Programming Guide describes the steps involved in transitioning from 1 8 V to 3 0 V and f...

Page 3411: ...6 CLKEXTFREE 0x0 System time out Abort power switching End Yes No System time out No Yes CC 0x1 Yes Remove forcing from ADPIDLE pin Write MMCHS_CON 15 PADEN 0x0 Read MMCHS_PSTAT 23 20 DLEV Read MMCHS_STAT 0 CC Read MMCHS_PSTAT 24 CLEV Read MMCHS_PSTAT 23 20 DLEV Read MMCHS_PSTAT 24 CLEV Public Version www ti com MMC SD SDIO Basic Programming Model Figure 24 46 MMC SD SDIO Power Switching Procedure...

Page 3412: ...e 24 47 Overview For the Camcorder use case the MMCHS controller is configured to operate with the following features High speed mode with a card clock frequency of 48 MHz 4 data lines 1 8 V and 3 0 V voltage capabilities MMC card power supply is not provided by the MMCHS controller itself but rather by the companion device See Chapter 17 to learn how to set these voltage levels Only MMC1 controll...

Page 3413: ...cture of the MMCHS controller Figure 24 48 Environment 24 6 1 2 1 Command and Data Transfer Formats When communicating with a MMC card The MMCHS controller is always the master The communication between the MMCHS controller and the MMC card always starts by sending a command Both command and data transfers are started with a command The data transfer type used by the MMCHS controller is a finite m...

Page 3414: ...block CRC Data block CRC CRC Status XX XXXX mmchs_054 Public Version MMC SD SDIO Use Cases and Tips www ti com Figure 24 49 Command Transfer Figure 24 50 Data Read Transfer Figure 24 51 Data Write Transfer 24 6 1 3 Programming Flow 24 6 1 3 1 Initial Configuration The initialization of the MMCHS controller is done through these steps 1 MMCHS controller interface and functional clocks enabling 2 MM...

Page 3415: ...NE turns 1 Table 24 9 describes the software reset registers Table 24 9 Software Reset Register Description Register Name Register Address Value Value Description MMCHS1 MMCHS_SYSCONFIG 0x4809 C010 0x00000002 Activate software reset MMCHS1 MMCHS_SYSSTATUS 0x4809 C014 0x00000001 Reset is over 24 6 1 3 1 3 MMCHS Controller Voltage Capabilities Initialization MMCHS1 controller s voltage capabilities ...

Page 3416: ...ription MMCHS1 MMCHS_CON 0x4809C02C current_value sets MMCHS1 MMCHS_CON 1 INIT to 1 0x00000002 MMCHS1 MMCHS_CMD 0x4809C10C 0x00000000 sends dummy command 24 6 1 3 1 6 MMCHS Controller Precard Identification Configuration Before card identification starts the MMCHS controller s configuration should change MMC card s clock should now be 400 kHz according to MMC system spec requirements Table 24 13 s...

Page 3417: ...ster Table 24 16 Sending CMD8 Register Name Register Address Value Value Description MMCHS1 MMCHS_CON 0x4809C02C 0x00000001 MMC bus is still in open drain state for broadcast MMCHS1 MMCHS_IE 0x4809C134 0x100f0001 Enables CERR CIE CCRC CC CTO and CEB events to occur MMCHS1 MMCHS_ISE 0x4809C138 0x100f0001 Enables CERR CIE CCRC CC CTO and CEB interrupts to rise MMCHS1 MMCHS_CMD 0x4809C10C 0x81a0000 S...

Page 3418: ...MCHS_RSP54 and MMCHS1 MMCHS_RSP76 registers Table 24 19 Sending CMD2 Register Name Register Address Value Value Description MMCHS1 MMCHS_CON 0x4809C02C 0x00000001 MMC bus is still in open drain state for broadcast MMCHS1 MMCHS_IE 0x4809C134 0x00070001 Enables CERR CIE CCRC CC CTO and CEB events to occur MMCHS1 MMCHS_ISE 0x4809C138 0x00070001 Enables CERR CIE CCRC CC CTO and CEB interrupts to rise ...

Page 3419: ...e is received in MMCHS1 MMCHS_RSP10 MMCHS1 MMCHS_RSP32 MMCHS1 MMCHS_RSP54 and MMCHS1 MMCHS_RSP76 registers CMD9 is an addressed command which means that card s address must be written in MMCHS1 MMCHS_ARG register before the command is issued Table 24 22 Sending CMD9 Register Name Register Address Value Value Description MMCHS1 MMCHS_CON 0x4809C02C 0x00000000 MMC bus is in push pull mode MMCHS1 MMC...

Page 3420: ...byte in MMC card extended CSD register ext_csd It is an IO access function There are two write actions the first one enables a specific data bus width in the card For our use case we used data bus width 4 The second one enables high speed feature in the card 24 6 1 3 4 1 1 Setting Data Bus Width to 4 Table 24 25 shows the set of registers impacted by issuing CMD6 Table 24 25 Setting Data Bus Width...

Page 3421: ...ontroller to perform memory DDRAM to from MMCHS controller transfers The DMA part is not described in this chapter it is described in Chapter 11 SDMA Before any data transfer begins the card must selected by issuing CMD7 command Table 24 24 A write transfer is a finite multiple block write transfer To perform a write transfer the following steps must performed 24 6 1 3 5 1 Send CMD16 Issuing CMD16...

Page 3422: ...CRC DEB and CEB interrupts to rise MMCHS1 MMCHS_CMD 0x4809C10C 0x193a0023 Sends CMD25 whose opcode is 25 response type is 48 bits with CICE DP MSBS BCE DE and CCCE enabled MMCHS1 MMCHS_ARG 0x4809C108 0x00000000 Not used MMCHS1 MMCHS_BLK 0x4809C104 0x00080200 number_blocks 16 block_length 24 6 1 3 6 MMC Read Transfer Either data read or data write transfer uses DMA controller to perform memory DDRA...

Page 3423: ... not the 32 bit byte address For high capacity cards the block size is fixed at 512 bytes Any data transfer when the data bus is involved must be a multiple of 512 bytes The number of blocks for a high capacity card which determines the capacity of the card block_count x 512 bytes is accessible through field C_SIZE in the card s CSD register version 2 0 for SD cards or through the SEC_COUNT field ...

Page 3424: ...09 C12C 0x480B 412C 0x480A D12C MMCHS_STAT RW 32 0x0000 0130 0x4809 C130 0x480B 4130 0x480A D130 MMCHS_IE RW 32 0x0000 0134 0x4809 C134 0x480B 4134 0x480A D134 MMCHS_ISE RW 32 0x0000 0138 0x4809 C138 0x480B 4138 0x480A D138 MMCHS_AC12 R 32 0x0000 013C 0x4809 C13C 0x480B 413C 0x480A D13C MMCHS_CAPA RW 32 0x0000 0140 0x4809 C140 0x480B 4140 0x480A D140 MMCHS_CUR_CAPA RW 32 0x0000 0148 0x4809 C148 0x...

Page 3425: ... activity and the wake up capability can be used if the wake up capability is enabled bit MMCi MMCHS_SYSCONFIG 2 ENAWAKEUP bit is set to 1 0x3 Reserved do not use 2 ENAWAKEUP Wake up feature control RW 1 0x0 Wake up capability is disabled 0x1 Wake up capability is enabled 1 SOFTRESET Software reset RW 0 The bit is automatically reset by the hardware During reset it always returns 0 Read 0x0 Normal...

Page 3426: ...SDIO Use Cases and Tips Programming Flow 3 4 MMC SD SDIO Register Manual MMC SD SDIO Register Summary 5 Table 24 39 MMCHS_CSRE Address Offset 0x024 Physical Address 0x4809 C024 Instance MMCHS1 0x480A D024 MMCHS3 0x480B 4024 MMCHS2 Description Card status response error This register enables the host controller to detect card status errors of response type R1 R1b for all cards and of R5 R5b and R6 ...

Page 3427: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OBI SSB D7D D6D D5D D4D D3D D2D D1D D0D DDIR CDIR CDAT SDCD MCKD SDWP WAKD Bits Field Name Description Type Reset 31 17 Reserved Reserved bit field Do not write any value Reads return 0 R 0x00000 16 OBI Out Of Band Interrupt OBI data value RW 0 0x0 The Out of Band Interrupt pin is driven low 0x1 The Out of Ban...

Page 3428: ...tion returns 0 Write 0x0 If MMCi MMCHS_SYSTEST 3 DDIR bit 0 output mode direction the DAT6 line is driven low If MMCi MMCHS_SYSTEST 3 DDIR bit 1 input mode direction no effect Read 0x1 If MMCi MMCHS_SYSTEST 3 DDIR bit 1 input mode direction returns the value on the DAT6 line high If MMCi MMCHS_SYSTEST 3 DDIR bit 0 output mode direction returns 1 Write 0x1 If MMCi MMCHS_SYSTEST 3 DDIR bit 0 output ...

Page 3429: ...TEST 3 DDIR bit 1 input mode direction returns the value on the DAT3 line high If MMCi MMCHS_SYSTEST 3 DDIR bit 0 output mode direction returns 1 Write 0x1 If MMCi MMCHS_SYSTEST 3 DDIR bit 0 output mode direction the DAT3 line is driven high If MMCi MMCHS_SYSTEST 3 DDIR bit 1 input mode direction no effect 6 D2D DAT2 input output signal data value RW 0 Read 0x0 If MMCi MMCHS_SYSTEST 3 DDIR bit 1 i...

Page 3430: ... 3 DDIR bit 0 output mode direction the DAT0 line is driven high If MMCi MMCHS_SYSTEST 3 DDIR bit 1 input mode direction no effect 3 DDIR Control of the DAT 7 0 pins direction RW 0 Read 0x0 No action Returns 0 Write 0x0 The DAT lines are outputs host to card Read 0x1 No action Returns 1 Write 0x1 The DAT lines are inputs card to host 2 CDAT CMD input output signal data value RW 0 Read 0x0 If MMCi ...

Page 3431: ...RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DVAL HR OD MIT INIT STR CDP DW8 WPP OBIE OBIP CTPL MODE CEATA PADEN CLKEXTFREE Bits Field Name Description Type Reset 31 17 Reserved Reserved bit field Do not write any value R 0x00000 16 CLKEXTFREE External clock free running RW 0 This register is used to maintain card clock out of transfer transacti...

Page 3432: ...t buffers except the buffer of mmci_dat 1 outside of a transaction in order to detect asynchronous card interrupt on mmci_dat 1 line and minimize the leakage current of the buffers 0x0 Disable all the input buffers outside of a transaction 0x1 Disable all the input buffers except the buffer of mmci_dat 1 outside of a transaction 10 9 DVAL Debounce filter value All cards RW 0x3 This register is use...

Page 3433: ... buffer is configured as a stack memory accessible only by the local host or system DMA The pins retain their default type input output or in out SYSTEST mode is operated under the control of the SYSTEST register 3 STR Stream command Only for MMC cards RW 0 This bit must be set to 1 only for the stream data transfers read or write of the adtc commands Stream read is a class 1 command CMD11 READ_DA...

Page 3434: ...r a broadcast host response see Broadcast host response register MMCi MMCHS_CON 2 HR bit 0x0 No Open Drain 0x1 Open Drain or Broadcast host response Table 24 44 Register Call Summary for Register MMCHS_CON MMC SD SDIO Functional Description MMC CE ATA Command Completion Disable Management 0 1 2 MMC SD SDIO Use Cases and Tips Programming Flow 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ...

Page 3435: ...nly if no transaction is executing i e after a transaction has stopped Read operations during transfers may return an invalid value and write operation will be ignored In suspend context the number of blocks yet to be transferred can be determined by reading this register When restoring transfer context prior to issuing a Resume command The local host shall restore the previously saved block count...

Page 3436: ...nding the command itself to the card write action into the register MMCi MMCHS_CMD register Only exception is for a command index specifying stuff bits in arguments making a write unnecessary Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARG Bits Field Name Description Type Reset 31 0 ARG Command argument bits 31 0 1 RW 0x00000000 1 For CMD52 ARG has...

Page 3437: ...his register specifies three types of special command Suspend Resume and Abort These bits shall be set to 0b00 for all other commands 0x0 Others Commands 0x1 Upon CMD52 Bus Suspend operation 0x2 Upon CMD52 Function Select operation 0x3 Upon CMD12 or CMD52 I O Abort command 21 DP Data present select RW 0 This register indicates that data is present and mmci_dat line shall be used It must be set to ...

Page 3438: ...et to 1 the module can perform infinite transfer 4 DDIR Data transfer Direction RW 0 Select This bit defines either data transfer will be a read or a write 0x0 Data Write host to card 0x1 Data Read card to host 3 Reserved Reserved bit field Do not write any value R 0 2 ACEN Auto CMD12 Enable SD cards only RW 0 When this bit is set to 1 the host controller issues a CMD12 automatically after the tra...

Page 3439: ... Description Command response 31 0 Register This 32 bit register holds bits positions 31 0 of command response type R1 R1b R2 R3 R4 R5 R5b R6 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSP1 RSP0 Bits Field Name Description Type Reset 31 16 RSP1 R1 R1b normal response R3 R4 R5 R5b R6 Command Response R 0x0000 39 24 R2 Command Response 31 16 15 0 RSP...

Page 3440: ...1 2 3 MMC SD SDIO Register Manual MMC SD SDIO Register Summary 4 Table 24 57 MMCHS_RSP54 Address Offset 0x118 Physical Address 0x4809 C118 Instance MMCHS1 0x480A D118 MMCHS3 0x480B 4118 MMCHS2 Description Command response 95 64 Register This 32 bit register holds bits positions 95 64 of command response type R2 Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 3441: ...egister This register is the 32 bit entry point of the buffer for read or write data transfers The buffer size is 32bits x256 1024 bytes Bytes within a word are stored and read in little endian format This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput Sequential and contiguous access is necessary to increment the pointer correctly Random or...

Page 3442: ... from this 32 bit read only register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DLEV Reserved Reserved DLA RTA BRE WTA BWE DATI CMDI CLEV Reserved Reserved Reserved Bits Field Name Description Type Reset 31 25 Reserved Reserved bit field Do not write any value R 0x00 24 CLEV mmci_cmd line signal level R This status is used to check the mmc...

Page 3443: ...s status indicates a write transfer active It is set to 1 after the end bit of write command or by activating a continue request MMCi MMCHS_HCTL 17 CR bit following a stop at block gap request This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request Read 0x0 No valid data on the mmci_dat lines Read 0x1 Write data transfer on going 7 3 Reserved Re...

Page 3444: ... 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Table 24 65 MMCHS_HCTL Address Offset 0x128 Physical Address 0x4809 C128 Instance MMCHS1 0x480A D128 MMCHS3 0x480B 4128 MMCHS2 Description Control register This register defines the host controls to set power wake up and transfer parameters MMCi MMCHS_HCTL 31 24 Wake up control MMCi MMCHS_HCTL 23 16 Block gap control MMCi MMCHS_HCTL 15 8 Power control MMCi MM...

Page 3445: ...ct on mmci_dat line 0x0 Disable Read Wait Control Suspend Resume cannot be supported 0x1 Enable Read Wait Control 17 CR Continue request RW 0 This bit is used to restart a transaction that was stopped by requesting a stop at block gap MMCi MMCHS_HCTL 16 SBGR bit Set this bit to 1 restarts the transfer The bit is automatically set to 0 by the host controller when transfer has restarted i e mmci_dat...

Page 3446: ...Prior to this command the MMC card configuration register CSD and EXT_CSD must be verified for compliance with MMC standard specification 4 x This register has no effect when the MMC 8 bit mode is selected MMCi MMCHS_CON 5 DW8 bit set to 1 For SD SDIO cards this bit must be set following a valid SET_BUS_WIDTH command ACMD6 with the value written in bit 1 of the argument Prior to this command the S...

Page 3447: ...re also reset Here below the registers cleared by the MMCi MMCHS_SYSCTL 25 SRC bit MMCi MMCHS_PSTATE CMDI MMCi MMCHS_STAT CC Interconnect and MMC command status management is reinitialized 0x0 Reset completed 0x1 Software reset for mmci_cmd line 24 SRA Software reset for all This bit is set to 1 for reset and released to 0 when RW 0 completed This reset affects the entire host controller except fo...

Page 3448: ...R 0 stable or not Read The internal clock is not stable 0x0 Read The internal clock is stable after enabling the clock 0x1 MMCi MMCHS_SYSCTL 0 ICE bit or after changing the clock ratio MMCi MMCHS_SYSCTL 15 6 CLKD bits 0 ICE Internal clock enable This register controls the internal clock activity RW 0 In very low power state the internal clock is stopped Note The activity of the debounce clock used...

Page 3449: ...changed Read 0x1 Bad Access Write 0x1 Status is cleared 28 CERR Card error RW 0 This bit is set automatically when there is at least one error in a response of type R1 R1b R6 R5 or R5b Only bits referenced as type E error in status field in the response can set a card status error An error bit in the response is flagged only if corresponding bit in card status response error MMCi MMCHS_CSRE in set...

Page 3450: ...index previously emitted It depends on the enable bit MMCi MMCHS_CMD 20 CICE Read 0x0 No error Write 0x0 Status bit unchanged Read 0x1 Command index error Write 0x1 Status is cleared 18 CEB Command end bit error RW 0 This bit is set automatically when detecting a 0 at the end bit position of a command response Read 0x0 No error Write 0x0 Status bit unchanged Read 0x1 Command end bit error Write 0x...

Page 3451: ... interrupt service with card clearing card interrupt status to remove card interrupt source Otherwise the Controller interrupt will be reasserted as soon as MMCi MMCHS_IE 8 CIRQ_ENABLE is set to 1 Writes to this bit are ignored Read 0x0 No card interrupt Read 0x1 Generate card interrupt 7 6 Reserved Reserved bit field Do not write any value RW 00 5 BRR Buffer read ready RW 0 This bit is set automa...

Page 3452: ...it Read 0x0 No transfer complete Write 0x0 Status bit unchanged Read 0x1 Data transfer complete Write 0x1 Status is cleared 0 CC Command complete RW 0 This bit is set when a 1 to 0 transition occurs in the register command inhibit MMCi MMCHS_PSTATE 0 CMDI bit If the command is a type for which no response is expected then the command complete interrupt is generated at the end of the command A comm...

Page 3453: ...RQ_ENABLE BADA_ENABLE CERR_ENABLE DCRC_ENABLE CCRC_ENABLE Bits Field Name Description Type Reset 31 30 Reserved Reserved bit field Do not write any value R 0 29 BADA_ENABLE Bad access to data space Interrupt Enable RW 0 0x0 Masked 0x1 Enabled 28 CERR_ENABLE Card error interrupt Enable RW 0 0x0 Masked 0x1 Enabled 27 25 Reserved Reserved bit field Do not write any value R 0x0 24 ACE_ENABLE Auto CMD1...

Page 3454: ...pt in the SDIO card the status bit is reasserted when this bit is set to 1 This bit must be set to 1 when entering in smart idle mode to enable system to identity wakeup event and to allow controller to clear internal wakeup source 0x0 Masked 0x1 Enabled 7 6 Reserved Reserved bit field Do not write any value RW 00 5 BRR_ENABLE Buffer Read Ready Interrupt Enable RW 0 0x0 Masked 0x1 Enabled 4 BWR_EN...

Page 3455: ...CIRQ_SIGEN BADA_SIGEN CERR_SIGEN DCRC_SIGEN CCRC_SIGEN Bits Field Name Description Type Reset 31 30 Reserved Reserved bit field Do not write any value R 0 29 BADA_SIGEN Bad access to data space signal status Enable RW 0 0x0 Masked 0x1 Enabled 28 CERR_SIGEN Card error interrupt signal status Enable RW 0 0x0 Masked 0x1 Enabled 27 25 Reserved Reserved bit field Do not write any value R 0x0 24 ACE_SIG...

Page 3456: ...te any value RW 0 6 Reserved Reserved bit field Do not write any value RW 0 5 BRR_SIGEN Buffer Read Ready signal status Enable RW 0 0x0 Masked 0x1 Enabled 4 BWR_SIGEN Buffer Write Ready signal status Enable RW 0 0x0 Masked 0x1 Enabled 3 Reserved Reserved bit field Do not write any value R 0 2 BGE_SIGEN Black Gap Event signal status Enable RW 0 0x0 Masked 0x1 Enabled 1 TC_SIGEN Transfer completed s...

Page 3457: ... error This bit is a set to 1 when response index differs R 0 from corresponding command auto CMD12 index previously emitted This bit depends on the command index check enable MMCi MMCHS_CMD 20 CICE bit Read 0x0 No error Read 0x1 Auto CMD12 Index Error 3 ACEB Auto CMD12 end bit error This bit is set to 1 when detecting a 0 at the end R 0 bit position of auto CMD12 command response Read 0x0 No erro...

Page 3458: ...shall not modify this register after the initialization This register is only reinitialized by a hard reset via MMCi_RESET signal Read 0x0 3 0 V Not Supported Write 0x0 3 0 V Not supported Read 0x1 3 0 V Supported Write 0x1 3 0 V Supported MMCHS1 This bit must be set to 1 MMCHS2 and 3 This bit must be left to 0 24 VS33 Voltage support 3 3V Initialization of this register via a write access to this...

Page 3459: ...gement for more information on the value of FUNC_96M_CLK clock signal 7 TCU Timeout clock unit This bit shows the unit of base clock frequency used to R 1 detect Data Timeout Error MMCi MMCHS_STAT 20 DTO bit Read 0x0 kHz Read 0x1 MHz 6 Reserved Reserved This bit is initialized to zero and writes to it are ignored R 0 5 0 TCF Timeout clock frequency The timeout clock frequency is used to detect R 0...

Page 3460: ... 0 Reserved CUR_1V8 CUR_3V0 CUR_3V3 Bits Field Name Description Type Reset 31 24 Reserved Reserved This bit is initialized to zero and writes to it are ignored R 0x0 23 16 CUR_1V8 Maximum current for 1 8 V RW 0x0 Read 0x0 The maximum current capability for this voltage is not available Feature not implemented 15 8 CUR_3V0 Maximum current for 3 0 V RW 0x0 Read 0x0 The maximum current capability for...

Page 3461: ...or revision Examples 0x10 for 1 0 0x21 for 2 1 23 16 SREV Specification Version Number This status indicates the Standard SD Host R 0x00 Controller Specification Version The upper and lower 4 bits indicate the version Read 0x0 SD Host Specification Version 1 0 15 1 Reserved Reserved bit field Do not write any value R 0x0000 0 SIS Slot Interrupt Status This status bit indicates the inverted state o...

Page 3463: ... Overview 3464 25 2 General Purpose Interface Environment 3466 25 3 General Purpose Interface Integration 3469 25 4 General Purpose Interface Functional Description 3476 25 5 General Purpose Interface Basic Programming Model 3480 25 6 General Purpose Interface Register Manual 3486 3463 SWPU177N December 2009 Revised November 2010 General Purpose Interface Copyright 2009 2010 Texas Instruments Inco...

Page 3464: ...on see Chapter 13 System Control Module 25 1 1 Global Features GPIOs include the following global features Synchronous interrupt requests in active mode from each channel are processed by two identical interrupt generation submodules used independently by the imaging video and audio accelerator IVA2 2 and the microprocessor unit MPU subsystems One of these interrupts is mapped on the IVA2 2 subsys...

Page 3465: ... GPIOi GPIO_DATAOUT register through the level 4 L4 interconnect The input line can be fed to GPIO through an optional and configurable debounce cell The debouncing time value is global for all ports of one GPIO module so up to five different debouncing time values are possible The input line value is sampled into the GPIOi GPIO_DATAIN register and can be read through the L4 interconnect In active...

Page 3466: ...ure of the external memory using the pop_tq_temp_sense_ft ball and a GPIO input To do this pop_tq_temp_sense_ft is connected to a GPIO through the customer board This feature is application dependent CAUTION Due to buffer strength an external serial resistor must be connected to the balls corresponding to gpio_120 to gpio_129 pads GPIO multiplexed on these pads should only be used with special ele...

Page 3467: ...eup When the keyboard interrupt is received the processor the MPU and or IVA2 2 subsystem can disable the keyboard interrupt and scan the column channels for the key coordinates The scanning sequence has as many states as column channels For each step in the sequence the processor drives one column channel low and the others high The processor reads the values of the row channels and thus detects ...

Page 3468: ...on 3 2 Reset Value gpio_ 31 0 I O GPIO in HiZ configuration mode 4 gpio_ 186 34 I O GPIO in HiZ configuration mode 4 gpio_ 191 188 I O GPIO in HiZ configuration mode 4 1 I Input O Output 2 Some of the pins have special or restricted use For more information see Table 25 5 3 For more information about pin configuration modes see Chapter 13 System Control Module 3468 General Purpose Interface SWPU17...

Page 3469: ...IO_ 115 112 gpio_ 126 116 GPIO_ 126 116 Public Version www ti com General Purpose Interface Integration 25 3 General Purpose Interface Integration 25 3 1 Description Figure 25 4 highlights the general purpose interface integration in the device Figure 25 4 General Purpose Interface Integration 25 3 1 1 Clocking Reset and Power Management Scheme 25 3 1 1 1 Clocking Each GPIO module uses two clocks ...

Page 3470: ...n it is active low level In each GPIO module the RESETDONE bit GPIOi GPIO_SYSSTATUS 0 monitors the internal reset status it is set when the reset completes For more information see Chapter 3 Power Reset and Clock Management Software reset Each GPIO module has its own software reset using the GPIOi GPIO_SYSCONFIG 1 SOFTRESET bit where i 1 2 3 4 5 or 6 The software reset has the same effect as the h...

Page 3471: ...general purpose interface has six identical idle mode request acknowledge handshake mechanisms with the PRCM module see Figure 25 4 and Section 25 3 1 2 Hardware Requests One per GPIO module The general purpose interface allows GPIOs to enter idle mode based on the GPIOi GPIO_SYSCONFIG 4 3 IDLEMODE bit field The idle acknowledge depends on the configuration and activity of each GPIO module Smart i...

Page 3472: ...ate can be checked by the PRCM CM_IDLEST_WKUP 3 ST_GPIO1 bit 0 Idle 1 active and is idle only when GPIO1 is configured in smart idle mode and has asserted its idle acknowledge GPIO2 to GPIO6 wake up status can be checked by accessing the corresponding bits in the PRCM PM_WKST_PER register read 0 No wakeup occurred read 1 Wakeup occurred write 1 Status bit reset The GPIO1 wake up status can also be...

Page 3473: ...mapped on the MPU INTC Synchronous interrupt request line 2 is mapped on the IVA2 2 INTC Table 25 3 lists the interrupt lines that are driven out from the general purpose interface to the MPU INTC and the IVA2 2 INTC Table 25 3 Interrupts Name Mapping Comments GPIO1 GPIO1_MPU_IRQ M_IRQ_29 Destination is the MPU INTC GPIO1_IVA2_IRQ IVA2_IRQ 28 Destination is the IVA2 2 INTC GPIO2 GPIO2_MPU_IRQ M_IR...

Page 3474: ... 4 shows the wake up signals mapping Table 25 4 Wake Up Signals Name Mapping Comments GPIOi_WAKE GPIOi_SWAKEUP Where i 1 2 3 4 5 and 6 Destination is the PRCM module Table 25 5 describes the GPIO channels Table 25 5 GPIO Channel Description Channel Type 1 Mapping Wake Up Feature Comments Number GPIO1 31 0 I O gpio_ 31 0 Yes GPIO 2 GPIO2 0 I No Not available on external balls Read value is always 0...

Page 3475: ...l shutdown comparator output signal TSHUT is an output from the BANDGAP module This signal is low during normal operation and goes high during a thermal shutdown event When channel 31 of GPIO4 is not connected to a ball of the device the corresponding pin is configured in a mode different from the configuration mode 4 for more information about pin configuration see Chapter 13 System Control Modul...

Page 3476: ...rupt enable1 OR32 I O pins gpif 006 Public Version General Purpose Interface Functional Description www ti com 25 4 General Purpose Interface Functional Description Figure 25 5 shows the general purpose interface description Figure 25 5 General Purpose Interface Description Figure 25 5 details GPIOs in the general purpose interface block diagram with their configuration registers and their main fu...

Page 3477: ...are set to enable the interrupt generation see Section 25 5 3 Interrupt and Wakeup a synchronous path samples the transitions and levels on the input GPIO with the internally gated interface clock see Section 25 3 1 1 4 4 Module Power Saving When an event matches the programmed settings see Section 25 5 3 Interrupt and Wakeup the corresponding bit in the interrupt status register is set to 1 and o...

Page 3478: ...i GPIO_IRQSTATUS2 In idle mode the interface clock is shut down and the GPIO configuration registers are programmed see Section 25 5 3 Interrupt and Wakeup an asynchronous path detects the expected transition s on a GPIO input based on register programming and activates an asynchronous wake up request by the sideband signal GPIOi_SWAKEUP where i 1 2 3 4 5 and 6 if the wakeup enable register is set...

Page 3479: ... receives an interrupt request issued by GPIO it reads the corresponding interrupt status register GPIOi GPIO_IRQSTATUS1 or GPIOi GPIO_IRQSTATUS2 to determine which GPIO input triggered the interrupt or the wake up request After servicing the interrupt or acknowledging the wake up request the processor resets the status bit and releases the interrupt line by writing 1 in the corresponding bit of t...

Page 3480: ...the corresponding clock is not gated and the detection starts immediately 25 5 2 Set and Clear Instructions 25 5 2 1 Description GPIO implements the set and clear protocol register update for the GPIOi GPIO_DATAOUT GPIOi GPIO_IRQENABLE1 GPIOi GPIO_ IRQENABLE2 and GPIOi GPIO_WAKEUPENABLE registers This protocol is an alternative to the atomic test and set operations and consists of writing operatio...

Page 3481: ...er returns 0b0000 0001 0000 0000 bit 0 is cleared NOTE Although the general purpose interface registers are 32 bits wide only the less significant 16 bits are represented in this example Figure 25 10 shows an example of a clear instruction Figure 25 10 Write GPIO_CLEARDATAOUT Register Example 25 5 2 3 Set Instruction 25 5 2 3 1 Set Register Addresses Set interrupt enable registers GPIOi GPIO_SETIR...

Page 3482: ...nterface clock These registers can be accessed with direct read write operations or using the alternate set and clear protocol register update feature This feature enables to set or clear specific bits of these registers with a single write access to the corresponding set interrupt enable1 or interrupt enable2 registers or to the clear interrupt enable1 or interrupt enable2 registers address see S...

Page 3483: ...GPIO_RISINGDETECT and or falling edge interrupt wakeup enable register write 1 or 0 to the corresponding bit of GPIOi GPIO_FALLINGDETECT NOTE Interrupt generation on both edges on one input is configured by setting the corresponding bit to 1 in the rising detect enabling register GPIOi GPIO_RISINGDETECT and falling detect enabling register GPIOi GPIO_FALLINGDETECT along with the interrupt enable b...

Page 3484: ...write operations or by using the alternate set and clear protocol register update feature This feature lets you set or clear specific bits of this register with a single write access to the set output data register GPIOi GPIO_SETDATAOUT or to the clear output data register GPIOi GPIO_CLEARDATAOUT address see Section 25 5 2 Set and Clear Instructions If the application uses a pin as an output and d...

Page 3485: ...rts of one GPIO module so up to six different debouncing values are possible The debounce cell is running with the debounce clock 32 kHz This register represents the number of the clock cycle s one cycle is 31ms long to be used The following formula describes the required input stable time to be propagated to the debounced output Required input line stable GPIOi GPIO_DEBOUNCINGTIME 7 0 DEBOUNCVAL ...

Page 3486: ... GPIO_REVISION R 32 0x000 0x4831 0000 GPIO_SYSCONFIG RW 32 0x010 0x4831 0010 GPIO_SYSSTATUS R 32 0x014 0x4831 0014 GPIO_IRQSTATUS1 RW 32 0x018 0x4831 0018 GPIO_IRQENABLE1 RW 32 0x01C 0x4831 001C GPIO_WAKEUPENABLE RW 32 0x020 0x4831 0020 GPIO_IRQSTATUS2 RW 32 0x028 0x4831 0028 GPIO_IRQENABLE2 RW 32 0x02C 0x4831 002C GPIO_CTRL RW 32 0x030 0x4831 0030 GPIO_OE RW 32 0x034 0x4831 0034 GPIO_DATAIN R 32 ...

Page 3487: ... 0x4905 0064 GPIO_CLEARIRQENABLE2 RW 32 0x070 0x4905 0070 GPIO_SETIRQENABLE2 RW 32 0x074 0x4905 0074 GPIO_CLEARWKUENA RW 32 0x080 0x4905 0080 GPIO_SETWKUENA RW 32 0x084 0x4905 0084 GPIO_CLEARDATAOUT RW 32 0x090 0x4905 0090 GPIO_SETDATAOUT RW 32 0x094 0x4905 0094 Table 25 9 GPIO3 Register Summary Register Name Type Register Width Address Offset Physical Address Bits GPIO_REVISION R 32 0x000 0x4905 ...

Page 3488: ...IRQENABLE2 RW 32 0x02C 0x4905 402C GPIO_CTRL RW 32 0x030 0x4905 4030 GPIO_OE RW 32 0x034 0x4905 4034 GPIO_DATAIN R 32 0x038 0x4905 4038 GPIO_DATAOUT RW 32 0x03C 0x4905 403C GPIO_LEVELDETECT0 RW 32 0x040 0x4905 4040 GPIO_LEVELDETECT1 RW 32 0x044 0x4905 4044 GPIO_RISINGDETECT RW 32 0x048 0x4905 4048 GPIO_FALLINGDETECT RW 32 0x04C 0x4905 404C GPIO_DEBOUNCENABLE RW 32 0x050 0x4905 4050 GPIO_DEBOUNCING...

Page 3489: ...2 0x084 0x4905 6084 GPIO_CLEARDATAOUT RW 32 0x090 0x4905 6090 GPIO_SETDATAOUT RW 32 0x094 0x4905 6094 Table 25 12 GPIO6 Register Summary Register Name Type Register Width Address Offset Physical Address Bits GPIO_REVISION R 32 0x000 0x4905 8000 GPIO_SYSCONFIG RW 32 0x010 0x4905 8010 GPIO_SYSSTATUS R 32 0x014 0x4905 8014 GPIO_IRQSTATUS1 RW 32 0x018 0x4905 8018 GPIO_IRQENABLE1 RW 32 0x01C 0x4905 801...

Page 3490: ...the register is dedicated to each channel The bit and the corresponding channel are identified with the same number Bit 0 refers to channel 0 bit 1 refers to channel 1 and so on up to 31 25 6 2 Register Descriptions Table 25 13 through Table 25 63 describe the register bits Table 25 13 GPIO_REVISION Address Offset 0x000 Physical Address 0x4831 0000 Instance GPIO1 0x4905 0000 GPIO2 0x4905 2000 GPIO...

Page 3491: ...e module 0x3 Reserved do not use 2 ENAWAKEUP Wake up capability enabled disabled RW 0x0 0x0 Wakeup disable 0x1 Wakeup enable 1 SOFTRESET Software reset This bit is automatically reset by the RW 0x0 hardware During reads it always returns 0 0x0 Normal mode 0x1 The module is reset 0 AUTOIDLE Internal interface clock gating strategy RW 0x0 0x0 Interface clock is free running 0x1 Automatic interface c...

Page 3492: ...R 0x00 0 RESETDONE Internal reset monitoring R 0x0 Internal module reset in on going 0x1 Reset completed Table 25 18 Register Call Summary for Register GPIO_SYSSTATUS General Purpose Interface Integration Reset 0 1 General Purpose Interface Register Manual General Purpose Interface Register Mapping Summary 2 3 4 5 6 7 Table 25 19 GPIO_IRQSTATUS1 Address Offset 0x018 Physical Address 0x4831 0018 In...

Page 3493: ...x4905 001C GPIO2 0x4905 201C GPIO3 0x4905 401C GPIO4 0x4905 601C GPIO5 0x4905 801C GPIO6 Description This register provides IRQ 1 enable information Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQENABLE1 Bits Field Name Description Type Reset 31 0 IRQENABLE1 Interrupt 1 Enable Register RW 0x00000000 0x0 Disable IRQ generation for channel N 0x1 Enab...

Page 3494: ...cription Type Reset 31 0 WAKEUPEN Wake Up Enable Register RW 0x00000000 0x0 Disable wake up generation for channel N 0x1 Enable wake up generation for channel N Table 25 24 Register Call Summary for Register GPIO_WAKEUPENABLE General Purpose Interface Overview Global Features 0 General Purpose Interface Integration Wake Up Generation 1 General Purpose Interface Functional Description Asynchronous ...

Page 3495: ...tion Synchronous Path Interrupt Request Generation 0 Asynchronous Path Wake Up Request Generation 1 Interrupt or Wake Up Line Release 2 General Purpose Interface Basic Programming Model Involved Configuration Registers 3 Description 4 General Purpose Interface Register Manual General Purpose Interface Register Mapping Summary 5 6 7 8 9 10 Table 25 27 GPIO_IRQENABLE2 Address Offset 0x02C Physical A...

Page 3496: ...stance GPIO1 0x4905 0030 GPIO2 0x4905 2030 GPIO3 0x4905 4030 GPIO4 0x4905 6030 GPIO5 0x4905 8030 GPIO6 Description This register controls the clock gating functionality Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED GATINGRATIO DISABLEMODULE Bits Field Name Description Type Reset 31 3 RESERVED Read returns 0 RW 0x00000000 2 1 GATINGRATIO Gati...

Page 3497: ...e corresponding GPIO port is configured as output 0x1 The corresponding GPIO port is configured as input Table 25 32 Register Call Summary for Register GPIO_OE General Purpose Interface Overview Global Features 0 General Purpose Interface Basic Programming Model Description 1 2 Data Input Capture Output Drive 3 4 5 Debouncing Time 6 General Purpose Interface Register Manual General Purpose Interfa...

Page 3498: ... 003C GPIO2 0x4905 203C GPIO3 0x4905 403C GPIO4 0x4905 603C GPIO5 0x4905 803C GPIO6 Description This register is used for setting the value of the GPIO output pins Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAOUTPUT Bits Field Name Description Type Reset 31 0 DATAOUTPUT Output Data RW 0x00000000 Table 25 36 Register Call Summary for Register GPI...

Page 3499: ...rpose Interface Basic Programming Model Power Saving by Grouping the Edge Level Detection 0 1 Description 2 General Purpose Interface Register Manual General Purpose Interface Register Mapping Summary 3 4 5 6 7 8 Table 25 39 GPIO_LEVELDETECT1 Address Offset 0x044 Physical Address 0x4831 0044 Instance GPIO1 0x4905 0044 GPIO2 0x4905 2044 GPIO3 0x4905 4044 GPIO4 0x4905 6044 GPIO5 0x4905 8044 GPIO6 De...

Page 3500: ...e Reset 31 0 RISINGEDGE Rising Edge Interrupt wake up enable RW 0x00000000 0x0 Disable IRQ wake up on rising edge detect 0x1 Enable IRQ wake up on rising edge detect Table 25 42 Register Call Summary for Register GPIO_RISINGDETECT General Purpose Interface Basic Programming Model Power Saving by Grouping the Edge Level Detection 0 1 Description 2 3 4 General Purpose Interface Register Manual Gener...

Page 3501: ... 0050 GPIO2 0x4905 2050 GPIO3 0x4905 4050 GPIO4 0x4905 6050 GPIO5 0x4905 8050 GPIO6 Description This register is used to enable disable the debouncing feature for each input line Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEBOUNCEEN Bits Field Name Description Type Reset 31 0 DEBOUNCEEN Input Debounce Enable RW 0x00000000 0x0 Disable debouncing fe...

Page 3502: ...nt and Wake Up 0 General Purpose Interface Functional Description Synchronous Path Interrupt Request Generation 1 2 General Purpose Interface Basic Programming Model Debouncing Time 3 4 5 6 General Purpose Interface Register Manual General Purpose Interface Register Mapping Summary 7 8 9 10 11 12 13 Table 25 49 GPIO_CLEARIRQENABLE1 Address Offset 0x060 Physical Address 0x4831 0060 Instance GPIO1 0...

Page 3503: ...me Description Type Reset 31 0 SETIRQEN1 Set Interrupt Enable 1 RW 0x00000000 0x0 No effect 0x1 Set the corresponding bit in the GPIO_IRQENABLE1 register Table 25 52 Register Call Summary for Register GPIO_SETIRQENABLE1 General Purpose Interface Basic Programming Model Set Register Addresses 0 General Purpose Interface Register Manual General Purpose Interface Register Mapping Summary 1 2 3 4 5 6 ...

Page 3504: ...4 GPIO2 0x4905 2074 GPIO3 0x4905 4074 GPIO4 0x4905 6074 GPIO5 0x4905 8074 GPIO6 Description Set to 1 the corresponding bits in the GPIO_IRQENABLE2 register Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SETIRQEN2 Bits Field Name Description Type Reset 31 0 SETIRQEN2 Set Interrupt Enable 2 RW 0x00000000 0x0 No effect 0x1 Set the corresponding bit in th...

Page 3505: ...r GPIO_CLEARWKUENA General Purpose Interface Basic Programming Model Clear Register Addresses 0 General Purpose Interface Register Manual General Purpose Interface Register Mapping Summary 1 2 3 4 5 6 Table 25 59 GPIO_SETWKUENA Address Offset 0x084 Physical Address 0x4831 0084 Instance GPIO1 0x4905 0084 GPIO2 0x4905 2084 GPIO3 0x4905 4084 GPIO4 0x4905 6084 GPIO5 0x4905 8084 GPIO6 Description Set t...

Page 3506: ...e Reset 31 0 CLEARDATAOUT Clear Data Output Register RW 0x00000000 0x0 No effect 0x1 Clear the corresponding bit in the GPIO_DATAOUT register Table 25 62 Register Call Summary for Register GPIO_CLEARDATAOUT General Purpose Interface Basic Programming Model Clear Register Addresses 0 Data Input Capture Output Drive 1 General Purpose Interface Register Manual General Purpose Interface Register Mappi...

Page 3507: ...DATAOUT register Table 25 64 Register Call Summary for Register GPIO_SETDATAOUT General Purpose Interface Basic Programming Model Set Register Addresses 0 Data Input Capture Output Drive 1 General Purpose Interface Register Manual General Purpose Interface Register Mapping Summary 2 3 4 5 6 7 3507 SWPU177N December 2009 Revised November 2010 General Purpose Interface Copyright 2009 2010 Texas Inst...

Page 3509: ...P device Topic Page 26 1 Initialization Overview 3510 26 2 Preinitialization 3511 26 3 Power Clocks and Reset Power Up Sequence 3520 26 4 Device Initialization by ROM Code 3520 26 5 Wake Up Booting by ROM Code 3578 26 6 Debug Configuration 3582 3509 SWPU177N December 2009 Revised November 2010 Initialization Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3510: ...booting ROM code mechanism that consists of polling selected interfaces downloading and executing initial software in this case downloaded software in the internal RAM Permanent booting device Memory device containing by default the image to be executed during the booting sequence It is the default memory booting device The permanent booting device is used after warm reset if no software booting c...

Page 3511: ...uccessful device initialization The following sections describe the specific requirements for the preinitialization stage 26 2 1 Power Connections The device can be supplied by an external power integrated circuit IC TI provides a global solution with the device connected to the TWL5030 power management audio codec IC Figure 26 2 shows example power connections between the device and the TWL5030 p...

Page 3512: ...DPLL and delay locked loop DLL vdda_dpll_per Input power for DPLL peripheral vdda_csiphy1 Dedicated power supply for camera serial interface2 CSI2a complex I O vdds_csiphy2 Dedicated power supply for CSI2b complex I O vdda_dsi Dedicated power supply for display serial interface DSI complex I O vdda_dac Video buffers and digital to analog converter DAC power supply vdds_sdmmc1 Power supply for mult...

Page 3513: ...Figure 26 3 Clock and Reset Environment The main features of the system interface are A clock request output to an external square clock source 12 13 16 8 19 2 26 or 38 4 MHz reference clock input from the external crystal oscillator only 12 13 16 8 or 19 2 MHz or the digital clock input all frequencies 32 kHz CMOS clock input An additional clock input up to 54 MHz Two configurable output clocks S...

Page 3514: ...en the core is off The sys_clkreq output signal switches the system clock on or off After POR the hardware configuration enables the internal oscillator assuming that the input clock comes from a crystal The decision whether to bypass the internal oscillator is controlled by the polarity of the sys_boot 6 pin The device operation requires two external input clocks as follows sys_32k The 32 kHz fre...

Page 3515: ...Optional System Output Clock sys_clkout1 and sys_clkout2 Two output clocks sys_clkout1 and sys_clkout2 pins are available sys_clkout1 can output the oscillator clock Its OFF state polarity is programmable sys_clkout2 can output the system clock 12 13 16 8 19 2 26 or 38 4 MHz the core clock CORE DPLL output 96 MHz or 54 MHz sys_clkout2 can be divided by 2 4 8 or 16 and its OFF state polarity is pro...

Page 3516: ...ith the sys_boot pin configuration at the moment of sensing Because these pins have no internal pullup or pulldown capability care must be taken when choosing to use these GPIOs Table 26 3 Table 26 4 and Table 26 5 are decoding tables for sys_boot pins Depending on sys_boot pin configuration during the reset leftmost column the ROM code tries to boot on the first booting device listed If the boot ...

Page 3517: ...ing from the UART HS USB boot If the internal USB transceiver of a supported power management IC is used the IC s configuration interface must be connected to the device through I2C1 No other I2 C interface is supported for this purpose If other USB transceiver is used the ROM code assumes it is powered clocked and out of reset Table 26 3 Memory Preferred Booting Configuration Pins After POR sys_b...

Page 3518: ... When SYS BOOT 5 1 Peripheral Preferred Booting Order First Second Third Fourth Fifth 0b00000 Reserved 1 0b00001 0b00010 0b00011 0b00100 USB OneNAND 0b00101 USB MMC2 0b00110 USB MMC1 0b00111 Reserved 1 0b01000 0b01001 0b01010 0b01011 0b01100 0b01101 USB UART3 MMC1 XIP 0b01110 USB UART3 MMC1 XIPwait DOC 0b01111 USB UART3 MMC1 NAND 0b10000 USB UART3 MMC1 OneNAND 0b10001 USB UART3 MMC1 MMC2 0b10010 U...

Page 3519: ...eNAND 0b00001 NAND NAND 0b00010 OneNAND OneNAND 0b00011 MMC2 MMC2 0b00100 OneNAND OneNAND 0b00101 MMC2 MMC2 0b00110 MMC1 MMC1 0b00111 XIP XIP 0b01000 XIPwait DOC XIPwait DOC 0b01001 MMC2 MMC2 0b01010 XIP XIP 0b01011 XIPwait DOC XIPwait DOC 0b01100 NAND NAND 0b01101 XIP XIP 0b01110 XIPwait DOC XIPwait DOC 0b01111 NAND NAND 0b10000 OneNAND OneNAND 0b10001 MMC2 MMC2 0b10010 MMC1 MMC1 0b10011 XIP XIP ...

Page 3520: ...out ARM CP15 registers see the ARM Architecture Reference Manual NOTE When the ROM Code branches to the first instruction of a GP device Initial software the L2 cache is disabled 26 4 1 1 Booting Types Booting is the process of starting a bootstrap from one of the booting memories The ROM code has two booting functions peripheral booting and memory booting In peripheral booting the ROM code polls ...

Page 3521: ...ins that provide UART3 functionality in their MUXMODE 0 can be used No other UART configuration allows booting from the UART HS USB boot If the internal USB transceiver of a supported power management IC is used the IC s configuration interface must be connected to the device through I2C1 No other I2 C interface is supported for this purpose If other USB transceiver is used the ROM code assumes it...

Page 3522: ...rrupt handler Interface drivers Device drivers Image and execution Other modules init 006 MMC SD FAT 16 32 Public Version Device Initialization by ROM Code www ti com Figure 26 5 ROM Code Architecture 3522 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3523: ...addresses in the PC register Table 26 7 ROM Exception Vectors Address Exception Content 14000h Reset Branch to the public ROM code startup 14004h Undefined PC 4020FFC8h 14008h Software interrupt SWI PC 4020FFCCh 1400Ch Prefetch abort PC 4020FFD0h 14010h Data abort PC 4020FFD4h 14014h Unused PC 4020FFD8h 14018h IRQ PC 4020FFDCh 1401Ch FIQ PC 4020FFE0h ROM code cyclic redundancy check CRC The ROM co...

Page 3524: ... dead loop This function is at address 140C0h The function is assembly code in ARM mode which takes the dead loop address from the R0 register The main purpose of the function is to issue a global software reset before going to a dead loop In addition the function clears the global cold reset status before issuing the global software reset Code This space is used to keep code Code and data This sp...

Page 3525: ... tracing vector word 2 0x4020FFC4 4 Reserved RAM exception vectors The RAM exception vectors provide an easy way to redirect exceptions to the custom handler Table 26 10 shows the contents of the RAM space reserved for RAM vectors The first seven addresses are ARM instructions that load into the PC the value in the next seven addresses These instructions are executed when an exception occurs becau...

Page 3526: ...x4020FFF8 0x4020FFE0 FIQ PC 0x4020FFFC 0x4020FFE4 Undefined 0x14080 0x4020FFE8 SWI 0x14084 0x4020FFEC Prefetch abort 0x14088 0x4020FFF0 Data abort 0x1408C 0x4020FFF4 Unused 0x14090 0x4020FFF8 Interrupt request IRQ 0x14094 0x4020FFFC Fast interrupt request 0x14098 FIQ 3526 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3527: ...first next device from the list Yes No Yes No Configuration header present Yes No Copying or download successful No Yes Step 3 Booting device list set up Step 7 Image execution Jump to code on CS0 Process next booting device Process first booting device init 007 Public Version www ti com Device Initialization by ROM Code 26 4 3 Overall Booting Sequence Figure 26 8 is the ROM code flow chart Figure...

Page 3528: ...booting is executed when booting device is temporary UART or USB Step 5 Memory booting reads data from memory type booting devices Memory booting is described in detail in Section 26 4 7 Memory Booting Step 6 Peripheral booting downloads data from communication interfaces The ROM code uses a simple logical protocol with peripheral booting First the device sends an ASIC ID structure to inform the h...

Page 3529: ...rations during the boot ROM code default settings described in this paragraph Software booting configuration after a software reset described in Section 26 4 4 4 Software Booting Configuration CH described in Section 26 4 8 2 Configuration Header This configuration can be blocked by the software booting configuration this is possible during the memory booting The CH lets the user have a known conf...

Page 3530: ...ice list The second section provides clock settings which are applied before booting The sections are not mandatory and their order is not important The ROM code searches for the next section at the location based on the size filled in the previous section The clock configuration from software booting configuration overwrites the CH settings Table 26 12 Software Booting Configuration Structure Fie...

Page 3531: ...ing clocks Bit 7 Bypass DPLL1 before setting clocks Bit 8 Bypass DPLL3 before setting clocks Bits 24 31 System clock ID Must be set accordingly to the SYS CLK 0x01 12 MHz 0x02 13 MHz 0x03 16 8 MHz 0x04 19 2 MHz 0x05 26 MHz 0x06 38 4 MHz Others Reserved must not be set General Clock Settings PRM_CLKSRC_CTRL 4 Register value PRM_CLKSEL 4 Register value CM_CLKSEL1_EMU 4 Register value Clock Configura...

Page 3532: ...are described in the following sections The common peripheral booting protocol is shown in Figure 26 10 Figure 26 10 Common Peripheral Booting Protocol The ROM code first initializes the interface and sends a message called ASIC ID to a host The content of this message is summarized in Table 26 13 The host uses this message to send only appropriate data to the device according to the identificatio...

Page 3533: ...s If the download passes the peripheral booting succeeds and the image can be executed Table 26 14 Boot Messages Message Name Value Description Peripheral boot 0xF0030002 Continue peripheral booting Change booting device 0xF003XX06 Skip current peripheral booting and continue booting from booting device type indicated by XX 0x00 Void no booting device 0x01 XIP memory 0x02 NAND 0x03 OneNAND 0x04 DO...

Page 3534: ... out No No Yes Yes Change booting device Memory booting Success Time out init 010 Request message 3 s time out Yes No VBUS detect or USB enumeration time out Yes No Wait for ASIC ID request Send ASIC ID Wait for booting message Message 300 ms time out Public Version Device Initialization by ROM Code www ti com Figure 26 11 shows the peripheral booting procedure Figure 26 11 Peripheral Booting Proc...

Page 3535: ...wnload CSST on www ti com Wireless Handset Solution OMAP Platform Development Tools 26 4 5 3 1 USB Driver Descriptors USB devices report their attributes using descriptors A descriptor is a data structure with a defined format Each descriptor begins with a byte wide field that contains the total number of bytes in the descriptor followed by a byte wide field that identifies the descriptor type Usi...

Page 3536: ...pecification release number in BCD bDeviceClass 0xFF Class code bDeviceSubClass 0xFF Subclass code bDeviceProtocol 0xFF Protocol code bMaxPacketSize0 0x40 Maximum packet size for endpoint 0 bNumConfigurations 0x01 Number of possible configurations bReserved 0x00 Reserved for future use Configuration descriptor This descriptor gives information about a specific device configuration The descriptor d...

Page 3537: ...scriptor describing this interface Endpoint descriptor Each endpoint used for an interface has its own descriptor This descriptor contains information required by the host to determine the bandwidth requirements of each endpoint This descriptor is returned as part of the GetDescriptor Configuration request See Table 26 20 and Table 26 21 for details Table 26 20 BULK IN Endpoint Descriptor Field Va...

Page 3538: ...tring descriptor type bString Texas Instruments Manufacturer string Table 26 24 Product ID String Descriptor Field Value Description bLength 0x12 Size of this descriptor in bytes bDescriptorType 0x03 String descriptor type bString Multimedia device or specific Product string Device specific vendor string Table 26 25 Configuration String Descriptor Field Value Description bLength 0x08 Size of this ...

Page 3539: ...or Selection 26 4 5 3 3 USB Driver Functionality Transactions supported The following transactions are supported Control transactions Used for standard device requests Bulk transactions Used for data transfer in the image downloading stage The ASIC ID is sent on the Bulk IN endpoint and the image is transferred over the Bulk OUT endpoint from the host The USB first attaches to the host as an FS de...

Page 3540: ... SET_FEATURE Sets or enables a specific feature Supported only for ENDPOINT_HALT feature SET_INTERFACE Selects an alternate setting in an interface No Runtime setting of alternate features is not supported SYNCH_FRAME Sets and reports an endpoint synchronization No because isochronous transfers are not frame used 26 4 6 Fast External Booting 26 4 6 1 Overview The fast external boot is a special me...

Page 3541: ...iew The memory booting process starts an external code in memory type booting devices Because the device always uses the memory type booting devices for booting they are called permanent booting devices The supported permanent booting devices are All NOR devices up to 2 Gb 256M bytes NAND devices from 64Mb OneNAND Flex OneNAND devices from 512Mb SD MMC eSD eMMC flash cards with active primary part...

Page 3542: ...ge if the booting device is not XIP The last step is image execution Unsuccessful execution or return from image results in a dead loop If CH copying or shadowing fails memory booting returns to the main booting procedure which selects the next booting device for booting Figure 26 14 Memory Booting Procedure 26 4 7 2 Non XIP Memory Figure 26 15 shows the procedure used when memory booting runs wit...

Page 3543: ...ory reserves only one block for booting which overlaps the XIP part MMC SD FAT card booting consists of reading a file Because there is only one file read it can be considered one block trial When no file system is present the first sectors of two blocks 128KB each are searched Table 26 29 Blocks and Sectors Searched on Non XIP Memories Memory Maximum Number of Checked Blocks Number of Sectors Sea...

Page 3544: ...booting device Booting from an XIP booting device consists of the following steps 1 Configure the GPMC for XIP booting device access 2 Verify that the CH is present at address 0x0800 0000 If it is copy the entire sector 512 B to internal RAM and execute the CH 3 Set the image location 0x0800 0000 if the CH is not found 0x0800 0200 if the CH 512 bits is found 4 Verify that a bootable image is at th...

Page 3545: ... for image Block size depends on the booting device For NAND memory booting no user intervention is needed the information in the following subsections is included for debugging Only the CH which is not mandatory lets the user change clock settings and GPMC parameters Failure in CH copying causes a return to the main booting procedure which selects the next booting device for booting 26 4 7 4 1 In...

Page 3546: ... ready for operation then the Read ID command is issued If the Read Device ID is recognized as a supported booting device the booting device parameters are extracted from an internal ROM code table Table 26 32 lists the supported NAND devices Table 26 32 Supported NAND Devices Capacity Device ID Bus Width Page Size in KB 64Mb E6h 8 512 128Mb 33h 8 512 128Mb 73h 8 512 128Mb 43h 16 512 128Mb 53h 16 ...

Page 3547: ...yte of the NAND ID data Because of inconsistency among manufacturers only NAND devices recognized to be at least 2Gb have these parameters updated Therefore the ROM code supports 4 KB page NAND devices but only if their size according to the table is at least 2Gb NAND devices smaller than 2Gb have the block size parameter set to 32KB when the page size is 512KB and to 128KB when the page size is 2...

Page 3548: ...uence is described in Figure 26 17 The description of the ID2 data content is summarized in Table 26 34 If the ROM code fails to identify booting device ID or ID2 it returns with FAIL When the booting device is successfully detected the ROM code changes the GPMC to 16 bit bus width if necessary 3548 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments I...

Page 3549: ...rs from table Update page size and block size for devices 1Gb Extract NAND parameters from ID2 Issue Reset command init 023 No No Failed Success Yes Yes Public Version www ti com Device Initialization by ROM Code Figure 26 16 NAND Device Detection 3549 SWPU177N December 2009 Revised November 2010 Initialization Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3550: ... command 0x00 Issue address 0x00 0x02 0x02 0x00 0x00 Issue Read confirm 0x30 Read 256 bytes Issue Reset command Failed Success init 024 No No No No Yes Yes Yes Yes Public Version Device Initialization by ROM Code www ti com Figure 26 17 NAND ID2 Detection 3550 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3551: ... nibble 1H 1 plane 4H 4 planes For future use 10 Partial prg count X Per page 1H No partial prg allowed 2H 2 per page 11 Read time maximum 12 Prg time maximum 13 Erase time maximum 252nd Identification number X B2184D7Bh 255th 256th Register spec XvX Higher nibble Major digit version Lower nibble Decimal digit Registers according to spec 2v0 20h Bad block detection verification Invalid blocks cont...

Page 3552: ... does not equal FFFFh 6th word in 1st page 1st word in 2nd page 1st word in 2nd page 6th word in 2nd page Figure 26 18 shows the invalid block detection routine The routine consists in reading spare areas and checking data according to the conditions listed in Table 26 35 The flags are used internally to give information about the validity of each block Figure 26 18 Bad NAND Invalid Block Detectio...

Page 3553: ...all pages and large pages several ECC data are stored in the spare area of the page If the computed ECC data and the stored ECC data are equal the read sector function returns the read 512 byte sector without error Otherwise the ROM code tries to correct the error in the sector and returns the data if successful If there are uncorrectable errors the ROM code returns with FAIL Figure 26 19 shows th...

Page 3554: ...han single level cell SLC NANDs As a consequence reading data from MLC NANDs requires a stronger error correction capability Usually NAND manufacturers recommend Bose Chaudhuri Hocquenghem BCH code which can correct 4 or 8 bit errors in 512 byte data sectors Because of the specific MLC implementation in the device which is not fully hardware based ROM code cannot implement sector BCH encoding Ther...

Page 3555: ...ding are added at the end 3 A sector is represented by 260 words 16 bits each 4 All 16 bit words are converted into 32 bit words by adding 12 bits of the BCH result and 4 bit zero padding Figure 26 21 shows how a sector of image data is processed Figure 26 21 MLC NAND Data Encoding The BCH algorithm has the following characteristics 32 20 2 32 bit message 20 bit data 2 bit error correction capabil...

Page 3556: ... on this controller ROM Code can support any existing and forecasted OneNAND Flex OneNAND devices The OneNAND Flex OneNAND device is a NAND matrix coupled with RAM buffers and a NOR type interface ECC correction handling is done automatically by the internal state machine The page to be accessed is first loaded in the RAM buffer using memory mapped registers Then the page is read directly from the...

Page 3557: ...If the booting device is successfully recognized the ROM code reads the booting device configuration amount and size of data buffers and configures it for asynchronous mode default 26 4 7 5 2 OneNAND Flex OneNAND Read Sector Procedure When booting requests a sector from the OneNAND Flex OneNAND device the ROM code issues the load operation which transfers the content of the requested sector to the...

Page 3558: ...eSD 1 8 V I O voltage and 3 0 V Core voltage on port 2 The external transceiver mode on port 2 is not supported Initial 1 bit MMC mode 4 bit SD mode Clock frequency Identification mode 400 kHz Data transfer mode 20 MHz Only one card connected to the bus Raw mode image data read directly from card sectors FAT12 16 32 support with or without a master boot record MBR For a FAT 12 16 32 formatted memo...

Page 3559: ...O in two modes 1 8 V or 3 0 V provided the correct voltage supply is connected to the VDDS_SDMMC1 pin Hardware provides the mechanism to detect the presence of 3 0 V on VDDS_SDMMC1 If the hardware does not detect 3 0 V the ROM code assumes 1 8 V voltage is present and configures the I O pads accordingly To enable the hardware to generate the correct levels on the SD MMC interface the following con...

Page 3560: ...DO is set to 3 0 V when booting from MMC port 1 is requested from the sys boot pins VMMC2_LDO is set to 3 0 V when a booting from MMC port 2 is requested from the sys boot pins Users must furnish VIO 1 8 V to the SD MMC memory respecting the timing sequence imposed by the memory 26 4 7 6 1 2 Booting From eMMC eSD Memory From SD MMC Port 1 When TWL5030 is Implemented ROM code can boot from the embe...

Page 3561: ... to Support eMMC eSD Booting on SD MMC Port 2 26 4 7 6 1 4 Booting When TWL5030 is Not Implemented When TWL5030 is not implemented the ROM code assumes the following The MMC SD card memory connected to SD MMC port 1 is powered by a 3 0 V power supply after any POR or software or warm reset The VDDS_SDMMC1 pin of the device is connected to a 3 0 V power supply that is the same as the one that power...

Page 3562: ... commands CMD1 and ACMD41 The ROM code uses this command difference to differentiate between MMC and SD cards that is CMD1 is supported only by MMC and ACMD41 is supported only by SD The ROM code first sends a CMD1 to the card and gets an answer only if an MMC card is connected If no answer is received ACMD41 a combination of CMD55 and ACMD41 is sent and an answer is expected from an SD card If an...

Page 3563: ... type FAT12 16 or FAT32 An MMC SD card can be configured as floppy like or hard drive like When acting like a floppy the content of the card is a single FAT12 16 32 file system without an MBR holding a partition table When acting like a hard drive an MBR is present in the first sector of the card This MBR holds a table of partitions one of which must be FAT12 16 32 primary and active According to ...

Page 3564: ...assed Passed Failed Read 1st sector Read partition 1st sector Find booting file in the root directory Buffers FAT entries in FAT buffer init 027 Failed Public Version Device Initialization by ROM Code www ti com Figure 26 29 SD MMC Booting 3564 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3565: ...2 Signature 0xAA55 Table 26 38 Partition Table Entry Offset Length Entry Description Value Bytes 0000h 1 Partition state 00h Inactive 80h Active 0001h 1 Partition start head Hs 0002h 2 Partition start cylinder and sector Cs 7 0 Cs 9 8 Ss 5 0 0004h 1 Partition type 01h FAT12 04h 06h 0Eh FAT16 0Bh 0Ch 0Fh FAT32 0005h 16 Partition end head He 0006h 2 Partition end cylinder and sector Ce 7 0 Ce 9 8 Se...

Page 3566: ... present in case of a floppy like system the first sector of the booting device is read and used later The read sector is checked to be a valid FAT12 16 or FAT32 partition If this fails if another partition type is used for instance Linux FS or if the partition is not valid the ROM code returns with FAIL The FAT file system consists of Boot sector which holds the BIOS parameter block BPB Not all a...

Page 3567: ...ep 3 Find the booting file When a partition is found the root directory entries are searched for a booting file named MLO in the root directory of the FAT12 16 32 file system The file is not searched in any other location For a FAT12 16 file system the root directory has a fixed location which is cluster 0 For a FAT32 file system its cluster location is given by BPB_RootClus The formula to find th...

Page 3568: ... root directory is reached Entries with the ATTR_LONG_NAME attribute LFN and first byte at E5h erased file are ignored When found the first cluster offset of the file is read from the DIR_FstClusHi DIR_FstClusLo fields There is a slight difference between FAT12 16 and FAT32 when handling the root directory On FAT12 16 this directory has a fixed location see above and length fixed by BPB_RootEntCnt...

Page 3569: ...booting file has been found the ROM code buffers each FAT entry corresponding to the file in a sector way This means each cluster is translated to one or several sectors depending on how many sectors are in a cluster BPB_SecPerClus This buffer is used later by the booting procedure to access the file 26 4 7 7 DiskOnChip The ROM code support for DiskOnChip devices has the following characteristics ...

Page 3570: ...first sector can contain CH The GP peripheral booting image contains only code Figure 26 32 Image Format 26 4 8 2 Configuration Header The CH is optional and is required only if the customer wants to use settings different from the ROM code defaults for example clock frequencies SDRAM double data rate DDR SDRAM settings GPMC settings The CH can be present only when booting from a memory type devic...

Page 3571: ...ic to the clock system The ROM code configures the device clocking to some default settings as described in Section 26 4 4 2 Clocking Configuration The CH CHSETTINGS section contains a method to override the ROM code default clocking settings The fields are described in Table 26 42 The clocking procedure as well as the clocking setting structure are described in Section 26 4 4 4 Software Booting C...

Page 3572: ...ed for section verification C0C0C0C2h Enables disables the section 0004h Valid 00h Disable Others Enable 0005h Reserved 0008h SDRC_SYSCONFIG LSB CR 000Ah SDRC_CS_CFG LSB CH CR 000Ch SDRC_SHARING LSB CH CR 000Eh SDRC_ERR_TYPE LSB CR 0010h SDRC_DLLA_CTRL LSB CH CR 0012h SDRC_DLLA_CTRL MSB CH CR 0014h Reserved Write 0s for future compatibility CR 0016h Reserved Write 0s for future compatibility CR 00...

Page 3573: ...DRC_RFRCTRL_1 MSB CH CR 0054h Reserved write 0s for future compatibility CR 0056h Reserved write 0s for future compatibility CR CH CR 0 0 CS0 not configured 0058h Flags 1 CS0 configured 1 0 CS1 not configured 1 CS1 configured 005A Must be 0 CH CR 26 4 8 2 3 CHFLASH The CHFLASH configuration header contains settings specific to the GPMC For more information seeSection 10 1 GPMC inChapter 10 Memory ...

Page 3574: ... by default to these settings 400 kHz clock during identification mode 19 2 MHz clock during data transfer mode Table 26 45 CHMMCSD CH Offset Register Modified Description Key used for section verification 0000h Section key C0C0C0C4h Enables disables the section 0004h Valid 00h Disable Other Enable 0005h Reserved 0008h MMCHS_SYSCTRL MSB Register value 000Ah MMCHS_SYSCTRL LSB 0xFFFFFFFF Do not upda...

Page 3575: ... to the first executable instruction in the initial software The execution address is the first word after the image header After the branch the ARM runs in public ARM supervisor mode The R0 register points to the booting parameter structure that contains information about booting Table 26 47 shows the booting parameters structure Table 26 47 Booting Parameter Structure Offset Field Size Descripti...

Page 3576: ...its location during the tracing initialization of the second ROM code run after the cold reset run These data can be used for debugging Table 26 48 Tracing Vector Bit Number Group Meaning 0 General Reset 1 General ROM code C main 2 General ROM code runs after the cold reset 3 Boot Booting started 4 Memory boot Memory booting started 5 Boot No more booting device to check 6 Peripheral boot Peripher...

Page 3577: ...C 37 Memory boot MMC SD2 38 Memory boot MMC SD1 39 Memory boot XIP memory with wait monitoring 40 Reserved Reserved 41 Reserved Reserved 42 Reserved Reserved 43 Reserved Reserved 44 Reserved Reserved 45 Reserved Reserved 46 Reserved Reserved 47 Memory boot No known NAND was detected 48 Memory boot MLC NAND image was detected 49 Memory boot NAND boot was attempted from block 0 50 Memory boot NAND b...

Page 3578: ...ss in the public restore pointer field of the CONTROL_SAVE_RESTORE_MEM structure The CONTROL_SAVE_RESTORE_MEM memory of the SCM saves and restores mandatory information to automatically reconfigure the SDRC and PRCM registers The SDRC and clock registers must be saved by users in the respective structures see Table 26 50 and Table 26 51 in the SCM scratchpad memory before going to off mode to be a...

Page 3579: ...Booting by ROM Code Figure 26 34 CONTROL_SAVE_RESTORE_MEM Format Table 26 49 CONTROL_SAVE_RESTORE_MEM Field Definitions Field Name Size Description Booting Configuration Pointer 32 bits Address of public booting information used after a software reset Public Restore Pointer 1 32 bits Address of the public restore function to branch to when exiting a wake up reset boot 1 Field to be set by users 35...

Page 3580: ...ck Offset 31 24 23 16 15 8 7 0 0x0000 PRM_CLKSRC_CTRL 0x0004 PRM_CLKSEL 0x0008 CM_CLKSEL_CORE 0x000C CM_CLKSEL_WKUP 0x0010 CM_CLKEN_PLL 0x0014 CM_AUTOIDLE_PLL 0x0018 CM_CLKSEL1_PLL 0x001C CM_CLKSEL2_PLL 0x0020 CM_CLKSEL3_PLL 0x0024 CM_CLKEN_PLL_MPU 0x0028 CM_AUTOIDLE_PLL_MPU 0x002C CM_CLKSEL1_PLL_MPU 0x0030 CM_CLKSEL2_PLL_MPU 0x0034 Reserved Table 26 51 describes the SDRC context restore block Tab...

Page 3581: ... Block continued SDRC Register Byte Organization in the SCM Block Offset 31 24 23 16 15 8 7 0 0x0044 ACTIM_CTRLB_1 0x0048 RFR_CTRL_1 0x004C Reserved Reserved 0x0050 Reserved 0x0054 Reserved 3581 SWPU177N December 2009 Revised November 2010 Initialization Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3582: ...on 1 Channel 1 trigger Boot mode 1 I Input O Output To reduce power consumption the power domain that contains the debug logic can be switched off in normal operating mode CAUTION Before starting the debugger the DEBUG power domain must be activated by applying a minimum of 10 TCK pulses to the device after nTRST is pulled high To prevent the JTAG_TMS pin from floating when the EMU power domain is...

Page 3583: ...DR scan Parameter The route to JTAG shift state is shortest transition Parameter The JTAG shift state is shift dr Parameter The JTAG destination state is pause dr Parameter The bit length of the command is 32 Parameter The send data value is 0xa3002108 Parameter The actual receive data is discarded Function Do a send only all ones JTAG IR DR scan Parameter The JTAG shift state is shift ir Paramete...

Page 3585: ... describes the debug and emulation module on the device Topic Page 27 1 Debug and Emulation Overview 3586 27 2 ICEPick Module 3588 27 3 SDTI Module 3607 27 4 Emulation Pin Manager 3639 3585 SWPU177N December 2009 Revised November 2010 Debug and Emulation Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3586: ...or debug and emulation Figure 27 1 Debug and Emulation Hardware in the Device The debug software and hardware components lets the user control multiple central processing unit CPU cores embedded in the device in a global or local manner This environment provides Synchronized global starting and stopping of multiple processors the ICEPick feature is not supported by all the platform processors Star...

Page 3587: ...ager It allows the selection of an emulation interface to be routed to the device boundary pads The EPM is described Section 27 4 Emulation Pin Manager 27 1 2 4 DAP The debug access port DAP enables the external debugger to directly access the entire memory space of the device without requiring the processor to enter the debug state and be programmed with a load or store instruction The DAP direct...

Page 3588: ...w ICEPick supports Individually selecting one or more of the TAPs for scan without disrupting the state of other TAPs Management of the reset to many processors Management of the power and clock of many power domains The ICEPick module has the following cheracteristics IR length of 6 bits DR length of 1 in bypass mode DR length from 1 to 32 see Section 27 2 4 5 ICEPick Instructions Boot mode contr...

Page 3589: ... input to the device jtag_tdo Test Data Output 1 O HiZ Scans data output of the device jtag_emu0 Emulation 0 1 IO HiZ Channel 0 trigger boot mode HS RTDX trace port jtag_emu1 Emulation 1 1 IO HiZ Channel 1 trigger boot mode HS RTDX trace port For more information about ICEPick boot modes see Section 27 2 4 4 The ICEPick module has a TAP state machine consistent with the IEEE 1149 1 specification F...

Page 3590: ...ck internal TAP can also be referenced as the primary TAP it is always in the first position in the scan chain ICEPick TAP input is connected to the device jtag_tdi pin Table 27 2 Secondary Debug TAP Mapping Secondary CoreSight TAP No Modules Accessed Through That JTAG Port JTAG port D2D No 0 Die to die interface IVA No 1 C64x ICEMaker ARM968 No 2 ARM968 ICECrusher IVA Sequencer DAP Yes 3 MPU ICEC...

Page 3591: ...27 4 All unused TAP controller instructions default to the bypass register Several instructions are reserved for extensions to the ICEPick opcodes Table 27 4 ICEPick Instructions IR ICEPick Instruction Extended Instruction Access 000000 BYPASS Not available Always open 000001 Reserved Not available Always open 000010 ROUTER Not available Connected 000011 Reserved Not available Always open 000100 I...

Page 3592: ...of this instruction has no effect on the operation of the on chip system logic Capture DR state The 32 bit ID code of the device is loaded into the data shift register during the Capture DR state Shift DR state The value captured is shifted out during the Shift DR TAP state with the LSB first while the value of jtag_tdi is shifted into the most significant bit MSB of the data shift register Data i...

Page 3593: ...Description The IEEE 1149 1 specification mandates a BYPASS instruction and that the instruction decode must be an all ones value equal in length to the instruction register length All unused TAP controller instruction codes default to having the same characteristics as the BYPASS instruction The BYPASS instruction and all instruction codes defaulting to the BYPASS instruction specifies a DR shift...

Page 3594: ...itten to Private_Enable when the Run_Test_Idle state is reached The Private_Enable instruction is used to prevent extended TAP functions from being invoked until the connect sequence completes This can be used to ensure test functions are held in reset even though the chip level test reset is no longer asserted 27 2 4 5 3 7 ROUTER Instruction Description The ROUTER instruction specifies that the D...

Page 3595: ...d out during the Shift DR TAP state with the LSB first while the value of jtag_tdi is shifted into the MSB of the data shift register Data is shifted from the MSB to the LSB The shifted in value may contain a new register read or write request and the associated payload Update DR state For a read or write the scan chain is decoded during the Update DR state Figure 27 5 shows multiple read access i...

Page 3596: ...change during operation POR The bit is reset upon POR QTLR The bit is reset upon state change to Test Logic Reset if the ICEPick TAP is visible and the ICEPick register reset is not blocked In this sense reset based on reaching the Test Logic Reset state is qualified QnTRST The bit is reset on assertion low of the device pin nTRST if the ICEPick TAP is visible and the ICEPick register reset is not...

Page 3597: ...ed in TDI is preserved and scanned out of TDO one ITCK cycle later Type RW 0 BYPASS Table 27 10 TAPID Description The device identification register allows the manufacturer part number and version of a component to be determined through the TAP The device identification register is scanned in response to the IDCODE instruction This allows the manufacturer part number and variant for the component ...

Page 3598: ...4 MINOR Revision of the ICEPick R See 1 23 20 TEST_TAP Number of Test TAPs instantiated A value of 0 indicates 16 R TAPs since 0 is an invalid number of TAPs 19 16 EMU_TAP Number of EMU TAPs instantiated A value of 0 indicates 16 R TAPs since 0 is an invalid number of TAPs 15 4 ICEPICK An identifier of the Icepick Type Current Types are A B and C R 0x1CC 3 RESERVED Reserved reads back a zero R 0 2...

Page 3599: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLOCK REGISTER PAYLOAD WRITE Bits Field Name Description Type Reset 31 WRITE Write 0 a read operation is executed RW Write 1 a write operation is executed Read 0 previous write successful Read 1 previous write failed 30 28 BLOCK Select the block to read write See Table 27 15 RW 27 24 REGISTER Select the register in the block to read write See RW Section 27 2 4 6 3...

Page 3600: ...ESERVED RESERVED RESERVED RESERVED DEVICETYPE REDUCEDTCK SYSTEMRESET SYSTEMSTATUS TDOALWAYSOUT BLOCKSYSRESET GLOBALEXEMASK KEEPPOWERINTLR CLEARALLEXEFLAG FREERUNNINGEMUL GLOBALRELEASEWIR ADVANCERTCKTIMING UNNATURALSYSRESET Bits Field Name Description Type Reset 31 24 TAP_ROUTING See Table 27 14 RW 23 18 RESERVED Reserved Read return reset value write reset value for further R 0x0 ARST compatibilit...

Page 3601: ...EEPPOWERINTLR When 1 the ICEPick logic remains powered at all times RW 0 POR When 0 the ICEPick logic may be powered down in the Test Logic Reset state if ICEPick is visible and TMS is 1 6 BLOCKSYSRESET When1 the device system reset signal is blocked RW 0 ARST 5 TDOALWAYSOUT When 1 the device level TDO pin will always be driven in output RW 0 POR mode regardless of the TAP state When 0 the device ...

Page 3602: ...y Selected 10 Reserved Acts like Stay Selected 11 Auto deselect When a selected secondary TAP becomes inaccessible due to power constraints all secondary TAPs are deselected TDO is forced to Hiz Table 27 21 TAPLINKMODE Values Value Mode Behavior 000 Always first The ICEPick TAP always exists and is linked as the TAP closest to TDI 001 Reserved Reserved behaves like Always first 010 Key Sequence Wh...

Page 3603: ...condary Debug TAP Register SDTR for each secondary TAP j 0 to 15 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAP_ROUTING CLOCK POWER RESERVED TAPPOWER VISIBLETAP SELECTTAP DEBUGMODE TAPPRESENT BLOCKNTRST INHIBITSLEEP FORCEACTIVE FORCEPOWER DEBUGENABLE RESETCONTROL TAPACCESSIBLE UNNATURALRESET DEBUGANDEXECUTE CLOCKDOWNDESIRED POWERDOWNDESIRED POWERL...

Page 3604: ...ify the debug mode of the module upon power on reset RW 0 ARST See Table 27 25 10 DEBUGANDEXECUTE Read 0 all processors modules on this secondary TAP are in RW 0 ARST execution state Read 1 one or more processors modules on this secondary TAP have entered a state where debugger interaction is required Writing a 1 enables the module to take action on a preloaded execution command such as run This b...

Page 3605: ...1xx Cancel Cancels reset command lockout Table 27 25 DEBUGMODE Values Value Debug Mode Description 00 Default mode The processor will use whatever debug mode is its default mode 01 Monitor mode The debug features of the processor will be configured for monitor mode 10 Halt mode The debug feature of the processor will be configured for halt or stop mode 11 Real time halt mode The debug features of ...

Page 3606: ...eld 31 28 0x2 block 2 is Debug TAP Linking Control REGISTER bit field 27 24 TAP number select the TAP to be added to the chain see Table 27 2 for more information DEBUGENABLE bit 13 1 enable the TAP debug DEBUGMODE bit field 12 11 MODE see Table 27 25 for available debug modes 8 Read back the value in next DR scan WRITE bit 32 0 BLOCK bit field 31 28 0x2 block 2 is Debug TAP Linking Control REGIST...

Page 3607: ...sk entry procedures calls system status test signatures and memory allocation 256 message channels which can be allocated between software components are available Messages are exported to trace receivers through a serial interface SDTI has its own local dedicated first in first out FIFO buffering to allow trace capabilities concurrent to ETM trace captured in ETB SDTI implements only trace export...

Page 3608: ...IG 4 SINGLEEDGE bit Serial interface operates in clock stop regime the serial clock is not free running when there is no trace data there is no trace clock 27 3 2 1 SDTI Pins Configuration Mode Figure 27 9 through Figure 27 11 show the SDTI connected with an emulator box in four two and one data pin configuration respectively The number of pins used for transmission can be configured inthe SDTI_SC...

Page 3609: ...ure 27 12 Dual Edge Clock Waveform Figure 27 13 shows the SDTI single edge serial interface waveform Figure 27 13 Single Edge Clock Waveform The SDTI serial interface is configurable to support one two and four data bits operation Depending on the configuration trace data is exported on sdti_txd 0 sdti_txd 1 0 or sdti_txd 3 0 Serial clock frequency is selected in the SDTI serial configuration regi...

Page 3610: ...d Data DD 00 DD 01 DD 10 Da 7 0 Da 15 8 Da 31 24 Da 23 16 Da 7 0 Da 15 8 Da 7 0 Table 27 29 CPU1 Message Description Format Header 010D DA00 Address A 1 A 0 Ad 7 0 Nonexistent field Data DD 00 DD 01 DD 10 Da 7 0 Da 15 8 Da 31 24 Da 23 16 Da 7 0 Da 15 8 Da 7 0 Table 27 30 CPU2 Timestamped Message Description Format Header 011D DA00 Timestamp 0 Address A 1 A 0 Ad 7 0 Nonexistent field Data DD 00 DD ...

Page 3611: ... divider Divider factors for serial clock generation are referenced to SDTI_ICLK These factors range from 1 to 10 SDTI_FCLK always has an internal clock that runs twice as fast as the serial clock selected through division factors which is used as a base clock in dual edge serial transmitters 27 3 3 1 2 Reset The SDTI is reset with hardware POR All SDTI registers are asynchronously reset The SDTI ...

Page 3612: ...debugger Ownership is required to configure or program the SDTI Ownership determines whether write access is granted to the SDTI configuration registers SDTI resource ownership is exclusive Hence simultaneous use of SDTI resources by both debugger and application is not permitted However the debugger can forcibly seize ownership of SDTI resources NOTE Read access does not require ownership therefo...

Page 3613: ...aim command is successful only if the unit is available or the requester is the debugger and the SDTI_WINCTRL 29 DEBUGGEROVERRIDE bit is high 10 Enable unit Activate the SDTI for use The enable command is accepted only from the owner 11 No operation The NOP command does not affect ownership or claim state 27 3 4 2 3 Claim Bits The 4 claim bits are implemented in the SDTI_WINCTRL register as shown ...

Page 3614: ...2 timestamped message When there is a write in that range SDTI hardware decodes the access and stores the address decoded as channel CPU1 2 and message timestamped message along with the data and access size The message header is determined from the accessed address and access type 1 2 or 4 bytes Trace matching for CPU1 and CPU2 message generation can be globally enabled or disabled in the SDTI_WI...

Page 3615: ...the SDTI FIFO stalls L4_EMU by not acknowledging the write access When FIFO room becomes available the SDTI can capture a new message The SDTI FIFO status can be polled by reading the SDTI_SYSSTATUS 8 FIFOEMPTY bit FIFOEMPTY reflects the state of SDTI buffering including the SDTI FIFO and serial interface shift register When read as 1 there is no more data in the SDTI to be exported Check the SDTI...

Page 3616: ...he patterns generated Table 27 37 Walking Test Pattern Interface Width Bits Pattern 1 0 1 2 00 01 10 4 0x0 0x1 0x2 0x4 0x8 27 3 4 5 3 Ramp Pattern The ramp pattern can be used to verify that no data is lost at the trace receiver The ramp pattern generator is implemented as a 4 bit up counter 27 3 4 5 4 Pseudo Random LFSR Pattern The linear feedback shift register LFSR pattern can be used to verify...

Page 3617: ...ial Interface Clock Generation The sdti_clk is derived from SDTI_FCLK with a programmable clock divider controlled by the SDTI_SCONFIG 3 0 SDTISCLKRATE bit field Table 27 38 shows the divider for the value of the SDTI_SCONFIG 3 0 SDTISCLKRATE bit field Table 27 38 sdti_clk Divider Value SDTISCLKRATE Value Division Value 0x0 Division by 1 0x1 Division by 1 0x2 Division by 2 0x3 Division by 3 0x4 Di...

Page 3618: ...FF CPU1 timestamped message 134 0x86400 0x867FF CPU2 message 0 0x00800 0x00BFF CPU2 timestamped message 0 0x00C00 0x00FFF CPU2 message 51 0x33800 0x33BFF CPU2 timestamped message 255 0xFFC00 0xFFFFF 27 3 4 9 SDTI Error Handling The SDTI port returns the in band error as a response in the following cases Unsupported master command Unsupported byte enable Unaligned address Application write access t...

Page 3619: ... change in the interface configuration the programming model is 1 Disable trace 2 Wait until SDTI FIFO is drained 3 Enable trace and thus start a new session This ensures that the first message in the new session is always exported with the address field In case of a short disable enable sequence when trace is re enabled while data from a previous session are still in the SDTI FIFO session breaks ...

Page 3620: ...m status register R No ownership 0x024 SDTI_WINCTRL SDTI window control register R W Has to be claimed 0x028 SDTI_SCONFIG SDTI serial configuration register R W Same owner as for SDTI_WINCTRL 0x02C SDTI_TESTCTRL SDTI test control register R W Same owner as for SDTI_WINCTRL CoreSight Management Registers 0xF00 INT_MODE_CTRL_REG Integration mode control register R W No ownership 0xF04 INT_OUTPUT_REG...

Page 3621: ...MODE_CTRL_REG RW 32 0x0000 0F00 0x5450 0F00 INT_OUTPUT_REG RW 32 0x0000 0F04 0x5450 0F04 INT_INPUT_REG RW 32 0x0000 0F08 0x5450 0F08 CLAIM_TAG_SET_REG RW 32 0x0000 0FA0 0x5450 0FA0 CLAIM_TAG_CLEAR_REG RW 32 0x0000 0FA4 0x5450 0FA4 LOCK_ACCESS_REG W 32 0x0000 0FB0 0x5450 0FB0 LOCK_STATUS_REG R 32 0x0000 0FB4 0x5450 0FB4 AUTHENTICATION_STATUS R 32 0x0000 0FB8 0x5450 0FB8 DEVICE_ID R 32 0x0000 0FC8 0...

Page 3622: ...hip 0 SDTI Register Manual SDTI Register Summary 1 Table 27 46 SDTI_SYSCONFIG Address Offset 0x0000 0010 Physical Address Instance SDTI See Table 27 43 Description This register allows controlling various parameters of the OCP interface Software reset have the same effect as hardware power on reset This register is excluded from erroneous application access lock protection in order to allow standa...

Page 3623: ...ED FIFOEMPTY RESETDONE Bits Field Name Description Type Reset 31 9 RESERVED RFU for module specific status information R 0x000000 8 FIFOEMPTY SDTI FIFO not Empty something to export R 1 SDTI FIFO Empty Write access has no effect 7 1 RESERVED RFU for OCP socket status information R 0x00 Read 0x0 Internal module reset in on going Read 0x1 Reset completed 0 RESETDONE Internal Module reset monitoring ...

Page 3624: ...l be granted regardless of current ownership status of the unit When written with DebuggerOverride 0 the claim request shall be granted only if the unit is available 28 CURRENTOWNER This value reflects the SDTI ownership when the register RW 0 is in a non Available state 0 Debugger owns resource 1 Application owns resource 27 3 RESERVED RFU R 0x0000000 2 DEBUGGERTRACEEN 0 Debugger writes to addres...

Page 3625: ...l edge operation mode RW 0 1 Single edge operation mode 3 0 SDTISCLKRATE 0x0 Division by 1 RW 0x1 0x1 Division by 1 0x2 Division by 2 0x3 Division by 3 0x4 Division by 4 0x5 Division by 5 0x6 Division by 6 0x7 Division by 7 0x8 Division by 8 0x9 Division by 9 0xA Division by 10 Others Division by 1 Table 27 53 Register Call Summary for Register SDTI_SCONFIG SDTI Environment SDTI Environment 0 SDTI...

Page 3626: ...ce messages RW 0 functional mode 1 SDTI serial interface exports selected test patterns test mode Table 27 55 Register Call Summary for Register SDTI_TESTCTRL SDTI Basic Programming Model Serial interface test mode setup 0 SDTI Register List Ownership 1 SDTI Register Manual SDTI Register Summary 2 Table 27 56 INT_MODE_CTRL_REG Address Offset 0x0000 0F00 Physical Address Instance SDTI See Table 27 ...

Page 3627: ...Name Description Type Reset 31 28 RESERVED RFU R 0x0 27 16 NUMOUTPUTS This field shall indicate the number of output terminals on R 0x005 the component 15 13 RESERVED RFU R 0x0 12 INTEGEN When IntegEn 1 the integration output is set to 1 RW 1 11 0 OUTBITSELECT This field shall selects the output bit to set high RW 0x000 Table 27 59 Register Call Summary for Register INT_OUTPUT_REG SDTI Functional ...

Page 3628: ...ce Normally the lower 4 bits are used for claiming and releasing debug components but SDTI implements a more sophisticated Claim mechanism These bits can be used for software semaphores to help manage the debug resources although the claim and enable mechanism of the SDTI resources must still be used Writing a 1 to one of the set bits will cause the corresponding bit in the Claim Tag Value word to...

Page 3629: ... Call Summary for Register CLAIM_TAG_CLEAR_REG SDTI Functional Description CoreSight Integration Mode 0 SDTI Basic Programming Model SDTI Register List Ownership 1 SDTI Register Manual SDTI Register Summary 2 Table 27 66 LOCK_ACCESS_REG Address Offset 0x0000 0FB0 Physical Address Instance SDTI See Table 27 43 Description Note This 32 bit write only register is used to lockout errant accesses by ap...

Page 3630: ...ng write access to the SDTI registers Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED EIGTBITLOCK LOCKSTATUS LOCKIMPLEMENTED Bits Field Name Description Type Reset 31 3 RESERVED RFU R 0x0000 0000 2 EIGTBITLOCK 0 indicates a 32 bit Lock Access Register R 0 1 indicates an 8 bit Lock Access Register 1 LOCKSTATUS 0 indicates unlocked condition R 1 ...

Page 3631: ...shall return 00 R 0x0 ATUS functionality not implemented 3 2 NONSECURE_NONINVASIVE_ The Non Secure Non Invasive Debug Status shall return R 0x0 DEBUGSTATUS 00 functionality not implemented 1 0 NONSECURE_INVASIVE_DEBU The Non Secure Invasive Debug Status shall return R 0x0 GSTATUS 00 functionality not implemented Table 27 71 Register Call Summary for Register AUTHENTICATION_STATUS SDTI Basic Progra...

Page 3632: ...e type register Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DEVICETYPE Bits Field Name Description Type Reset 31 8 RESERVED RFU R 0x000000 7 0 DEVICETYPE The device type shall return 0x63 Enables devices to be R 0x63 identified as to their CoreSight Class Table 27 75 Register Call Summary for Register DEVICE_TYPE_REG SDTI Basic Programming ...

Page 3633: ...RAL_ID5 Address Offset 0x0000 0FD4 Physical Address Instance SDTI See Table 27 43 Description All Peripheral ID registers are implemented as 8 bit registers with the upper 24 bits returning a value of zero Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED Bits Field Name Description Type Reset 31 8 RESERVED RFU RW 0x000000 7 0 RESERVED ...

Page 3634: ...st Ownership 0 SDTI Register Manual SDTI Register Summary 1 Table 27 82 PERIPHERAL_ID7 Address Offset 0x0000 0FDC Physical Address Instance SDTI See Table 27 43 Description All Peripheral ID registers are implemented as 8 bit registers with the upper 24 bits returning a value of zero Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED Bits...

Page 3635: ...gister Manual SDTI Register Summary 1 Table 27 86 PERIPHERAL_ID1 Address Offset 0x0000 0FE4 Physical Address Instance SDTI See Table 27 43 Description All Peripheral ID registers are implemented as 8 bit registers with the upper 24 bits returning a value of zero Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED JEP106IDCODE PARTNUMBER1 Bits Field...

Page 3636: ...DCODE JEP106 identity code 6 4 R 0x1 Table 27 89 Register Call Summary for Register PERIPHERAL_ID2 SDTI Basic Programming Model SDTI Register List Ownership 0 SDTI Register Manual SDTI Register Summary 1 Table 27 90 PERIPHERAL_ID3 Address Offset 0x0000 0FEC Physical Address Instance SDTI See Table 27 43 Description All Peripheral ID registers are implemented as 8 bit registers with the upper 24 bi...

Page 3637: ...l Summary for Register COMPONENT_ID0 SDTI Basic Programming Model SDTI Register List Ownership 0 SDTI Register Manual SDTI Register Summary 1 Table 27 94 COMPONENT_ID1 Address Offset 0x0000 0FF4 Physical Address Instance SDTI See Table 27 43 Description All Component ID registers are implemented as 8 bit registers with the upper 24 bits returning a value of zero These registers are used to indicat...

Page 3638: ...List Ownership 0 SDTI Register Manual SDTI Register Summary 1 Table 27 98 COMPONENT_ID3 Address Offset 0x0000 0FFC Physical Address Instance SDTI See Table 27 43 Description All Component ID registers are implemented as 8 bit registers with the upper 24 bits returning a value of zero These registers are used to indicate to software the existence of a peripheral Software will read the last four loc...

Page 3639: ...each pin This allows supporting concurrent debug features provided that pin mapping does not conflict The device EPM can be programmed from the application or debugger software A claim mechanism ensures exclusive ownership However the debugger can override the ownership state The debug port is mapped on top of a set of application pins The device platforms provide the application software with the...

Page 3640: ... by the DAPC_EPM1 19 16 DBGP12 bit field Table 27 100 lists the different modes supported for each pin and the bit field that controls the output mode 3640 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3641: ... O etk_d0 etk_d0 O etk_d0 O etk_ctl etk_ctl O etk_ctl O etk_clk etk_clk O etk_clk O DBGP1 jtag_emu1 emu1 IO O sdti_txd0 3 O sdti_txd1 3 O sdti_txd0 O 3 DBGP0 jtag_emu0 emu0 IO O sdti_clk 1 O sdti_txd0 1 O sdti_clk O 1 1 Two SDTI pins can be mapped to the same etk_ SDTI_CLK selects the sdti_clk pin and SDTI_DATA selects the sdti_txd data pin 2 To map the uart1_rx pin configuration must be done on t...

Page 3642: ...y defined by the EPM CONTROL 0 setup The jtag_emu1 debug signal routing depends on the debug function mapped to jtag_emu1 and the debug signal routed to jtag_emu0 The etk_clk debug signal routing depends on the debug function mapped to etk_clk and the debug signals routed to jtag_emu0 and jtag_emu The etk_ctl debug signal routing depends on the debug function mapped to etk_ctl and the debug signal...

Page 3643: ...e EPM has not been claimed Claimed 01 The EPM has been claimed Enabled 10 The EPM is enabled by the owning party Reserved 11 Reserved If the EPM is in a nonavailable state the DAPC_EPM2 31 30 CLAIMOWNERSHIP bit field 01 or 10 the current owner can be read in the DAPC_EPM2 28 CLAIMCURRENTOWNER bit To change claim ownership state write a command in the DAPC_EPM2 31 30 CLAIMOWNERSHIP bit field Table ...

Page 3644: ...Table 27 107 SDTI Single Pin Data Clock ETM16 EMU Pin Debug Mode Debug Signal Routing EPM Control Field EPM Control Value jtag_emu0 SDTI Clock sdti_clk DBGP0 1000 jtag_emu1 SDTI Data sdti_txd0 DBGP1 0111 etk_clk Trace ETM etk_clk DBGP2 DBGP12 DBGP 19 15 1000 etk_ctl Trace ETM etk_ctl etk_d 15 0 Trace ETM etk_d 15 0 Table 27 108 Trigger HS RTDX ETM8 SDTI 4 Pin Data Clock Dedicated Port EMU Pin Debu...

Page 3645: ...k_d 7 0 Trace ETM etk_d 7 0 etk_d 10 8 None etk_d 11 SDTI Trace clock sdti_clk DBGP15 1000 etk_d 13 12 None etk_d 15 14 SDTI Trace data sdti_txd 3 2 DBGP 19 18 0111 27 4 5 EPM Register Manual Table 27 111 summarizes the EPM instance Table 27 111 EPM Instance Summary Module Name SIMCOP Base Address Size EPM 0x0000 0800 32 bytes 27 4 5 1 EPM Register Summary Table 27 112 is the EPM register mapping ...

Page 3646: ... Multiplexing 0 1 EPM Register Manual EPM Register Manual 2 Table 27 115 DAPC_EPM1 Address Offset 0x054 Physical address 0x5401 D054 Instance DAPC_EPM Description Emulation pin manager register 1 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBGP15 RESERVED DBGP12 RESERVED Bits Field Name Description Type Reset 31 28 DBGP15 TRACEDATA 11 pin control R...

Page 3647: ... This qualifier bit is used with the debugger s CLAIM request When written with DebuggerOverride 1 a claim request by the debugger is granted regardless of current ownership status of the unit When written with DebuggerOverride 0 the claim request is granted only if the unit is available 28 CLAIMCURRENTOWNER This value reflects the unit ownership when the register is R 0 in a non Available state 0...

Page 3649: ...ge Signal Processor 3663 A 6 Display Subsystem 3665 A 7 Interconnect 3667 A 8 Memory Subsystem 3670 A 9 sDMA 3671 A 10 Interrupt Controller 3673 A 11 System Control Module 3676 A 12 Multimaster High Speed I2 C Controller 3689 A 13 UART IrDA CIR 3690 A 14 Multichannel SPI 3692 A 15 Multichannel Buffered Serial Port 3693 A 16 High Speed USB Host Subsystem 3695 A 17 General Purpose Interface 3696 A 1...

Page 3650: ...n the display subsystem Asynchronous Die To Die AD2D interface Universal asynchronous receiver transmitter 4 UART4 Multichannel buffered serial port 4 McBSP4 Multichannel serial peripheral interface 1 McSPI1 Multimaster high speed HS inter integrated circuit controller 3 I2C3 HDQ 1 Wire interface module A 1 2 2 Functionality Restrictions The following subsystems and modules have their full functio...

Page 3651: ...pin mcbsp1_clkr thus cannot be configured in Slave Transmit Master Receive mode or in Master Transmit Slave Receive mode HS multiport USB host port 3 is not accessible General purpose input output GPIO A number of GPIO channels are not available due to missing associated pins All die pads that are not connected to any pins on the OMAP36xx in CYN package devices are shown highlighted in Section B 5...

Page 3652: ...ilbox Serial camera Parallel I2C4 USB ISP Public Version Memory Mapping www ti com Figure A 1 OMAP36xx in CYN Package Block Diagram A 2 Memory Mapping NOTE This subsection provides a quick reference about the unavailable modules and their memory mapping Cells highlighted in orange in the tables indicate modules with removed functionality in the OMAP36xx in CYN package devices These modules are sti...

Page 3653: ...tiator port agent configuration HS USB OTG IA 0x6800 4400 0x6800 47FF 1 HS USB OTG initiator port agent configuration Reserved 0x6800 4800 0x6800 4BFF 1 Reserved sDMA RD IA 0x6800 4C00 0x6800 4FFF 1 sDMA RD initiator port agent configuration sDMA WR IA 0x6800 5000 0x6800 53FF 1 sDMA WR initiator port agent configuration Display subsystem IA 0x6800 5400 0x6800 57FF 1 Display subsystem initiator por...

Page 3654: ...00 2FFF 4KB Module 0x4800 3000 0x4800 3FFF 4KB L4 interconnect Clock manager 0x4800 4000 0x4800 5FFF 8KB Module region A DPLL 0x4800 6000 0x4800 67FF 2KB Module region B Clock manager 0x4800 6800 0x4800 6FFF 2KB Reserved 0x4800 7000 0x4800 7FFF 4KB L4 interconnect Reserved 0x4800 8000 0x4802 3FFF 112KB Reserved Reserved 0x4802 4000 0x4802 4FFF 4KB Reserved 0x4802 5000 0x4802 5FFF 4KB Reserved Rese...

Page 3655: ...7 5000 0x4807 5FFF 4KB L4 interconnect Reserved 0x4807 6000 0x4808 5FFF 64KB Reserved GPTIMER10 0x4808 6000 0x4808 6FFF 4KB Module 0x4808 7000 0x4808 7FFF 4KB L4 interconnect GPTIMER11 0x4808 8000 0x4808 8FFF 4KB Module 0x4808 9000 0x4808 9FFF 4KB L4 interconnect Reserved 0x4808 A000 0x4808 AFFF 4KB Reserved 0x4808 B000 0x4808 BFFF 4KB Reserved Reserved 0x4808 C000 0x4809 3FFF 32KB Reserved Mailbo...

Page 3656: ...0x480C DFFF 4KB Module chassis mode only 0x480C E000 0x480C EFFF 4KB L4 interconnect Reserved 0x480C F000 0x482F FFFF 2208KB Reserved L4 Wakeup interconnect region A 0x4830 0000 0x4830 9FFF 40KB Nonshared device mapping Control module ID code 0x4830 A000 0x4830 AFFF 4KB See Section A 2 2 2 2 0x4830 B000 0x4830 BFFF 4KB L4 interconnect L4 Wakeup interconnect region B 0x4830 C000 0x4833 FFFF 208KB S...

Page 3657: ...2000 0x4903 2FFF 4KB Module 0x4903 3000 0x4903 3FFF 4KB L4 interconnect GPTIMER3 0x4903 4000 0x4903 4FFF 4KB Module 0x4903 5000 0x4903 5FFF 4KB L4 interconnect GPTIMER4 0x4903 6000 0x4903 6FFF 4KB Module 0x4903 7000 0x4903 7FFF 4KB L4 interconnect GPTIMER5 0x4903 8000 0x4903 8FFF 4KB Module 0x4903 9000 0x4903 9FFF 4KB L4 interconnect GPTIMER6 0x4903 A000 0x4903 AFFF 4KB Module 0x4903 B000 0x4903 B...

Page 3658: ...y Signal sys_xtalout of the built in high speed oscillator intended to drive a quartz crystal clock master mode is not supported Clock output sys_clkout1 cannot be used to supply external devices with clock clock master mode is not supported sys_altclk clock input for PLLs NTSC standard 54 MHz and USB full speed FS controller 48 MHz is not supported Figure A 2 shows the external clock signals of t...

Page 3659: ...ription section in the Power Reset and Clock Management chapter of the OMAP36xx TRM All unsupported modules and functionality are listed in Section A 1 Introduction Interface clocks must not be related to the domain state transitions See the PRCM Clock Manager Functional Description section in the Power Reset and Clock Management chapter of the OMAP36xx TRM All unsupported modules and functionalit...

Page 3660: ...ved Reserved D_DMA_17 Reserved Reserved D_DMA_18 Reserved Reserved D_DMA_19 Reserved Reserved A 4 2 2 Interrupt Requests The IVA2 2 subsystem manages three types of interrupts Internal interrupts Requests generated by modules in the IVA2 2 subsystem or in the DSP megamodule included in the IVA2 2 subsystem External interrupts Requests generated by peripherals external to the IVA2 2 subsystem like ...

Page 3661: ...A internal N A N A 45 50 Reserved IVA2_IRQ 0 5 N A Reserved 51 GPT5_IRQ IVA2_IRQ 6 GPTIMER5 General purpose timer module 5 52 GPT6_IRQ IVA2_IRQ 7 GPTIMER6 General purpose timer module 6 53 GPT7_IRQ IVA2_IRQ 8 GPTIMER7 General purpose timer module 7 54 GPT8_IRQ IVA2_IRQ 9 GPTIMER8 General purpose timer module 8 55 MAIL_U1_IVA2_IRQ IVA2_IRQ 10 Mailbox Mailbox user 1 interrupt request 56 CAM_IRQ1 IVA...

Page 3662: ... internal DSP INT CTL Dropped CPU interrupt event 97 EMC_IDMAERR N A internal EMC Invalid IDMA parameters 98 Reserved N A internal Reserved Reserved 99 Reserved N A internal N A N A 100 EFIINTA N A internal EFI EFI interrupt from side A 101 EFIINTB N A internal EFI EFI interrupt from side B 102 112 Reserved N A internal N A N A 113 EMC_ED N A internal DSP PMC Single bit error detected during DMA r...

Page 3663: ...ble at device boundary thus is not operational in the OMAP36xx in CYN package devices Camera parallel interface CPI is not supported in the OMAP36xx in CYN package devices because it shares common pins with CSIPHY1 Some of dedicated to CPI pins are also not present Generation of signal for strobe flash cam_strobe cannot be output Table A 7 describes the camera subsystem functions and the correspon...

Page 3664: ...lly configurable pair strobe or data positive or negative ccpv2_dy1 I Serial CSI CCP2B mode Fully configurable pair strobe or data positive or negative cam_xclka O External clock for the image sensor module cam_xclkb O External clock for the image sensor module A 5 3 Camera ISP Functional Description Following modules are present in the camera subsystem but are not functional in the OMAP36xx in CY...

Page 3665: ...e kept disabled see Section 6 5 Camera ISP Basic Programming Model in Chapter 6 Camera Image Signal Processor The CSIPHY2 complex I O must be configured in D PHY mode from the control module SCM CONTROL_CAMERA_PHY_CTRL 1 0 R_CONTROL_CAMERA2_PHY_CAMMODE must be set to 0x0 see Chapter 6 Camera Image Signal Processor and Chapter 13 System Control Module A 6 Display Subsystem A 6 1 Display Subsystem O...

Page 3666: ...elds Table A 9 Display Subsystem I O Pins Pin name I O Description Reset Value dss_pclk O LCD pixel clock when in parallel mode 0 dss_hsync O LCD horizontal synchronization when in parallel mode 0 dss_vsync O LCD vertical synchronization when in parallel mode 0 dss_acbias O AC bias control STN or pixel data enable TFT output in when 0 parallel mode dss_data 23 0 I O LCD pixel data bus when in para...

Page 3667: ...delines The DISPC digital video encoder data path must be kept disabled DIGITALENABLE of DISPC_CONTROL 1 0x0 Moreover to avoid current leakage the following bits must be set to 0 DSS DSS_CONTROL 5 DAC_POWERDN_BGZ VENC_OUTPUT_CONTROL 2 0 PRCM CM_FCLKEN_DSS 2 EN_TV CONTROL CONTROL_DEVCONF 18 TVOUTBYPASS A 7 Interconnect NOTE This subsection provides a quick reference about the unavailable modules in...

Page 3668: ...ERA subsystem Camera subsystem port SAD2D Die to die port sDMA read System DMA read port sDMA write System DMA write port HS USB OTG Universal serial bus high speed port OTG controller HS USB Host Universal serial bus high speed port host controller DAP Debug access port JTAG emulation access to system resources 1 Modules highlighted in orange are present on the die but cannot be used with the OMA...

Page 3669: ...ial port 1 McBSP5 Multichannel buffered serial port 5 GPTIMER10 General purpose timer 10 GPTIMER11 General purpose timer 11 MMC1 Multimedia memory controller SDIO 1 MMC2 Multimedia memory controller SDIO 2 MMC3 Multimedia memory controller SDIO 3 HDQ 1 Wire Single wire serial link low rate MLB Mailbox Mailbox MCSPI1 Serial peripheral interface 1 MCSPI2 Serial peripheral interface 2 MCSPI3 Serial p...

Page 3670: ...owing signals are supported by the GPMC but are unaccessible outside the OMAP36xx in CYN package devices Six chip select signals CS1 through CS6 With two CSs total GPMC address space is 512 Mbytes 2 x 256 Mbytes Three wait signals WAIT1 through WAIT3 NOTE Cells highlighted in orange in Table B 2 GPMC I O Description indicate signals with no dedicated pins in OMAP36xx in CYN package devices Table B...

Page 3671: ...ty in the OMAP36xx in CYN package devices These modules are still present on the die therefore their mappings are provided to control their activity and for debug purposes A 9 1 sDMA Environment The external DMA requests sys_ndmareq0 and sys_ndmareq1 are supported by the SDMA controller but are unaccessible outside the OMAP36xx in CYN package devices The sDMA controller supports external DMA reque...

Page 3672: ...ule 3 transmit request S_DMA_25 I2C3_DMA_RX I2 C module 3 receive request S_DMA_26 I2C1_DMA_TX I2 C module 1 transmit request S_DMA_27 I2C1_DMA_RX I2 C module 1 receive request S_DMA_28 I2C2_DMA_TX I2 C module 2 transmit request S_DMA_29 I2C2_DMA_RX I2 C module 2 receive request S_DMA_30 MCBSP1_DMA_TX MCBSP module 1 transmit request S_DMA_31 MCBSP1_DMA_RX MCBSP module 1 receive request S_DMA_32 MC...

Page 3673: ...dule 4 transmit request channel 0 S_DMA_70 SPI4_DMA_RX0 McSPI module 4 receive request channel 0 S_DMA_71 DSS_DMA0 Display subsystem DMA request 0 DSI S_DMA_72 DSS_DMA1 Display subsystem DMA request 1 DSI S_DMA_73 DSS_DMA2 Display subsystem DMA request 2 DSI S_DMA_74 DSS_DMA3 Display subsystem DMA request 3 DSI or RFBI S_DMA_75 Reserved Reserved S_DMA_76 MMC3_DMA_TX MMC SD3 transmit request S_DMA_...

Page 3674: ...IRQ_5 MCBSP3_ST_IRQ Sidetone MCBSP3 overflow M_IRQ_6 Reserved Reserved M_IRQ_7 sys_nirq External source active low M_IRQ_8 Reserved Reserved M_IRQ_9 SMX_DBG_IRQ L3 interconnect error for debug M_IRQ_10 SMX_APP_IRQ L3 interconnect error for application M_IRQ_11 PRCM_MPU_IRQ PRCM module IRQ M_IRQ_12 Reserved Reserved 3 M_IRQ_13 Reserved Reserved 3 M_IRQ_14 SDMA_IRQ_2 System DMA request 2 M_IRQ_15 SD...

Page 3675: ...ed Reserved M_IRQ_50 Reserved Reserved M_IRQ_51 Reserved Reserved M_IRQ_52 Reserved Reserved M_IRQ_53 Reserved Reserved 4 M_IRQ_54 MCBSP4_IRQ_TX McBSP module 4 transmit 4 M_IRQ_55 MCBSP4_IRQ_RX McBSP module 4 receive 4 M_IRQ_56 I2C1_IRQ I2 C module 1 M_IRQ_57 I2C2_IRQ I2 C module 2 M_IRQ_58 HDQ_IRQ HDQ 1 Wire M_IRQ_59 McBSP1_IRQ_TX McBSP module 1 transmit 4 M_IRQ_60 McBSP1_IRQ_RX McBSP module 1 re...

Page 3676: ...sked reset default state See the Interrupt Controller Functional Description section in the Interrupt Controller chapter of the OMAP36xx TRM A 11 System Control Module NOTE This subsection provides a quick reference about the device pads that are not connected to any pin Cells highlighted in orange in the tables indicate pads with removed functionality in the OMAP36xx in CYN package devices These ...

Page 3677: ...ists the pad configuration registers instantiated in the CORE power domain that drive the pads in the CORE power domain Table B 8 lists the pad configuration registers instantiated in the WKUP power domain that drive the pads in the WKUP power domain All rows highlighted in orange in the tables Table B 7 and Table B 8 represent the unconnected to any pin pads on device die The coressponding PADCON...

Page 3678: ...4C sdrc_d14 CONTROL_PADCONF_SDRC_D14 31 16 0x4800 204C sdrc_d15 CONTROL_PADCONF_SDRC_D16 15 0 0x4800 2050 sdrc_d16 CONTROL_PADCONF_SDRC_D16 31 16 0x4800 2050 sdrc_d17 CONTROL_PADCONF_SDRC_D18 15 0 0x4800 2054 sdrc_d18 CONTROL_PADCONF_SDRC_D18 31 16 0x4800 2054 sdrc_d19 CONTROL_PADCONF_SDRC_D20 15 0 0x4800 2058 sdrc_d20 CONTROL_PADCONF_SDRC_D20 31 16 0x4800 2058 sdrc_d21 CONTROL_PADCONF_SDRC_D22 15...

Page 3679: ...PADCONF_GPMC_A10 31 16 0x4800 208C gpmc_d0 CONTROL_PADCONF_GPMC_D1 15 0 0x4800 2090 gpmc_d1 CONTROL_PADCONF_GPMC_D1 31 16 0x4800 2090 gpmc_d2 CONTROL_PADCONF_GPMC_D3 15 0 0x4800 2094 gpmc_d3 CONTROL_PADCONF_GPMC_D3 31 16 0x4800 2094 gpmc_d4 CONTROL_PADCONF_GPMC_D5 15 0 0x4800 2098 gpmc_d5 CONTROL_PADCONF_GPMC_D5 31 16 0x4800 2098 gpmc_d6 CONTROL_PADCONF_GPMC_D7 15 0 0x4800 209C gpmc_d7 CONTROL_PAD...

Page 3680: ...DCONF_GPMC_NBE1 31 16 0x4800 20C8 gpmc_nwp gpio_62 safe_mode CONTROL_PADCONF_GPMC_WAIT0 15 0 0x4800 20CC gpmc_wait0 CONTROL_PADCONF_GPMC_WAIT0 31 16 0x4800 20CC gpmc_wait1 gpio_63 safe_mode CONTROL_PADCONF_GPMC_WAIT2 15 0 0x4800 20D0 gpmc_wait2 uart4_tx gpio_64 safe_mode CONTROL_PADCONF_GPMC_WAIT2 31 16 0x4800 20D0 gpmc_wait3 sys_ndmar uart4_rx gpio_65 safe_mode eq1 CONTROL_PADCONF_DSS_PCLK 15 0 0...

Page 3681: ...0x4800 20FC dss_data17 gpio_87 safe_mode CONTROL_PADCONF_DSS_DATA18 15 0 0x4800 2100 dss_data18 mcspi3_clk dss_data0 gpio_88 safe_mode CONTROL_PADCONF_DSS_DATA18 31 16 0x4800 2100 dss_data19 mcspi3_sim dss_data1 gpio_89 safe_mode o CONTROL_PADCONF_DSS_DATA20 15 0 0x4800 2104 dss_data20 mcspi3_so dss_data2 gpio_90 safe_mode mi CONTROL_PADCONF_DSS_DATA20 31 16 0x4800 2104 dss_data21 mcspi3_cs0 dss_d...

Page 3682: ..._PADCONF_CSI2_DX0 31 16 0x4800 2134 csi2_dy0 gpio_113 safe_mode CONTROL_PADCONF_CSI2_DX1 15 0 0x4800 2138 csi2_dx1 gpio_114 safe_mode CONTROL_PADCONF_CSI2_DX1 31 16 0x4800 2138 csi2_dy1 gpio_115 safe_mode CONTROL_PADCONF_MCBSP2_FSX 15 0 0x4800 213C mcbsp2_fsx gpio_116 safe_mode CONTROL_PADCONF_MCBSP2_FSX 31 16 0x4800 213C mcbsp2_clk gpio_117 safe_mode x CONTROL_PADCONF_MCBSP2_DR 15 0 0x4800 2140 m...

Page 3683: ...3_tll_ safe_mode data4 CONTROL_PADCONF_MCBSP3_DX 31 16 0x4800 216C mcbsp3_dr uart2_rts gpio_141 hsusb3_tll_ safe_mode data5 CONTROL_PADCONF_MCBSP3_CLKX 15 0 0x4800 2170 mcbsp3_clk uart2_tx gpio_142 hsusb3_tll_ safe_mode x data6 CONTROL_PADCONF_MCBSP3_CLKX 31 16 0x4800 2170 mcbsp3_fsx uart2_rx gpio_143 hsusb3_tll_ safe_mode data7 CONTROL_PADCONF_UART2_CTS 15 0 0x4800 2174 uart2_cts mcbsp3_dx gpt_9_...

Page 3684: ...fsx gpio_161 safe_mode CONTROL_PADCONF_MCBSP1_CLKX 15 0 0x4800 2198 mcbsp1_clk mcbsp3_clk gpio_162 safe_mode x x CONTROL_PADCONF_MCBSP1_CLKX 31 16 0x4800 2198 uart3_cts_r gpio_163 safe_mode ctx CONTROL_PADCONF_UART3_RTS_SD 15 0 0x4800 219C uart3_rts_s gpio_164 safe_mode d CONTROL_PADCONF_UART3_RTS_SD 31 16 0x4800 219C uart3_rx_irr gpio_165 safe_mode x CONTROL_PADCONF_UART3_TX_IRTX 15 0 0x4800 21A0...

Page 3685: ...L_PADCONF_MCSPI1_CLK 31 16 0x4800 21C8 mcspi1_sim sdmmc2_d gpio_172 safe_mode o at5 CONTROL_PADCONF_MCSPI1_SOMI 15 0 0x4800 21CC mcspi1_so sdmmc2_d gpio_173 safe_mode mi at6 CONTROL_PADCONF_MCSPI1_SOMI 31 16 0x4800 21CC mcspi1_cs0 sdmmc2_d gpio_174 safe_mode at7 CONTROL_PADCONF_MCSPI1_CS1 15 0 0x4800 21D0 mcspi1_cs1 sdmmc3_c gpio_175 safe_mode md CONTROL_PADCONF_MCSPI1_CS1 31 16 0x4800 21D0 mcspi1...

Page 3686: ...ADCONF_SDRC_A6 15 0 0x4800 25B0 sdrc_a6 CONTROL_PADCONF_SDRC_A6 31 16 0x4800 25B0 sdrc_a7 CONTROL_PADCONF_SDRC_A8 15 0 0x4800 25B4 sdrc_a8 CONTROL_PADCONF_SDRC_A8 31 16 0x4800 25B4 sdrc_a9 CONTROL_PADCONF_SDRC_A10 15 0 0x4800 25B8 sdrc_a10 CONTROL_PADCONF_SDRC_A10 31 16 0x4800 25B8 sdrc_a11 CONTROL_PADCONF_SDRC_A12 15 0 0x4800 25BC sdrc_a12 CONTROL_PADCONF_SDRC_A12 31 16 0x4800 25BC sdrc_a13 CONTR...

Page 3687: ...ata4 CONTROL_PADCONF_ETK_D4 31 16 0x4800 25E4 etk_d5 mcbsp5_fsx sdmmc3_d hsusb1_dat gpio_19 hsusb1_tll_ hw_dbg7 at1 a5 data5 CONTROL_PADCONF_ETK_D6 15 0 0x4800 25E8 etk_d6 mcbsp5_dx sdmmc3_d hsusb1_dat gpio_20 hsusb1_tll_ hw_dbg8 at2 a6 data6 CONTROL_PADCONF_ETK_D6 31 16 0x4800 25E8 etk_d7 mcspi3_cs1 sdmmc3_d hsusb1_dat gpio_21 mm1_txen_ hsusb1_tll_ hw_dbg9 at7 a3 n data3 CONTROL_PADCONF_ETK_D8 15...

Page 3688: ... CONTROL_PADCONF_SYS_BOOT3 15 0 0x4800 2A10 sys_boot3 dss_data20 gpio_5 safe_mode CONTROL_PADCONF_SYS_BOOT3 31 16 0x4800 2A10 sys_boot4 Reserved Reserved Reserved safe_mode CONTROL_PADCONF_SYS_BOOT5 15 0 0x4800 2A14 sys_boot5 sdmmc2_di dss_data22 gpio_7 safe_mode r_dat3 CONTROL_PADCONF_SYS_BOOT5 31 16 0x4800 2A14 sys_boot6 Reserved Reserved safe_mode CONTROL_PADCONF_SYS_OFF_MODE 15 0 0x4800 2A18 s...

Page 3689: ...ller The device supports three multimaster high speed HS inter integrated circuit I2 C controllers I2Ci where i 1 2 or 4 Each HS I2 C controller can be configured to act like a slave or master I2 C compatible device Moreover each HS I2 C controller can be configured in serial camera control bus SCCB mode to act as a master on a 2 wire SCCB bus Three wire SCCB bus is not supported The HS I2 C4 cont...

Page 3690: ...le is still present on the die therefore its mappings are provided to control its activity and for debug purposes Table A 24 HS I2 C Instance Summary Module Name Base Address Size I2C1 0x4807 0000 512 bytes I2C2 0x4807 2000 512 bytes I2C3 0x4806 0000 512 bytes A 12 1 HS I2 C Use Guidelines For the unsupported I2C3 module next guidelines must be followed Keep I2C_SYSC 4 3 IDLEMODE 0x0 Keep I2C_SYSC...

Page 3691: ...ial data output 1 1 I Input O Output Table B 4 lists the base address and address space for the UART IrDA CIR module instances in the OMAP36xx in CYN package devices NOTE Modules highlighted in orange in Table B 4 has removed functionality in the OMAP36xx in CYN package devices The module is still present on the die therefore its mappings are provided to control its activity and for debug purposes...

Page 3692: ...SPI2 module serial data slave input HiZ master output spi2_somi I O 1 SPI2 module serial data slave output HiZ master input spi2_cs0 I O 1 SPI2 module chip select 0 HiZ spi2_cs1 O SPI2 module chip select 1 0 spi3_clk I O 1 SPI3 module serial clock 2 HiZ spi3_simo I O 1 SPI3 module serial data slave input HiZ master output spi3_somi I O 1 SPI3 module serial data slave output HiZ master input spi3_c...

Page 3693: ... CYN package devices McBSP4 module mcbsp_clks pin external clock input shared by all McBSP modules McBSP1 modes Transmit master and receive slave mode Transmit slave and receive master mode A 15 2 McBSP Environment A 15 2 1 McBSP Signal Descriptions The four McBSP modules consist of a data flow path and a control path connected to external devices by a serial interface with 4 pin configuration Tab...

Page 3694: ...MAP36xx in CYN package devices mcbsp1_clkr must be used instead of mcbsp1_clkx Data are transmitted to external devices interfacing with McBSP modules through the mcbspi_dx pin Data from those devices are received on the mcbspi_dr pin Control information is communicated through the following pins mcbspi_clkx transmit clock mcbsp1_clkr receive clock mcbspi_fsx transmit frame sync and mcbsp1_fsr rec...

Page 3695: ...CLKG clock which in turn must be routed to the transmitter CLKX_int clock OMAP36xx TRM Clocking and Framing Data and McBSP SRG functional description subsections in the Multichannel Buffered Serial Port chapter provide basic concept for the McBSP data clocking and framing McBSP Basic Programming Model section in the OMAP36xx TRM describes the McBSP and SRG intialization A 16 High Speed USB Host Su...

Page 3696: ...general purpose interface supports up to 192 6 x 32 channels Not all channels can be used in the OMAP36xx in CYN package devices The total capability of the OMAP36xx in CYN package devices is 143 GPIO channels mapped on external pins and 1 channel used internally The actual number of external channels varies in function of the device configuration A 17 2 General Purpose Interface Environment Table...

Page 3697: ...9 gpio_ 108 105 Not available on external pins 15 13 I O gpio_ 111 109 Yes 3 GPIO 2 19 16 I gpio_ 115 112 Yes 3 GPI 2 29 20 I O gpio_ 125 116 Yes 3 GPIO 2 30 gpio_126 Not available on external pins 31 gpio_127 Not available on external pins I TSHUT Yes 3 Internal TSHUT signal from the BANDGAP module for the SRAMs LDOs 4 GPIO5 1 0 gpio_ 129 128 Not available on external pins 15 2 I O gpio_ 143 130 ...

Page 3698: ...criptor field product ID equal to 0xD00E TI default value for product ID string descriptor equal to OMAP3630 A 18 2 Preinitialization A 18 2 1 Power Connections Table A 32 describes the power supply pins for the OMAP36xx in CYN package devices The pins highlighted in orange are not available on the OMAP36xx in CYN package Table A 32 OMAP36xx in CYN Package Power Pins Device Voltage Pin Name Descri...

Page 3699: ...nnection to a quarz crystal is not supported sys_clkreq is always an output Only sys_clkout2 can output the system clock 12 13 16 8 19 2 26 or 38 4 MHz the core clock CORE DPLL output 96 MHz or 54 MHz sys_clkout1 is not supported A 18 4 Boot Configuration The OMAP36xx in CYN package boot configurations are compatible with the OMAP36xx in a full featured package with the following differences sys_b...

Page 3700: ...h Fifth 0b0000 OneNAND USB UART3 1 MMC1 0b0001 MMC2 USB UART3 1 MMC1 0b0010 MMC1 USB UART3 1 0b0011 XIP UART3 1 0b0100 XIPwait DOC UART3 1 0b0101 NAND UART3 1 0b0110 OneNAND UART3 1 0b0111 MMC2 UART3 1 0b1000 MMC1 UART3 1 0b1001 XIP USB 0b1010 XIPwait DOC USB 0b1011 NAND USB 0b1100 MMC2_H USB UART3 1 0b1101 Reserved 2 0b1110 0b1111 Fast external boot 2 1 UART3 boot is not supported in OMAP36xx in ...

Page 3701: ...ble A 35 Booting Configuration Pins After a Warm Reset sys_boot 4 0 Booting Sequence When SYS BOOT 5 0 Booting Sequence When SYS BOOT 5 1 Memory Preferred Booting Order Peripheral Preferred Booting Order First Second First Second 0b0000 OneNAND OneNAND 0b0001 MMC2 MMC2 0b0010 MMC1 MMC1 0b0011 XIP XIP 0b0100 XIPwait DOC XIPwait DOC 0b0101 NAND NAND 0b0110 OneNAND OneNAND 0b0111 MMC2 MMC2 0b1000 MMC...

Page 3703: ...multimedia device offered in the s PBGA N423 CUS package Topic Page B 1 Overview 3704 B 2 Description 3704 B 3 Unsupported Modules 3704 B 4 Functional Restrictions 3705 B 5 Control Module Pad Multiplexing Register Fields 3711 3703 SWPU177N December 2009 Revised November 2010 OMAP36xx Multimedia Device in CUS Package Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3704: ...itch CUS does not support the package on package POP concept and some of the pads are not available As a consequence there are features in the OMAP36xx device that are restricted or not supported Stacked mode is not supported Some of the functions offered in the die are not available Some of the functions offered in the die are restricted CAUTION Because all modules are still present on the die th...

Page 3705: ... O 1 Primary Function cam_hs I O Line trigger I O signal cam_vs I O Frame trigger I O signal cam_fld I O Field identification I O signal cam_pclk I Parallel interface pixel clock cam_d 11 0 I Parallel mode input data bits 0 to 11 cam_wen I External write enable signal cam_strobe O Flash strobe control signal csi2_dx0 I Serial CSI2 mode Fully configurable pair csi2_dy0 I Serial CSI2 mode Fully conf...

Page 3706: ...mc_ncs4 O Chip select active low gpmc_ncs5 O Chip select active low gpmc_ncs6 O Chip select active low gpmc_ncs7 O Chip select active low gpmc_clk I O Clock 2 gpmc_nadv_ale O Address valid active low Also used as address latch enable active high for NAND protocol memories gpmc_noe_nre O Output enable active low Also used as read enable active low for NAND protocol memories gpmc_nwe O Write enable ...

Page 3707: ...rt2_rts O Request to send 1 uart3_rx_irrx I Serial data input IR and remote RX HiZ uart3_tx_irtx O Serial data output IR TX 1 uart3_cts_rctx I O Clear to send input remote TX output 1 uart3_rts_sd O Request to send IR enable 1 uart4_rx I Serial data input HiZ uart4_tx O Serial data output 1 1 I Input O Output Table B 4 lists the base address and address space for the UART IrDA CIR module instances...

Page 3708: ...ut HiZ master output spi2_somi I O 2 SPI2 module serial data slave output HiZ master input spi2_cs0 I O 2 SPI2 module CS0 HiZ spi2_cs1 O SPI2 module CS1 0 spi3_clk I O 2 SPI3 module serial clock 3 HiZ spi3_simo I O 2 SPI3 module serial data slave input HiZ master output spi3_somi I O 2 SPI3 module serial data slave output HiZ master input spi3_cs0 I O 2 SPI3 module CS0 HiZ spi3_cs1 O SPI3 module C...

Page 3709: ...al balls 30 22 I O gpio_ 62 54 Yes 3 GPIO 2 31 gpio_63 No Not available on external balls GPIO3 0 gpio_64 No Not available on external balls 31 1 I O gpio_ 95 65 Yes 3 GPIO 2 GPIO4 15 0 I O gpio_ 111 96 Yes 3 GPIO 2 19 16 gpio_ 115 112 No Not available on external balls 30 20 I O gpio_ 126 116 Yes 3 GPIO 2 31 gpio_127 No Not available on external balls I TSHUT Yes 3 Internal TSHUT signal from the ...

Page 3710: ...ins cannot be used to generate a direct wake up event because they are connected to the device I O pad logic in the CORE power domain VDD2 When the CORE power domain is off the VDD2 supplied I O pins of GPIO1 cannot generate a wake up event 3710 OMAP36xx Multimedia Device in CUS Package SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...

Page 3711: ...stem Control Module NOTE Pad configuration registers are split into two types which correspond to the following two tables Table B 7 lists the pad configuration registers instantiated in the CORE power domain that drive the pads in the CORE power domain Table B 8 lists the pad configuration registers instantiated in the WKUP power domain that drive the pads in the WKUP power domain The rows highli...

Page 3712: ...sdrc_d13 CONTROL_PADCONF_SDRC_D14 15 0 0x4800 204C sdrc_d14 CONTROL_PADCONF_SDRC_D14 31 16 0x4800 204C sdrc_d15 CONTROL_PADCONF_SDRC_D16 15 0 0x4800 2050 sdrc_d16 CONTROL_PADCONF_SDRC_D16 31 16 0x4800 2050 sdrc_d17 CONTROL_PADCONF_SDRC_D18 15 0 0x4800 2054 sdrc_d18 CONTROL_PADCONF_SDRC_D18 31 16 0x4800 2054 sdrc_d19 CONTROL_PADCONF_SDRC_D20 15 0 0x4800 2058 sdrc_d20 CONTROL_PADCONF_SDRC_D20 31 16 ...

Page 3713: ...ndmar gpio_42 safe_mode eq2 CONTROL_PADCONF_GPMC_A10 15 0 0x4800 208C gpmc_a10 sys_ndmar gpio_43 safe_mode eq3 CONTROL_PADCONF_GPMC_A10 31 16 0x4800 208C gpmc_d0 CONTROL_PADCONF_GPMC_D1 15 0 0x4800 2090 gpmc_d1 CONTROL_PADCONF_GPMC_D1 31 16 0x4800 2090 gpmc_d2 CONTROL_PADCONF_GPMC_D3 15 0 0x4800 2094 gpmc_d3 CONTROL_PADCONF_GPMC_D3 31 16 0x4800 2094 gpmc_d4 CONTROL_PADCONF_GPMC_D5 15 0 0x4800 2098...

Page 3714: ...CONF_GPMC_NWE 15 0 0x4800 20C4 gpmc_nwe CONTROL_PADCONF_GPMC_NWE 31 16 0x4800 20C4 gpmc_nbe0 gpio_60 safe_mode _cle CONTROL_PADCONF_GPMC_NBE1 15 0 0x4800 20C8 gpmc_nbe1 gpio_61 safe_mode CONTROL_PADCONF_GPMC_NBE1 31 16 0x4800 20C8 gpmc_nwp gpio_62 safe_mode CONTROL_PADCONF_GPMC_WAIT0 15 0 0x4800 20CC gpmc_wait0 CONTROL_PADCONF_GPMC_WAIT0 31 16 0x4800 20CC gpmc_wait1 gpio_63 safe_mode CONTROL_PADCO...

Page 3715: ...mode CONTROL_PADCONF_DSS_DATA12 31 16 0x4800 20F4 dss_data13 gpio_83 safe_mode CONTROL_PADCONF_DSS_DATA14 15 0 0x4800 20F8 dss_data14 gpio_84 safe_mode CONTROL_PADCONF_DSS_DATA14 31 16 0x4800 20F8 dss_data15 gpio_85 safe_mode CONTROL_PADCONF_DSS_DATA16 15 0 0x4800 20FC dss_data16 gpio_86 safe_mode CONTROL_PADCONF_DSS_DATA16 31 16 0x4800 20FC dss_data17 gpio_87 safe_mode CONTROL_PADCONF_DSS_DATA18 ...

Page 3716: ...cam_d10 Reserved gpio_109 hw_dbg8 safe_mode CONTROL_PADCONF_CAM_D11 15 0 0x4800 212C cam_d11 gpio_110 hw_dbg9 safe_mode CONTROL_PADCONF_CAM_D11 31 16 0x4800 212C cam_xclkb gpio_111 safe_mode CONTROL_PADCONF_CAM_WEN 15 0 0x4800 2130 cam_wen cam_shutte gpio_167 hw_dbg10 safe_mode r CONTROL_PADCONF_CAM_WEN 31 16 0x4800 2130 cam_strobe gpio_126 hw_dbg11 safe_mode CONTROL_PADCONF_CSI2_DX0 15 0 0x4800 2...

Page 3717: ...5 0 0x4800 2164 sdmmc2_d sdmmc2_di sdmmc3_d gpio_136 safe_mode at4 r_dat0 at0 CONTROL_PADCONF_MMC2_DAT4 31 16 0x4800 2164 sdmmc2_d sdmmc2_di cam_global sdmmc3_d gpio_137 hsusb3_tll_ mm3_rxdp safe_mode at5 r_dat1 _reset at1 stp CONTROL_PADCONF_MMC2_DAT6 15 0 0x4800 2168 sdmmc2_d sdmmc2_di cam_shutte sdmmc3_d gpio_138 hsusb3_tll_ safe_mode at6 r_cmd r at2 dir CONTROL_PADCONF_MMC2_DAT6 31 16 0x4800 2...

Page 3718: ... 15 0 0x4800 2188 mcbsp4_dx Reserved gpio_154 hsusb3_tll_ mm3_txdat safe_mode data2 CONTROL_PADCONF_MCBSP4_DX 31 16 0x4800 2188 mcbsp4_fsx Reserved gpio_155 hsusb3_tll_ mm3_txen_ safe_mode data3 n CONTROL_PADCONF_MCBSP1_CLKR 15 0 0x4800 218C mcbsp1_clk mcspi4_clk Reserved gpio_156 safe_mode r CONTROL_PADCONF_MCBSP1_CLKR 31 16 0x4800 218C mcbsp1_fsr cam_global gpio_157 safe_mode _reset CONTROL_PADC...

Page 3719: ...ode a3 ctx CONTROL_PADCONF_HSUSB0_DATA3 31 16 0x4800 21B0 hsusb0_dat gpio_188 safe_mode a4 CONTROL_PADCONF_HSUSB0_DATA5 15 0 0x4800 21B4 hsusb0_dat gpio_189 safe_mode a5 CONTROL_PADCONF_HSUSB0_DATA5 31 16 0x4800 21B4 hsusb0_dat gpio_190 safe_mode a6 CONTROL_PADCONF_HSUSB0_DATA7 15 0 0x4800 21B8 hsusb0_dat gpio_191 safe_mode a7 CONTROL_PADCONF_HSUSB0_DATA7 31 16 0x4800 21B8 i2c1_scl CONTROL_PADCONF...

Page 3720: ...at gpio_181 safe_mode m_evt data6 a6 CONTROL_PADCONF_MCSPI2_CS0 31 16 0x4800 21DC mcspi2_cs1 gpt_8_pwm hsusb2_tll_ hsusb2_dat gpio_182 mm2_txen_ safe_mode _evt data3 a3 n CONTROL_PADCONF_SYS_NIRQ 15 0 0x4800 21E0 sys_nirq gpio_0 safe_mode CONTROL_PADCONF_SYS_NIRQ 31 16 0x4800 21E0 sys_clkout2 gpio_186 safe_mode CONTROL_PADCONF_SAD2D_SBUSFLAG 31 16 0x4800 2260 sdrc_cke0 safe_mode _out1 1 CONTROL_PA...

Page 3721: ...DCONF_SDRC_DM1 31 16 0x4800 25D0 sdrc_dm2 CONTROL_PADCONF_SDRC_DM3 15 0 0x4800 25D4 sdrc_dm3 CONTROL_PADCONF_SDRC_DM3 31 16 0x4800 25D4 CONTROL_PADCONF_ETK_CLK 15 0 0x4800 25D8 etk_clk mcbsp5_clk sdmmc3_cl hsusb1_stp gpio_12 mm1_rxdp hsusb1_tll_ hw_dbg0 x k stp CONTROL_PADCONF_ETK_CLK 31 16 0x4800 25D8 etk_ctl sdmmc3_c hsusb1_clk gpio_13 hsusb1_tll_ hw_dbg1 md clk CONTROL_PADCONF_ETK_D0 15 0 0x480...

Page 3722: ... etk_d12 Reserved hsusb2_dir gpio_26 hsusb2_tll_ hw_dbg14 for non GP dir devices CONTROL_PADCONF_ETK_D12 31 16 0x4800 25F4 etk_d13 hsusb2_nxt gpio_27 mm2_rxdm hsusb2_tll_ hw_dbg15 nxt CONTROL_PADCONF_ETK_D14 15 0 0x4800 25F8 etk_d14 hsusb2_dat gpio_28 mm2_rxrcv hsusb2_tll_ hw_dbg16 a0 data0 CONTROL_PADCONF_ETK_D14 31 16 0x4800 25F8 etk_d15 hsusb2_dat gpio_29 mm2_txse0 hsusb2_tll_ hw_dbg17 a1 data1...

Page 3723: ...ode CONTROL_PADCONF_JTAG_NTRST 15 0 0x4800 2A1C jtag_ntrst CONTROL_PADCONF_JTAG_NTRST 31 16 0x4800 2A1C jtag_tck CONTROL_PADCONF_JTAG_TMS_TMSC 15 0 0x4800 2A20 jtag_tms_t msc CONTROL_PADCONF_JTAG_TMS_TMSC 31 16 0x4800 2A20 jtag_tdi CONTROL_PADCONF_JTAG_EMU0 15 0 0x4800 2A24 jtag_emu0 gpio_11 safe_mode CONTROL_PADCONF_JTAG_EMU0 31 16 0x4800 2A24 jtag_emu1 gpio_31 safe_mode CONTROL_PADCONF_CHASSIS_S...

Page 3725: ...egister arithmetic unit ARGB Alpha red green blue ASIC Application specific integrated circuit A chip built for a specific application In the context of this document ASIC refers to the FPGA that resides on the EVM board ASCII American standard code for information ATR Answer to reset AVC Advanced video coding MPEG4 Part 10 also known as H264 AXI Advanced extensible interface B BB Busy bus BCD Bin...

Page 3726: ... data rate of 30 fps with each frame containing 288 lines and 352 pixels per line CLE Command latch enable CLK Clock CLUT Color look up table CMOS Complementary metal oxide semiconductor CMT Cellular mobile telephone Codec Coder decoder or compression decompression A device that codes in one direction of transmission and decodes in another direction of transmission ConnID Connection identifier An ...

Page 3727: ...ssor contends for and receives mastery of the memory bus so that data transfers can occur independent of the host DMC Data memory controller DPD DPDM Deep power down mode DPF Dynamic power framework DPI Display parallel interface Digital implementation of PLL DPLL Digital phase locked loop DRD Dual role device DRDY Data ready DRM Digital rights management DSI Display serial interface DSP Digital s...

Page 3728: ...rder they were put in A FIFO is useful for buffering a stream of data between a sender and receiver which are not synchronized that is the sender and receiver are not sending and receiving at exactly the same rate If the rates differ by too much in one direction for too long the FIFO becomes either full blocking the sender or empty blocking the receiver FIQ Fast interrupt request FlatLink 3G A Tex...

Page 3729: ...data transfer I2S Inter IC sound A digital audio interface standard IA Initiator agent also Identifier address IC Integrated circuit ICR Intersystem communication registers IF Interface INT Interrupt A signal sent by hardware or software to a processor requesting attention An interrupt tells the processor to suspend its current operation save the current task status and perform a particular set of...

Page 3730: ...ems designed around complex integrated circuits and assembled with surface mount technologies The group drafted a standard that was subsequently adopted by IEEE as IEEE Standard 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architecture K Kb Kilobits KB Kilobyte 1024 B Kbps Kilobits per second L L1 Level 1 cache memory L2 Level 2 cache memory L3 First level of interconnect in OMAP p...

Page 3731: ...dia card secure data MMU Memory management unit The MMU performs virtual to physical address translations performs access permission checks for access to the system memory and provides the flexibility and protection required for the OS to manage a shared physical memory space between the two processors MPEG Motion Pictures Expert Group A compression scheme for full motion video MPEG1 The first MPE...

Page 3732: ...GL Open GL programming API enable OHCI Open host controller interface This is an industry standard USB host controller interface OMAP An open software and hardware platform targeted at second and third generation cellular phones with multimedia capabilities OneNand A memory chip based on NAND architecture integrating SRAM buffers and NOR logic interface It combines the advanced data storage functi...

Page 3733: ...ter selection PRCM Power reset and clock management PRM Power and reset manager PS Packet start PSA Parallel signature analyzer PT Packet type PVT Process voltage and temperature that is PVT dispersion PWB Printed wiring board PWM Pulse width modulation PWR Power Q QCIF Quarter common intermediate format A video conferencing format that specifies data rates of 30 fps with each frame containing 144...

Page 3734: ...deo SCCB Serial camera control interface 3 wire and 2 wire serial bus defined and deployed by Omnivision Technologies Inc SCL Serial clock Programmable serial clock used in the I2 C interface Also SCLK SCM Scan combiner module also statistic collection module SCP Serial configuration port SD Starting delimiter SDA Serial data Serial data bus in the I2 C interface SDI Serial display interface SDIO ...

Page 3735: ...which a single serial bus is shared by multiple devices with each device taking turns to communicate on the bus The total number of time slots channels depends on the number of devices connected During a time slot a given device may talk to any combination of devices on the bus TFT Thin film transistor A type of LCD flat panel display screen in which each pixel is controlled by one to four transis...

Page 3736: ...es UTMI USB 2 0 transceiver macrocell interface UTMI UTMI extension supporting USB host and on the go V VA Volt amps A form of power management A VA rating is the volts rating multiplied by the amps current rating used to indicate the output capacity of an uninterruptible power supply UPS or other power source VC Virtual channel VENC Video encoder VESA Video Electronics Standards Association VFP V...

Page 3737: ...DT Watchdog timer WLAN Wireless local area network WMV Windows media video WMA Windows media audio Word16 16 bit word Word32 32 bit word WP Write protect WSS Wide screen signaling WWT Work waiting time X XGA XVGA Extended graphics array XIP Execution in place Y YUV Luminance Bandwidth Chrominance 3737 SWPU177N December 2009 Revised November 2010 Glossary Copyright 2009 2010 Texas Instruments Incor...

Page 3738: ...ch statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications o...

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