Set the receive
frame-sync mode
Set the receive
frame-sync polarity
Set the SRG frame-sync
period and pulse width
END
C
C
Set the
receive clock mode
Set the
receive clock polarity
Set the SRG
clock divide-down value
Set the SRG clock
synchronization mode
Set the SRG
imput clock polarity
Set the SRG clock mode
(choose an input clock)
Frame-sync Behavior
C
lo
ck
Be
h
a
vio
r
B
mcbsp-064
Public Version
www.ti.com
McBSP Basic Programming Model
Figure 21-61. Important Tasks to Configure the McBSP Receiver (Part 2)
21.5.1.5.2.1 Global Behavior
21.5.1.5.2.1.1 Set the Receiver Pins to Operate as McBSP Pins
The McBSPi.
[12] RIOEN bit determines whether the receiver pins are McBSP pins
(RIOEN bit=0) or general–purpose I/O pins (RIOEN bit=1).
See
which describes how to use McBSP pins as GPIO pins.
21.5.1.5.2.1.2 Enable/Disable the Digital Loop Back Mode
The McBSPi.
[5] DLB bit determines whether the digital loopback mode is on or
off.
In the digital loopback mode, the receive signals are connected internally through multiplexers to the
corresponding transmit signals:
•
DR signal is connected on DX signal to receive the transmitted data
•
FSR is connected to FRX output signal
•
CLKR is connected to the CLKX output signal
This mode allows testing of serial port; the McBSP module receives the data it transmits. This loopback
mode is not done through pads, all output signals being disabled.
NOTE:
That in digital loopback mode the SRG and the frame synchronization generator need to be
enabled to generate the CLKX and FSX signals.
3135
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated
