Texas Instruments OMAP36 Series, Technical Reference Manual

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McBSP Basic Programming Model
If the SRG creates a clock signal (CLKG) that is derived from an external input clock, the GSYNC bit
determines whether CLKG is kept synchronized with pulses on the mcbsp_fsr pin.
In the digital loopback mode (DLB=1) or analog loopback mode (ALB = 1), the transmit frame
synchronization signal is used as the receive frame synchronization signal. For more details on clock
configuration, see
Section 21.4.3.1 .
21.5.1.6.2.4.2 Set the Transmit Clock Polarity
The McBSPi. MCBSPLP_PCR_REG [1] CLKXP bit is used to set the transmit clock polarity.
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out
transmit data. Data is always transmitted on the rising edge of internal CLKX. If CLKXP=1 and external
clocking is selected (CLKXM=0 and CLKX is an input), the external falling–edge triggered input clock on
CLKX is inverted to a rising–edge triggered clock before being sent to the transmitter. If CLKXP=1 and
internal clocking is selected (CLKXM=1 and CLKX is an output pin), the internal (rising–edge triggered)
clock, internal CLKX, is inverted before being sent out on the mcbsp_clkx pin.
Similarly, the receiver can reliably sample data that is clocked with a rising edge clock (by the transmitter).
The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is
always sampled on the falling edge of internal CLKR. Therefore, if CLKRP=1 and external clocking is
selected (CLKRM=0 and CLKR is an input pin), the external rising–edge triggered input clock on CLKR is
inverted to a falling–edge triggered clock before being sent to the receiver. If CLKRP=1 and internal
clocking is selected (CLKRM=1), the internal falling–edge triggered clock is inverted to a rising–edge
triggered clock before being sent out on the mcbsp_clkr pin.
NOTE: CLKRP=CLKXP in a system where the same clock (internal or external) is used to clock the
receiver and transmitter. The receiver uses the opposite edge as the transmitter to ensure
valid setup and hold of data around this edge.
21.5.1.6.2.4.3 Set the SRG Clock Divide-Down Value
See Section 21.5.1.5.2.4.3 .
21.5.1.6.2.4.4 Set the SRG Clock Synchronization Mode
See Section 21.5.1.5.2.4.4 .
21.5.1.6.2.4.5 Set the SRG Clock Mode (Choose an Input Clock)
See Section 21.5.1.5.2.4.5 .
21.5.1.6.2.4.6 Set the SRG Input Clock Polarity
See Section 21.5.1.5.2.4.6 .
21.5.1.7 General-Purpose I/O on the McBSP Pins (Legacy Only)
Table 21-34 summarizes how to use the McBSP pins as general–purpose I/O pins. All the bits mentioned
in the table except XRST and RRST bits are in the pin control register (McBSPi. MCBSPLP_PCR_REG ).
McBSPi. MCBSPLP_SPCR2_REG [0] XRST bit and McBSPi. MCBSPLP_SPCR1_REG [0] RRST bit are in
the serial port control registers.
To use receiver pins mcbsp_clkr, mcbsp_fsr, and mcbsp_dr as general–purpose I/O pins rather than as
serial port pins, you must set two conditions:
1. The receiver of the serial port is in reset (McBSPi. MCBSPLP_SPCR1_REG [0] RRST bit =0).
2. General–purpose I/O is enabled for the serial port receiver (McBSPi. MCBSPLP_PCR_REG [12]
RIOEN=1).
3149 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
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