Texas Instruments OMAP36 Series, Technical Reference Manual

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CLK(R/X)
D(R/X)
Data delay 0
FS(R/X)
B7 B6 B5 B4 B3
D(R/X)
Data delay 1
B7 B6
B5 B4
D(R/X)
Data delay 2
B7 B6 B5
1-bit delay
2-bit delay
0-bit delay
mcbsp-056
CLK(R/X)
D(R/X)
FS(R/X)
Framing bit
B7 B6 B5
2-bit delay
mcbsp-057
Public Version
McBSP Basic Programming Model
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XDATDLY specifies the data delay for reception. The range of programmable data delay is zero to two
bit–clocks (XDATDLY=00b–10b), as shown in
Figure 21-68 . In this figure, the data transferred is an 8–bit
value with bits labeled B7, B6, B5, and so on.
NOTE: Typically a 1–bit delay is selected, because data often follows a 1–cycle active
frame-synchronization pulse.
Figure 21-68. Range of Programmable Data Delay
21.5.1.6.2.2.5.1 0-Bit Data Delay:
Normally, a frame-synchronization pulse is detected or sampled with respect to an edge of internal serial
clock CLK(R/X). Thus, on the following cycle or later (depending on the data delay value), data may be
received or transmitted. However, in the case of 0–bit data delay, the data must be ready for reception
and/or transmission on the same serial clock cycle.
For reception, this problem is solved because receive data is sampled on the first falling edge of CLKR
where an active–high internal FSR is detected. However, data transmission must begin on the rising edge
of the internal CLKX clock that generated the frame synchronization. Therefore, the first data bit is
assumed to be present in XSR1, and thus on mcbspi_dx. The transmitter then asynchronously detects the
frame-synchronization signal (FSX) going active high and immediately starts driving the first bit to be
transmitted on the mcbsp_dx pin.
21.5.1.6.2.2.5.2 2-Bit Data Delay:
A data delay of two bit periods allows the serial port to interface to different types of T1 framing devices
where the data stream is preceded by a framing bit. During reception of such a stream with data delay of
two bits (framing bit appears after a 1–bit delay and data appears after a 2–bit delay), the serial port
essentially discards the framing bit from the data stream, as shown in
Figure 21-69 . The data transferred
is an 8–bit value with bits labeled B7, B6, B5, and so on.
Figure 21-69. 2-Bit Data Delay Used to Skip a Framing Bit
21.5.1.6.2.2.6 Set the Transmit DXENA Mode
McBSPi. MCBSPLP_SPCR1_REG [7] DXENA bit is used to set the transmit DXENA (DX delay enable)
mode.
3146 Multi-Channel Buffered Serial Port SWPU177N – December 2009 – Revised November 2010
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