CLKR
DR
FSR
A1
B7
B6
B5
B4
B3
B2
B1
B0
A0
RRDY
C7
C6
C5
C4
C3
C2
C1
C0
RFULL
RB to DRR copy (A)
No read from DRR (A)
No read from DRR (B), RB full
Read from DRR (A)
RSR to RB copy (B)
mcbsp-037
CLKR
DR
FSR
A1
B7
B6
B5
B4
B3
B2
B1
B0
A0
RRDY
RSYNCERR
mcbsp-038
RB to DRR copy (A)
Read from DRR (A)
Unexpected frame synchronization
RB to DRR copy (B)
Read from DRR (B)
Public Version
McBSP Functional Description
www.ti.com
Figure 21-42. Overrun in the McBSP Receiver
21.4.4.3 Unexpected Receive Frame-sync Pulse
21.4.4.3.1 Possible Responses to Receive Frame-sync Pulses
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
received, this pulse is treated as an unexpected frame-synchronization pulse, and the receiver sets the
receive frame-synchronization error bit McBSPi.
[0] RSYNCERR (and the
legacy McBSPi.
[3] RSYNCERR bit).
According to the McBSPi.
register settings this condition can generate the
McBSPi_IRQ line to be asserted low. Writing 1 to the corresponding bit in
McBSPi.
register clears the interrupt.
Using the legacy mode, McBSPi.
[3] RSYNCERR bit can be cleared only by a
receiver reset or by writing 0 to this bit. If you want the McBSP module to notify the MPU/IVA2.2
subsystem of receive frame-synchronization errors, set the legacy mode receive interrupt with the
McBSPi.
[5:4] RINTM field. When RINTM = 0b11, the McBSP module sends a
receive interrupt (legacy mode) request to the MPU/IVA2.2 subsystems each time that RSYNCERR is set.
21.4.4.3.2 Example of an Unexpected Receive Frame-sync Pulse
shows an unexpected receive frame-synchronization pulse during normal operation of the
serial port, with time intervals between data packets.
NOTE:
The unexpected receive frame-synchronization pulse does not influence the data receive
process, being ignored by the data receive state-machine.
Figure 21-43. Unexpected Frame-sync Pulse During a McBSP Reception
21.4.4.3.3 Preventing Unexpected Receive Frame-sync Pulses
Each frame transfer can be delayed by 0, 1, or 2 CLKR cycles, depending on the value of the
McBSPi.
[1:0] RDATDLY field. For each possible data delay,
shows
when a new frame-synchronization pulse on FSR can safely occur relative to the last bit of the current
frame.
3110
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated