Texas Instruments OMAP36 Series, Technical Reference Manual

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Table 13-83. CONTROL_PADCONF_CAPABILITIES (continued)
REGISTER NAME Pad name Physical address WakeUpx Off Mode Input Reserved PU/PD MuxMode
Enable
CONTROL_PADCONF_SAD2D_DMAREQ2[31:16] chassis_dmareq 0x48002240 -- 0b00000 – 0b000 0b00 0b000
3
CONTROL_PADCONF_SAD2D_NTRST[15:0] chassis_ntrst 0x48002244 -- 0b00000 – 0b000 0b00 ---
CONTROL_PADCONF_SAD2D_NTRST[31:16] chassis_tdi 0x48002244 -- 0b00000 – 0b000 0b00 ---
CONTROL_PADCONF_SAD2D_TDO[15:0] chassis_tdo 0x48002248 -- 0b00000 0b1 0b000 0b01 ---
CONTROL_PADCONF_SAD2D_TDO[31:16] chassis_tms 0x48002248 -- 0b00000 – 0b000 0b00 ---
CONTROL_PADCONF_SAD2D_TCK[15:0] chassis_tck 0x4800224C -- 0b00000 – 0b000 0b00 ---
CONTROL_PADCONF_SAD2D_TCK[31:16] chassis_rtck 0x4800224C -- 0b00000 0b1 0b000 0b01 ---
CONTROL_PADCONF_SAD2D_MSTDBY[15:0] chassis_mstdby 0x48002250 0b00 0b00000 0b1 0b000 0b11 ---
CONTROL_PADCONF_SAD2D_MSTDBY[31:16] chassis_idlereq 0x48002250 -- 0b00000 – 0b000 0b00 ---
CONTROL_PADCONF_SAD2D_IDLEACK[15:0] chassis_idleack 0x48002254 -- 0b00000 0b1 0b000 0b11 ---
CONTROL_PADCONF_SAD2D_IDLEACK[31:16] sad2d_mwrite 0x48002254 -- 0b00000 0b1 0b000 0b01 0b000
CONTROL_PADCONF_SAD2D_SWRITE[15:0] sad2d_swrite 0x48002258 -- 0b00000 0b1 0b000 0b00 0b000
CONTROL_PADCONF_SAD2D_SWRITE[31:16] sad2d_mread 0x48002258 -- 0b00000 0b1 0b000 0b01 0b000
CONTROL_PADCONF_SAD2D_SREAD[15:0] sad2d_sread 0x4800225C -- 0b00000 0b1 0b000 0b00 0b000
CONTROL_PADCONF_SAD2D_SREAD[31:16] sad2d_mbusflag 0x4800225C -- 0b00000 0b1 0b000 0b01 0b000
CONTROL_PADCONF_SAD2D_SBUSFLAG[15:0] sad2d_sbusflag 0x48002260 -- 0b00000 – 0b000 0b00 0b000
CONTROL_PADCONF_SDRC_SBUSFLAG[31:16] sdrc_cke0 0x48002260 -- ----- – 0b000 0b00 0b111
CONTROL_PADCONF_SDRC_CKE1[15:0] sdrc_cke1 0x48002264 -- ----- – 0b000 0b00 0b111
CONTROL_PADCONF_SDRC_CKE1[31:16] gpmc_a11 0x48002264 0b00 0b00000 0b1 0b000 0b01 0b111
CONTROL_PADCONF_SDRC_BA0[15:0] sdrc_ba0 0x480025A0 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_BA0[31:16] sdrc_ba1 0x480025A0 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A0[15:0] sdrc_a0 0x480025A4 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A0[31:16] sdrc_a1 0x480025A4 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A2[15:0] sdrc_a2 0x480025A8 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A2[31:16] sdrc_a3 0x480025A8 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A4[15:0] sdrc_a4 0x480025AC -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A4[31:16] sdrc_a5 0x480025AC -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A6[15:0] sdrc_a6 0x480025B0 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A6[31:16] sdrc_a7 0x480025B0 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A8[15:0] sdrc_a8 0x480025B4 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A8[31:16] sdrc_a9 0x480025B4 -- ----- – 0b000 0b00 ---
CONTROL_PADCONF_SDRC_A10[15:0] sdrc_a10 0x480025B8 -- ----- – 0b000 0b00 ---
2565 SWPU177N – December 2009 – Revised November 2010 System Control Module
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