Texas Instruments OMAP36 Series, Technical Reference Manual

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Manual Mode
DSI_PLL_GO[0].DSI_PLL_GO bit set to 1 by software
Generate TINITZ, etc. Sequence PLL reprogrammed
Completed Clear DSI_PLL_GO[0] DSI_PLL_GO bit to 0
dss-182
Public Version
Display Subsystem Basic Programming Model
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7.5.5.3 DSI PLL Go Sequence
In Manual Mode (DSS. DSI_PLL_CONTROL [0] DSI_PLL_AUTOMODE bit set to 0), the DPLL requires a
sequence on TINITZ, TENABLE and TENABLEDIV to update the configuration values and start the
locking sequence.
Once all the configuration values have been programmed into the registers, the GO bit must be set. The
appropriate sequence should then be sent on the TINITZ, TENABLE, and TENABLEDIV pins, respecting
the timing requirements of the ADPLLM. The DSS.
DSI_PLL_GO [0] DSI_PLL_GO bit are cleared to 0 at
the end of the sequence.
Because the TENABLEDIV signal is shared with the HSDIVIDER module, it is programmed at the same
time. In this mode, software must deassert CLKINEN by unsetting the
DSS.
DSI_PLL_CONFIGURATION2 [14] DSI_PHY_CLKINEN to 0 and assert HSDIVBYPASS correctly by
setting the DSS. DSI_PLL_CONFIGURATION2 [20] DSI_HSDIVBYPASS bit to 1 to prevent uncontrolled
frequencies affecting the DSI_PHY and display subsystem during PLL locking. In manual mode the
shadow register must be updated anyway so that valid values are present when later selecting automatic
mode.
Figure 7-136 shows the DSI PLL Go flow chart in manual mode (DSS. DSI_PLL_CONTROL [0]
DSI_PLL_AUTOMODE bit set to 0).
Figure 7-136. DSI PLL Go Sequence (Manual Mode)
NOTE: All thick-outlined blocks show operations performed by software. Other blocks show operations performed
by hardware.
In automatic mode (DSS. DSI_PLL_CONTROL [0] DSI_PLL_AUTOMODE bit set to 1),the TINITZ,
TENABLE and TENABLEDIV sequence and the update of the PLL configuration from the
DSI_PLL_CONFIGURATION2 register are deferred until the time of the front porch time signal sent by the
DISPC module. This is intended to simplify the software to implement a configuration change (such as a
frequency change to support a different link bandwidth). In this mode CLKINEN, HSDIVBYPASS and
REFEN are controlled automatically and the register value is overridden.
Figure 7-137 shows the DSI PLL Go flow chart in automatic mode (DSS. DSI_PLL_CONTROL [0]
DSI_PLL_AUTOMODE bit set to 1).
1752 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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