dss-327
…(4)
LP state
LP state
HS_INTERLEAVING
BLANKING_PERIOD
Video
HS
packet
Video
HS
packet
LP state
Video
HS
packet
exit HS
mode
Command mode
HS packet
enter
HS
LP state
exit HS
mode
enter
HS
Command mode
HS packet
LP state
enter
HS
Command mode
HS packet
exit HS
mode
Video
HS
packet
exit HS
mode
Command mode
HS packet
LP state
enter
HS
…(1)
…(3)
…(2)
HS_INTERLEAVING
HS_INTERLEAVING
HS_INTERLEAVING
Public Version
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Display Subsystem Functional Description
Figure 7-91. HS Command Mode Interleaving
NOTE:
For calculations and equations, the following abbreviations are used: EXIT_CLK_HS_MODE
represents the exit HS mode latency for the clock lane. There is no dedicated register for this
value but the programmer must know this value for further calculations.
EXIT_CLK_HS_MODE = T
CLK-TRAIL
+ TH
S-EXIT
For the following equations, BLANKING_PERIOD represents the BLLP, HSA, HBP, or HFP blanking
periods. The HS_INTERLEAVING period represents the maximal period HS command mode packets. Its
value is set in the BL_HS_INTERLEAVING, HSA_HS_INTERLEAVING, HBP_HS_INTERLEAVING, or
HFP_HS_INTERLEAVING registers, depending on the blanking type.
In each scenario, two calculations are present, depending on the value of ddr_clk_always_on.
•
ddr_clk_always_on = 1: Clock lane is always active.
•
ddr_clk_always_on = 0: Clock lane is activated only when there are HS packets to be sent on the PPI
link.
•
Scenario 1: The gap for interleaving starts and ends with a regular video stream HS packet.
–
ddr_clk_always_on = 1
HS_INTERLEAVING = BLANKING_PERIOD – (EXIT_HS_MODE_L max{
ENTER_HS_MODE_LATENCY, 2} + 1)
–
ddr_clk_always_on = 0
HS_INTER1 = BLANKING_PERIOD – (EXIT_HS_MODE_L max{
ENTER_HS_MODE_LATENCY, 2} + 1)
1667
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
