Texas Instruments OMAP36 Series, Technical Reference Manual

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mpu-008
MPU clock generator
PRCM
ARM Cortex-A8
Emulation/
trace/debug
EMU
DPLL
ICECrusher
Local interconnect
INTC
Cortex-A8 MPU subsystem
AXI_FCLK
INTC_FCLK
ICECRUSHER_FCLK
ARM_FCLK
EMU_CLOCKS
MPU_CLK
MPU_DPLL
(DPLL1)
Reference
clock
Bypass
clock
Reference
clock
Device
Hardware
divider of 2
Hardware
divider of 2
Hardware
divider of 2
Hardware
divider of 1
Public Version
www.ti.com
MPU Subsystem Integration
4.2.1 MPU Subsystem Clock and Reset Distribution
4.2.1.1 Clock Distribution
The MPU subsystem includes a clock generator block that supplies clocks for the modules in the MPU
subsystem. It is fed by the MPU_CLK clock from the PRCM module.
All major modules in the MPU subsystem are clocked at half the frequency of the ARM core. The divider
of the output clock can be programmed with the PRCM.CM_CLKSEL2_PLL_MPU[4:0]
MPU_DPLL_CLKOUT_DIV bit field; the frequency is relative to the ARM core. For details, see
Chapter 3 ,
Power, Reset, and Clock Management. The clock generator generates the following functional clocks:
• ARM (ARM_FCLK): This is the core clock. It is the base fast clock that is routed internally to the ARM
logic and internal RAMs, including NEON, L2 cache, the ETM core (emulation), and the ARM core. It
runs at the frequency of the MPU_CLK when DPLL1 is locked, and runs as the frequency of the
bypass clock when DPLL1 is bypassed.
• Local interconnect clock (AXI_FCLK): This clock is half the frequency of the MPU clock
(MPU_CLK). The L3 interconnect interface thus performs at one half the frequency of the MPU.
• Interrupt Controller Functional Clock (MPU_INTC_FCLK): This clock, which is part of the INTC
module, is half the frequency of the MPU clock (MPU_CLK).
• ICECrusher™ Functional Clock (ICECRUSHER_FCLK): ICECrusher clocking operates on the APB
interface, using the ARM core clocking. For details, see the Emulation TRM.
Emulation Clocking: Except for the ICECrusher functional clock, which is provided by the MPU DLL, the
emulation modules inside the MPU subsystem are not generated by the MPU subsystem DPLL, but by an
EMU DPLL. These clocks (EMU_CLOCKS) are distributed by the device PRCM module, are
asynchronous to the ARM core clock (ARM_FCLK) and can run at a maximum of 1/3 the ARM core clock.
For details, see the Emulation TRM.
Figure 4-3 shows the MPU subsystem clocking scheme.
Figure 4-3. MPU Subsystem Clocking Scheme
For more information about MPU_DPLL, see Section 3.5.3.3.3 , DPLLs, in Chapter 3 , Power, Reset, and
Clock Managment.
Table 4-1 summarizes the clocks generated in the MPU subsystem by the MPU DPLL and clock
generator.
679 SWPU177N – December 2009 – Revised November 2010 MPU Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated