Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
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Table 19-43. RHR_REG
Address Offset 0x000
Physical Address
See Table 19-39 to Table 19-40
Description Receive holding register
The receiver section consists of the receiver holding register ( RHR_REG ) and the receiver shift register. The
RHR_REG is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is
converted to parallel data and moved to the RHR_REG . If the FIFO is disabled, location zero of the FIFO is
used to store the single data character.
RHR_REG must be read only after it is verified that the receive FIFO is not empty; this is done by reading the
LSR_REG [0] RX_FIFO_E bit.
Note: If an overflow occurs the data in the RHR_REG is not overwritten.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RHR
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0. R 0x000000
7:0 RHR Receive holding register R 0x-
Table 19-44. Register Call Summary for Register RHR_REG
UART/IrDA/CIR Functional Description
• FIFO Management : [0] [1]
• Register Access Modes : [2]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [3] [4]
• UART Mode : [5] [6] [7] [8] [9] [10] [11]
• IrDA Mode (UART3 Only) : [12] [13] [14]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [15] [16]
• UART/IrDA/CIR Register Description : [17] [18] [19] [20] [21] [22] [23]
Table 19-45. THR_REG
Address Offset 0x000
Physical Address
See Table 19-39 to Table 19-40
Description Transmit holding register
The transmitter section consists of the transmit holding register ( THR_REG ) and the transmit shift register. The
transmit holding register is a 64-byte FIFO. The MPU writes data to the THR_REG . The data is placed in the
transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location zero of the
FIFO is used to store the data.
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED THR
Bits Field Name Description Type Reset
31:8 Reserved Write has no functional effect. W 0x000000
7:0 THR Transmit holding register W 0x-
2932 UART/IrDA/CIR SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated