Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
19.6.3 UART/IrDA/CIR Register Description
Table 19-41. DLL_REG
Address Offset 0x000
Physical Address
See Table 19-39 to Table 19-40
Description Divisor latches low
This register, with DLH_REG , stores the 14-bit divisor for generation of the baud clock in the baud rate
generator. DLH_REG stores the most-significant part of the divisor. DLL_REG stores the least-significant part of
the divisor.
Note: DLL_REG and DLH_REG can be written to only before sleep mode is enabled (before IER_REG [4] is
set).
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLOCK_LSB
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0. R 0x000000
7:0 CLOCK_LSB Stores the 8-bit LSB divisor value RW 0x00
Table 19-42. Register Call Summary for Register DLL_REG
UART/IrDA/CIR Functional Description
• FIFO DMA Mode Operation : [0]
• Register Access Modes : [1] [2] [3] [4]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
• UART Mode : [17] [18] [19]
• IrDA Mode (UART3 Only) : [20]
• UART Mode Power Management : [21] [22]
UART/IrDA/CIR Basic Programming Model
• Quick start : [23] [24] [25] [26] [27]
• SIR Mode : [28] [29] [30] [31] [32] [33] [34] [35]
• MIR Mode : [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [48] [49]
• UART/IrDA/CIR Register Description : [50] [51] [52] [53] [54] [55] [56] [57] [58]
2931 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
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