Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
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Table 19-78. Register Call Summary for Register TLR_REG
UART/IrDA/CIR Functional Description
• FIFO Management : [0]
• FIFO Trigger : [1] [2] [3] [4]
• FIFO Interrupt Mode : [5] [6]
• FIFO DMA Mode Operation : [7] [8] [9] [10]
• Register Access Modes : [11] [12] [13] [14] [15] [16]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33]
[34]
UART/IrDA/CIR Basic Programming Model
• Quick start : [35] [36] [37] [38] [39] [40]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [41] [42]
• UART/IrDA/CIR Register Description : [43] [44] [45] [46] [47]
Table 19-79. MDR1_REG
Address Offset 0x020
Physical Address
See Table 19-39 to Table 19-40
Description Mode definition register 1.
The mode of operation can be programmed by writing to MDR1_REG [2:0]; therefore, the MDR1_REG must be
programmed on startup after configuration of the configuration registers ( DLL_REG , DLH_REG , LCR_REG ). The
value of MDR1_REG [2:0] must not be changed again during normal operation.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
SCT
SET_TXIR IR_SLEEP
SIP_MODE
MODE_SELECT
FRAME_END_MODE
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0. R 0x000000
7 FRAME_END_ IrDA mode only RW 0
MODE
0x0: Frame-length method
0x1: Set EOT bit method
6 SIP_MODE MIR/FIR modes only. IrDA only. RW 0
0x0: Manual SIP mode: SIP is generated with the
control of
ACREG_REG [3].
0x1: Automatic SIP mode: SIP is generated after each
transmission.
5 SCT Store and control the transmission. RW 0
0x0: Starts the infrared transmission when a value is
written to
THR_REG
0x1: Starts the infrared transmission with the control of
ACREG_REG [2]
Note: Before starting any transmission, there must be no
reception ongoing.
4 SET_TXIR Used to configure the infrared transceiver. IrDA only. RW 0
0x0: a) No action if MDR2[7]=0
b) TXIR pin output is forced low if MDR2[7]=1
2952 UART/IrDA/CIR SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated