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UART/IrDA/CIR Functional Description
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19.4.2.1 FIFO Trigger
19.4.2.1.1 Transmit FIFO Trigger
summarizes the transmit FIFO trigger level settings.
Table 19-19. TX FIFO Trigger Level Setting Summary
[3:0]
TX FIFO Trigger Level
0
= 0x0
Defined by the UARTi.
[5:4] TX_FIFO_TRIG field (8,16, 32, or 56
spaces)
0
≠
0x0
Defined by the UARTi.
[3:0] TX_FIFO_TRIG_DMA field (from 4 to 60
spaces with a granularity of 4 spaces)
1
Value
Defined by the concatenated value of TX_FIFO_TRIG_DMA and
TX_FIFO_TRIG (from 1 to 63 spaces with a granularity of 1 space)
Note: The combination of TX_FIFO_TRIG_DMA = 0x0 and TX_FIFO_TRIG =
0x0 (all zeros) is not supported (minimum of one space required). All zeros
result in unpredictable behavior.
19.4.2.1.2 Receive FIFO Trigger
summarizes the receive FIFO trigger level settings.
Table 19-20. RX FIFO Trigger Level Setting Summary
[7:4]
RX FIFO Trigger Level
0
= 0x0
Defined by the UARTi.
[7:6] RX_FIFO_TRIG field (8,16, 56, or 60
characters)
0
≠
0x0
Defined by UARTi.
[7:4] RX_FIFO_TRIG_DMA field (from 4 to 60
characters with a granularity of 4 characters)
1
Value
Defined by the concatenated value of RX_FIFO_TRIG_DMA and
RX_FIFO_TRIG (from 1 to 63 characters with a granularity of 1 character).
Note: The combination of RX_FIFO_TRIG_DMA = 0x0 and RX_FIFO_TRIG =
0x0 (all zeros) is not supported (minimum 1 character required). All zeros result
in unpredictable behavior.
The receive threshold is programmed using the UARTi.
[7:4] RX_FIFO_TRIG_START and
[3:0] RX_FIFO_TRIG_HALT fields.
•
Trigger levels from 0 to 60 bytes are available with a granularity of four. (Trigger level = 4 x [4-bit
register value])
•
To ensure correct device operation, ensure that RX_FIFO_TRIG_HALT > RX_FIFO_TRIG when
auto-RTS is enabled.
Delay = [4 + 16 × (1 + CHAR_ Stop – 0.5)] × Bau 4 × FCLK
NOTE:
The RTS signal is deasserted after the UART module receives the data over
RX_FIFO_TRIG_HALT. Delay means how long the UART module takes to deassert the RTS
signal after reaching RX_FIFO_TRIG_HALT.
•
In the FIFO interrupt mode with flow control, ensure that the trigger level to HALT transmission is
greater than or equal to the receive FIFO trigger level (either the UARTi.
RX_FIFO_TRIG_START field or the UARTi.
[7:6] RX_FIFO_TRIG field); otherwise, FIFO
operation stalls. In the FIFO DMA mode with flow control, this concept does not exist, because a DMA
request is sent when a byte is received.
19.4.2.2 FIFO Interrupt Mode
In the FIFO interrupt mode (the FIFO control register UARTi.
[0] FIFO_EN bit is set to 1 and
2892
UART/IrDA/CIR
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
