Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
Bits Field Name Description Type Reset
If this bit is set during an MIR/FIR transmission, the SIP is sent
at the end of it. This bit is automatically cleared at the end of
the SIP transmission.
0x0: No action
0x1: Send SIP pulse.
2 SCTX_EN Store and control TX start. When MDR1_REG [5] = 1 and the RW 0
MPU writes 1 to this bit, the TX state-machine starts frame
transmission. This bit is self-clearing.
1 ABORT_EN Frame abort. The MPU can intentionally abort transmission of RW 0
a frame by writing 1 to this bit. Neither the end flag nor the
CRC bits are appended to the frame.
0 EOT_EN EOT (end-of-transmission) bit. The MPU writes 1 to this bit RW 0
just before it writes the last byte to the TX FIFO in the set-EOT
bit frame-closing method. This bit is automatically cleared
when the MPU writes to the
THR_REG (TX FIFO).
Table 19-104. Register Call Summary for Register ACREG_REG
UART/IrDA/CIR Environment
• UART3 Interface Description : [0]
• IrDA Protocol and Data Format : [1] [2] [3] [4]
• CIR Interface Description : [5]
UART/IrDA/CIR Functional Description
• Register Access Modes : [6] [7]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [8] [9] [10] [11]
• IrDA Mode (UART3 Only) : [12] [13] [14] [15] [16] [17] [18]
• CIR Mode (UART3 Only) : [19] [20]
UART/IrDA/CIR Basic Programming Model
• SIR Mode : [21]
• MIR Mode : [22]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [23] [24]
• UART/IrDA/CIR Register Description : [25] [26]
Table 19-105. SCR_REG
Address Offset 0x040
Physical Address
See Table 19-39 to Table 19-40
Description Supplementary control register
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
DMA_MODE_2
DMA_MODE_CTL
TX_TRIG_GRANU1
RX_TRIG_GRANU1
TX_EMPTY_CTL_IT
RX_CTS_DSR_WAKE_UP_ENABLE
2963 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated