Texas Instruments OMAP36 Series, Technical Reference Manual

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xBOF BOF A C CRC EOF
FIFO Data
I
N * 8 bits
8 bits 8 bits 8 bits
M * 8 bits
2 * 8
bits
8 bits
uart-006
Public Version
UART/IrDA/CIR Environment
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The SIR receive state-machine recovers the receive clock, removes the start flags and any transparency
from the incoming data, and determines the frame boundary with reception of the stop flag. The SIR
state-machine also checks for errors, such as a frame abort (0x7D character followed immediately by a
0xC1 stop flag without transparency), a CRC error, and a frame-length error. At the end of a frame
reception, the MPU reads the line status register (UART3.
LSR_REG ) to find possible errors of the
received frame.
NOTE: Data can be transferred both ways by the module, but when the device is transmitting, the
IR RX circuitry is automatically disabled by hardware. See the UART3. ACREG_REG [5]
DIS_IR_RX bit description. This applies to all three modes: SIR, MIR, and FIR.
Infrared output in SIR mode can be either 1.6-µs or 3/16th encoding, selected by the
UART3.
ACREG_REG [7] PULSE_TYPE bit. In 1.6-µs encoding, the infrared pulse width is 1.6 εs; and in
3/16th encoding, the infrared pulse width is 3/16th of a bit duration (1/baud rate).
The transmitting device must send at least two start flags at the start of each frame for back-to-back
frames.
NOTE: Reception supports variable-length stop-bits.
19.2.5.2.1.1 Frame Format
Figure 19-6 shows the IrDA SIR frame format.
Figure 19-6. IrDA SIR Frame Format
The CRC is applied on the address (A), control (C), and information (I) bytes.
NOTE: The two words of CRC are written to the FIFO in reception.
19.2.5.2.1.2 Asynchronous Transparency
Before transmitting a byte, the UART IrDA controller examines each byte of the payload and the CRC field
(between BOF and EOF). For each byte equal to 0xC0 (BOF), 0xC1 (EOF), or 0x7D (control escape), the
controller performs certain tasks:
• In transmission:
– Inserts a control escape (CE) byte preceding the byte
– Complements bit 5 of the byte (that is, exclusive ORs the byte with 0x20)
The byte sent for the CRC computation is the initial byte written in the TX FIFO (before the XOR with
0x20).
• In reception:
For the A, C, I, CRC field:
– Compares the byte with the CE byte; if they are not equal, sends the byte to the CRC detector and
2876 UART/IrDA/CIR SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated