Public Version
UART/IrDA/CIR Functional Description
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Table 19-34. IrDA Baud Rates Settings (continued)
Baud Rate
IR Mode
Baud Multiple
Encoding
DLH, DLL
Actual Baud
Error (%)$
Source Jitter
Pulse duration
(Decimal)
Rate
(%)
0.576 Mbps
MIR
41x/42x
1/4
2
0.5756 Mbps
(1)
0
+1.63/- 0.80
416 ns
1.152 Mbps
MIR
41x/42x
1/4
1
1.1511 Mbps
(1)
0
+1.63/- 0.80
208 ns
4 Mbps
FIR
6x
4 PPM
-
4 Mbps
0
0
125 ns
(1)
Average value
NOTE:
Baud rate error and source jitter table values do not include 48-MHz reference clock error
and jitter.
19.4.4.2.3 IrDA Data Formatting
The methods described in this section apply to all IrDA modes (SIR, MIR, and FIR).
19.4.4.2.3.1 IRRX Polarity Control
The UART3.
[6] IRRXINVERT bit provides the flexibility to invert the uart3_rx_irrx pin in the
UART module to ensure that the protocol at the output of the transceiver module has the same polarity at
module level. By default, the uart3_rx_irrx pin is inverted because most transceivers invert the IR receive
pin.
19.4.4.2.3.2 IrDA Reception Control
Data can be transferred both ways by the module, but when the device is transmitting, the IR RX circuitry
is automatically disabled by hardware.
Operation of the uart3_rx_irrx input can be disabled by the UART3.
[5] DIS_IR_RX bit.
19.4.4.2.3.3 IR Address Checking
In all IR modes, when address checking is enabled, only frames intended for the device are written to the
RX FIFO. This restriction avoids receiving frames not meant for this device in a multipoint infrared
environment. It is possible to program two frame addresses that the UART IrDA receives with the
UART3.
[7:0] XON_WORD1 and UART3.
[7:0] XON_WORD2
fields.
Setting the
[0] bit to 1 selects address1 checking. Setting the
[1] bit to 1 selects
address2 checking. Setting the
[1:0] bit to 0 disables all address checking operations. If both
bits are set, the incoming frame is checked for both private and public addresses.
If address checking is disabled, all received frames write to the reception FIFO.
19.4.4.2.3.4 Frame Closing
A transmission frame can be correctly terminated in two ways:
•
Frame-length method: The frame-length method is selected by setting the UART3.
[7]
FRAME_END_MODE bit to 0. The MPU writes the frame-length value to the UART3.
and
UART3.
registers. The device automatically attaches end flags to the frame when the
number of bytes transmitted equals the frame-length value.
•
Set-EOT bit method: The set-EOT bit method is selected by setting the FRAME_END_MODE bit to 1.
The MPU writes 1 to the UART3.
[0] EOT bit just before it writes the last byte to the TX
FIFO. When the MPU writes the last byte to the TX FIFO, the device internally sets the tag bit for that
character in the TX FIFO. As the TX state-machine reads data from the TX FIFO, it uses this tag-bit
information to attach end flags and correctly terminate the frame.
2912
UART/IrDA/CIR
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated