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UART/IrDA/CIR Register Manual
Table 19-82. Register Call Summary for Register MDR2_REG (continued)
UART/IrDA/CIR Register Manual
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UART/IrDA/CIR Register Summary
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UART/IrDA/CIR Register Description
:
Table 19-83. TXFLL_REG
Address Offset
0x028
Physical Address
See
to
Description
Transmit frame length register low
IrDA modes only
The registers
and
hold the 13-bit transmit frame length (expressed in bytes).
holds the LSBs and
holds the MSBs. The frame length value is used if the frame
length method of frame closing is used.
Type
W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
TXFLL
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Write has no functional effect.
W
0x000000
7:0
TXFLL
LSB register used to specify the frame length
W
0x00
Table 19-84. Register Call Summary for Register TXFLL_REG
UART/IrDA/CIR Functional Description
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•
UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
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:
UART/IrDA/CIR Basic Programming Model
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:
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:
UART/IrDA/CIR Register Manual
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UART/IrDA/CIR Register Summary
•
UART/IrDA/CIR Register Description
:
Table 19-85. SFLSR_REG
Address Offset
0x028
Physical Address
See
to
Description
Status FIFO line status register
IrDA modes only
Reading this register effectively reads frame status information from the status FIFO (this register does not
physically exist). Reading this register increments the status FIFO read pointer (
and
must be read first).
Type
R
2955
SWPU177N – December 2009 – Revised November 2010
UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated