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UART/IrDA/CIR Register Manual
Bits
Field Name
Description
Type
Reset
0x0:
Disables the RHR interrupt
0x1:
Enables the RHR interrupt
IrDA Bit Field Details
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
EOF_IT
THR_IT
RHR_IT
LINE_STS_IT
TX_STATUS_IT
RX_OVERRUN_IT
LAST_RX_BYTE_IT
STS_FIFO_TRIG_IT
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Read returns 0. Write has no functional effect.
RW
0x000000
7
EOF_IT
0x0:
Disables the received EOF interrupt
0x1:
Enables the received EOF interrupt
6
LINE_STS_IT_I
RW
0
0x0:
Disables the receiver line status interrupt
0x1:
Enables the receiver line status interrupt
5
TX_STATUS_IT
TX_STATUS_IT interrupt reflects two possible conditions.
RW
0
The
[0] must be read to determine the status
in the event of this interrupt.
0x0:
Disables the TX status interrupt
0x1:
Enables the TX status interrupt
4
STS_FIFO_ TRIG_IT
RW
0
0x0:
Disables status FIFO trigger level interrupt
0x1:
Enables status FIFO trigger level interrupt.
3
RX_OVERRUN_ IT
RW
0
0x0:
Disables the RX overrun interrupt
0x1:
Enables the RX overrun interrupt
2
LAST_RX_ BYTE_IT
RW
0
0x0:
Disables the last byte of frame in RX FIFO
interrupt
0x1:
Enables the last byte of frame in RX FIFO
interrupt
1
THR_IT
RW
0
0x0:
Disables the THR interrupt
0x1:
Enables the THR interrupt
0
RHR_IT
RW
0
0x0:
Disables the RHR interrupt
0x1:
Enables the RHR interrupt
2935
SWPU177N – December 2009 – Revised November 2010
UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated