Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
Bits Field Name Description Type Reset
0x1: TXIR pin output is forced high (not dependant on
value of MDR2[7]).
3 IR_SLEEP RW 0
0x0: IrDA/CIR sleep mode disabled
0x1: IrDA/CIR sleep mode enabled
2:0 MODE_SELECT UART-IrDA-CIR mode selection RW 0x7
0x0: UART 16x mode
0x1: SIR mode
0x2: UART 16x auto-baud
0x3: UART 13x mode
0x4: MIR mode
0x5: FIR mode
0x6: CIR mode
0x7: Disable (default state)
Table 19-80. Register Call Summary for Register MDR1_REG
UART/IrDA/CIR Overview
• UART/IrDA/CIR Overview : [0]
UART/IrDA/CIR Environment
• UART Protocol and Data Format : [1]
UART/IrDA/CIR Functional Description
• Register Access Modes : [2] [3] [4] [5] [6] [7]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]
[26]
• UART Mode : [27] [28] [29]
• IrDA Mode (UART3 Only) : [30] [31] [32] [33] [34] [35]
• CIR Mode (UART3 Only) : [36]
UART/IrDA/CIR Basic Programming Model
• Quick start : [37] [38] [39]
• SIR Mode : [40] [41] [42] [43] [44]
• MIR Mode : [45] [46] [47] [48] [49] [50] [51] [52]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [53] [54]
• UART/IrDA/CIR Register Description : [55] [56] [57] [58] [59]
Table 19-81. MDR2_REG
Address Offset 0x024
Physical Address
See Table 19-39 to Table 19-40
Description Mode definition register 2
IR-IrDA and IR-CIR modes only
MDR2_REG [0] describes the status of the interrupt in IIR_REG [5]. The IRTX_UNDERRUN bit must be read after
an IIR_REG [5] TX_STATUS_IT interrupt occurs. The bits [2:1] of this register set the trigger level for the frame
status FIFO (8 entries) and must be programmed before the mode is programmed in MDR1_REG [2:0].
Type RW
2953 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
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