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UART/IrDA/CIR Functional Description
Table 19-36. Duty Cycle
Duty Cycle (High Level)
00
1/4
01
1/3
10
5/12
11
1/2
19.4.4.3.2 CIR Data Formatting
The methods described in this section apply to all CIR modes.
19.4.4.3.2.1 IRRX Polarity Control
The IRRX polarity control for the CIR mode has the same functionality as that for the IrDA mode (see
, IRRX Polarity Control).
19.4.4.3.2.2 CIR Transmission
In transmission, the MPU software must exercise an element of real-time control to transmit data packets,
each of which must be emitted at a constant delay from the start bits of each individual packet. Thus,
when sending a series of packets, the packet-to-packet delay must respect a specific delay. Two methods
can be used to control this delay:
•
Filling the TX FIFO with a number of zero bits that are transmitted with a t period
•
Using an external system timer to control the delay either between each start-of-frame or between the
end of a frame and the start of the next one. This can be performed by:
–
Controlling the start of the frame using the UART3.
[5] SCT bit and
[2] SCTX_EN bit, depending on the timer status
–
Using the UART3.
[5] TX_STATUS_IT interrupt to preload the next frame in the TX FIFO
and to control the start of the timer (in case of control delay between the end of a frame and the
start of the next frame).
19.4.4.3.2.3 CIR Reception
There are two methods of stopping reception:
•
The MPU can disable the reception by setting the UART3.
[5] DIS_IR_RX bit to 1 when it
detects that the reception is complete because of the large number of 0s received. To receive a new
frame, the DIS_IR_RX bit must be set to 0.
•
The reception stops automatically, depending on the value set in the BOF-length register (the
UART3.
[7:0] EBLR field). If the value set in the UART3.
[7:0] EBLR field is
different from 0, this feature is enabled and counts the number of bits received at 0.
When the counter achieves the value defined in the
register, the reception automatically stops
and the UART3.
[2] RX_STOP_IT bit is set. When 1 is detected on the uart3.rx_irrx pin, the
reception is automatically enabled.
CAUTION
If the UART3.
[2] RX_STOP_IT interrupt occurs before a byte
boundary, the remaining bits of the last byte are filled with zeros and then
passed into the RX FIFO.
2917
SWPU177N – December 2009 – Revised November 2010
UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated
