Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
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Table 19-52. Register Call Summary for Register FCR_REG
UART/IrDA/CIR Functional Description
• FIFO Management : [0]
• FIFO Trigger : [1] [2] [3]
• FIFO Interrupt Mode : [4] [5] [6]
• FIFO Polled Mode Operation : [7]
• FIFO DMA Mode Operation : [8] [9] [10] [11]
• Register Access Modes : [12] [13]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [14] [15] [16] [17] [18] [19]
UART/IrDA/CIR Basic Programming Model
• Quick start : [20] [21] [22] [23] [24] [25] [26] [27]
• MIR Mode : [28] [29] [30] [31] [32] [33]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [34] [35]
• UART/IrDA/CIR Register Description : [36] [37] [38] [39] [40]
Table 19-53. IIR_REG
Address Offset 0x008
Physical Address
See Table 19-39 to Table 19-40
Description Interrupt Identification register
The IIR_REG is a read-only register that provides the source of the interrupt in a prioritized manner.
Note: An interrupt source can be flagged only if enabled in the IER_REG register.
Type R
UART Bit Field Details
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IT_TYPE
IT_PENDING
FCR_MIRROR
Bits Field Name Description Type Reset
15:8 Reserved Read returns 0x00. R 0x00
7:6 FCR_MIRROR Mirror the contents of FCR_REG [0] on both bits. R 0x0
5:1 IT_TYPE Seven possible interrupts in UART mode; other R 0x00
combinations never occur:
0x0: Modem interrupt. Priority = 4
0x1: THR interrupt. Priority = 3
0x2: RHR interrupt. Priority = 2
0x3: Receiver line status error. Priority = 1
0x6: Rx timeout. Priority = 2
0x8: Xoff/special character. Priority = 5
0x10: CTS, RTS change state from active (low) to
inactive (high). Priority = 6
0 IT_PENDING 0x0: An interrupt is pending. R 1
0x1: No interrupt is pending.
2938 UART/IrDA/CIR SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated