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UART/IrDA/CIR Register Manual
Bits
Field Name
Description
Type
Reset
0x1:
Auto-CTS flow control is enabled; transmission is
halted when the nCTS pin is high (inactive).
6
AUTO_RTS_EN
Auto-RTS enable bit (UART mode only)
RW
0
0x0:
Normal operation
0x1:
Auto-RTS flow control is enabled; nRTS pin goes
high (inactive) when the receiver FIFO HALT
trigger level,
[3:0], is reached and goes
low (active) when the receiver FIFO RESTORE
transmission trigger level is reached.
5
SPEC_CHAR
(UART mode only) Special character detect
RW
0
0x0:
Normal operation
0x1:
Special character detect enable. Received data is
compared with XOFF2 data. If a match occurs, the
received data is transferred to RX FIFO and
bit 4 is set to 1 to indicate that a special
character was detected.
4
ENHANCED_EN
Enhanced functions write enable bit
RW
0
0x0:
Disables writing to
bits [7:4],
bits [5:4], and
bits [7:5]
0x1:
Enables writing to
bits [7:4],
bits [5:4], and
bits [7:5]
3:0
SW_FLOW_
Combinations of software flow control can be selected by
RW
0x0
CONTROL
programming bit [3:0].
See
. In IrDA mode, bits [1:0] select IR
address to check. See
, IR Address
Checking.
Table 19-56. Register Call Summary for Register EFR_REG
UART/IrDA/CIR Environment
•
:
UART/IrDA/CIR Functional Description
•
[3] [4] [5] [6] [7] [8] [9] [10]
•
UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
•
•
:
•
UART/IrDA/CIR Basic Programming Model
•
:
[27] [28] [29] [30] [31] [32] [33] [34] [35] [36]
•
Hardware and Software Flow Control Configuration
:
[37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52]
•
:
•
:
UART/IrDA/CIR Register Manual
•
UART/IrDA/CIR Register Summary
•
UART/IrDA/CIR Register Description
:
[65] [66] [67] [68] [69] [70] [71] [72]
2941
SWPU177N – December 2009 – Revised November 2010
UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated