Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 2940 / 3738

Public Version
UART/IrDA/CIR Register Manual
www.ti.com
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0x00. R 0x000000
7 EOF_IT
0x0: Received EOF interrupt inactive
0x1: Received EOF interrupt active
6 LINE_STS_IT R 0
0x0: Receiver line status interrupt inactive
0x1: Receiver line status interrupt active
5 TX_STATUS_IT R 0
0x0: TX status interrupt inactive
0x1: TX status interrupt active
4 STS_FIFO_IT R 0
0x0: Status FIFO trigger level interrupt inactive
0x1: Status FIFO trigger level interrupt active
3 RX_OE_IT R 0
0x0: RX overrun interrupt inactive
0x1: RX overrun interrupt active
2 RX_FIFO_LB_IT Receive FIFO last byte interrupt R 0
0x0: Last byte of frame in RX FIFO interrupt inactive
0x1: Last byte of frame in RX FIFO interrupt active
1 THR_IT R 0
0x0: THR interrupt inactive
0x1: THR interrupt active
0 RHR_IT R 0
0x0: RHR interrupt inactive
0x1: RHR interrupt active
Table 19-55. EFR_REG
Address Offset 0x008
Physical Address
See Table 19-39 to Table 19-40
Description Enhanced feature register
This register enables or disables enhanced features. Most enhanced functions apply only to UART modes, but
EFR_REG [4] enables write accesses to FCR_REG [5:4], the TX trigger level, which is also used in IrDA modes.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
AUTO_CTS_EN AUTO_RTS_EN
ENHANCED_EN
SW_FLOW_CONTROL
SPECIAL_CHAR_DETECT
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0. R 0x000000
7 AUTO_CTS_EN Auto-CTS enable bit (UART mode only) RW 0
0x0: Normal operation
2940 UART/IrDA/CIR SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated