Texas Instruments OMAP36 Series, Technical Reference Manual

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Programmable FIFO threshold
Receive FIFO level
Zero byte
Time
Interrupt request
Time
Interrupt request active low
Programmable flow control threshold
MPU acknowledged interrupt request
and transferred enough bytes to
recover FIFO level below
threshold
uart-024
Number
of
spaces
Programmable FIFO threshold
Transmit FIFO level
Zero byte
Time
Interrupt request
Time
Interrupt request
active low
Full level
uart-025
Public Version
www.ti.com
UART/IrDA/CIR Functional Description
relevant interrupts are enabled by the UARTi. IER_REG register), an interrupt signal informs the processor
of the status of the receiver and transmitter. These interrupts are raised when the receive/transmit FIFO
threshold (the UARTi.
TLR_REG [7:4] RX_FIFO_TRIG_DMA and UARTi. TLR_REG [3:0]
TX_FIFO_TRIG_DMA fields or the UARTi. FCR_REG [7:6] RX_FIFO_TRIG and UARTi. FCR_REG [5:4]
TX_FIFO_TRIG fields, respectively) is reached.
The interrupt signals instruct the MPU to transfer data to the destination (from the UART module in receive
mode and/or from any source to the UART FIFO in transmit mode).
When the UART flow control is enabled with the interrupt capabilities, the UART flow control FIFO
threshold (UARTi.
TCR_REG [3:0] RX_FIFO_TRIG_HALT field) must be greater than or equal to the
receive FIFO threshold.
Figure 19-23 shows the generation of the receive FIFO interrupt request.
Figure 19-23. Receive FIFO Interrupt Request Generation
In receive mode, no interrupt is generated until the receive FIFO reaches its threshold. Once low, the
interrupt can be deasserted only when the MPU has handled enough bytes to make the FIFO level below
threshold. The flow control threshold is set at a higher value than the FIFO threshold.
Figure 19-24 shows the generation of the transmit FIFO interrupt request.
Figure 19-24. Transmit FIFO Interrupt Request Generation
2893 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
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