Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
Table 19-94. Register Call Summary for Register SFREGL_REG
UART/IrDA/CIR Functional Description
• FIFO Management : [0]
• Register Access Modes : [1] [2] [3]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [4] [5] [6]
• IrDA Mode (UART3 Only) : [7]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [8] [9]
• UART/IrDA/CIR Register Description : [10] [11] [12] [13] [14]
Table 19-95. SFREGH_REG
Address Offset 0x034
Physical Address
See Table 19-39 to Table 19-40
Description Status FIFO register high
IrDA modes only
The frame lengths of received frames are written into the status FIFO. This information can be read by reading
the
SFREGL_REG and SFREGH_REG registers (these registers do not physically exist). The LSBs are read
from SFREGL_REG , and the MSBs are read from SFREGH_REG . Reading these registers does not alter the
status FIFO read pointer. These registers must be read before the pointer is incremented by reading the
SFLSR_REG .
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED SFREGH
Bits Field Name Description Type Reset
31:4 Reserved Read returns 0. R 0x0000000
3:0 SFREGH MSB part of the frame length R 0x-
Table 19-96. Register Call Summary for Register SFREGH_REG
UART/IrDA/CIR Functional Description
• FIFO Management : [0]
• Register Access Modes : [1] [2] [3]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [4] [5] [6]
• IrDA Mode (UART3 Only) : [7]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [8] [9]
• UART/IrDA/CIR Register Description : [10] [11] [12] [13] [14]
2959 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
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