Public Version
UART/IrDA/CIR Register Manual
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Table 19-91. RXFLL_REG
Address Offset
0x030
Physical Address
See
to
Description
Received frame length register low
IrDA modes only
The registers
and
hold the 12-bit receive maximum frame length.
holds
the LSBs, and
holds the MSBs. If the intended maximum receive frame length is n bytes, program
and
to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the
result of frame format with CRC and stop flag; two bytes are associated with the FIR stop flag).
Type
W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RXFLL
Bits
Field Name
Description
Type
Reset
15:8
Reserved
Write has no functional effect.
W
0x00
7:0
RXFLL
LSB register used to specify the frame length in reception
W
0x00
Table 19-92. Register Call Summary for Register RXFLL_REG
UART/IrDA/CIR Functional Description
•
•
UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
UART/IrDA/CIR Basic Programming Model
•
:
UART/IrDA/CIR Register Manual
•
UART/IrDA/CIR Register Summary
•
UART/IrDA/CIR Register Description
:
[10] [11] [12] [13] [14] [15] [16]
Table 19-93. SFREGL_REG
Address Offset
0x030
Physical Address
See
to
Description
Status FIFO register low
IrDA modes only
The frame lengths of received frames are written into the status FIFO. This information can be read by reading
the
and
registers (these registers do not physically exist). The LSBs are read
from
, and the MSBs are read from
. Reading these registers does not alter the
status FIFO read pointer. These registers must be read before the pointer is incremented by reading the
.
Type
R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SFREGL
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Read returns 0x00.
R
0x000000
7:0
SFREGL
LSB part of the frame length
R
0x-
2958
UART/IrDA/CIR
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated