Public Version
UART/IrDA/CIR Register Manual
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Table 19-97. RXFLH_REG
Address Offset
0x034
Physical Address
See
to
Description
Received frame length register high
IrDA modes only
The registers
and
hold the 12-bit receive maximum frame length.
holds
the LSBs, and
holds the MSBs. If the intended maximum receive frame length is n bytes, program
and
to be n + 3 in SIR or MIR modes and n + 6 in FIR mode (+3 and +6 are the
result of frame format with CRC and stop flag; there are two bytes associated with the FIR stop flag).
Type
W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RXFLH
Bits
Field Name
Description
Type
Reset
31:4
Reserved
Write has no functional effect.
W
0x0000000
3:0
RXFLH
MSB register used to specify the frame length in
W
0x0
reception
Table 19-98. Register Call Summary for Register RXFLH_REG
UART/IrDA/CIR Functional Description
•
•
UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
UART/IrDA/CIR Basic Programming Model
•
:
UART/IrDA/CIR Register Manual
•
UART/IrDA/CIR Register Summary
•
UART/IrDA/CIR Register Description
:
[9] [10] [11] [12] [13] [14] [15]
Table 19-99. BLR_REG
Address Offset
0x038
Physical Address
See
to
Description
BOF control register
IrDA modes only
[6] is used to select whether 0xC0 or 0xFF start patterns are to be used, when multiple start flags are
required in SIR mode. If only one start flag is required, this is always 0xC0. If n start flags are required, either
(-1) 0xC0 or (-1) 0xFF flags are sent, followed by a single 0xC0 flag (immediately preceding the first data byte).
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
XBOF_TYPE
STS_FIFO_RESET
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Read returns 0.
R
0x000000
7
STS_FIFO_ RESET
Status FIFO reset. This bit is self-clearing.
RW
0
6
XBOF_TYPE
SIR xBOF select
RW
1
2960
UART/IrDA/CIR
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated