Dragonchip DCT-EDP User Manual Download

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DCT-EDP Rev3.x User Manual

Rev1.3

Dragonchip

We bring silicon to life

DragonFLASH

1 of 27

DCT-EDP Rev3.x User Manual

Document Revision 1.3

June, 2019

Dragonchip

Summary of Contents for DCT-EDP

Page 1: ...DCT EDP Rev3 x User Manual Rev1 3 Dragonchip We bring silicon to life DragonFLASH TM 1 of 27 DCT EDP Rev3 x User Manual Document Revision 1 3 June 2019 Dragonchip ...

Page 2: ... board 8 3 3 2 DC6288EMT FT POD Rev2 0 board 8 3 4 SOFTWARE INSTALLATION 9 3 4 1 Source Code Template 10 3 4 2 Keil Project Settings 10 3 5 VIEW MEMORY CONTENT 13 3 5 1 DC6688F2SER F2STR 13 3 5 2 DC6688FLB 13 3 5 3 DC6688FLX FLE FLT FL96TE 13 3 5 4 DC6688FSB FSX FSE FST 14 3 5 5 DC6688BT 14 3 5 6 DC6288FT 14 3 6 SUPPLEMENTARY INFORMATION 14 3 6 1 Limitation 14 3 6 2 Troubeshooting 15 4 PROGRAMMING...

Page 3: ... based System on Chip SoC devices from Dragonchip 1 1 Box Contents 1 1 x DCT EDP Rev3 x 2 1 x USB cable 3 1 x 20 pin flat cable with 2x10 2 54mm connector 4 1 x 6 pin flat cable with 1x6 2 54 connector 1 2 Useful links Generally all the products information is available in our website Below are some examples 1 DC6688 1 Emulator download latest software installer Software SLP Emulator driver and So...

Page 4: ...l Rev1 3 Dragonchip We bring silicon to life DragonFLASH TM 4 of 27 2 DC6288 1 Emulator download latest software installer Software SLP Emulator driver and Source Code Template in one package and user manual 2 Technical website ...

Page 5: ...orts 1 Debug port 甲 Keil use this port for debug and programming 2 Programming port 甲 Software SLP use this port for programming Status LED Power ON Debug Programming ON OFF Button Power ON OFF device USB Port Connect to PC Rear panel Programming Port Connect to IC Debug Port Connect to IC POD Front panel Debug Programming VDD SL VSS CLK1 PROG CLK2 ...

Page 6: ... IDE the firmware will be downloaded automatically through this SL interface JTAG interface is used for debug communication There are two cases of connection depending on whether the package provided with JTAG pins or not 1 IC package with JTAG pins An example is DC6288FT32N3E In this case the debug port can connect directly to the IC 2 IC package without JTAG pins Debug P N DCT EDP Rev3 0 USB Tar...

Page 7: ...red target system They should not be connected together unless target system power supplied by VDD pin of Debug port If the power of Dragonchip IC is supplied by self powered target system VDD pin of Debug port should be left disconnected The following series are compulsory to connect VDD pin of Debug port instead of target system 1 DC6688 2 DC6388 Ribbon cable is strongly recommended for better n...

Page 8: ...6688FST and DC6688FLT for those packages without JTAG pins 3 3 2 DC6288EMT FT POD Rev2 0 board Pin Description Pin Description 1 PD3 2 PD2 3 PC3 4 IRI 5 VDD 3 3V 6 VSS 7 PC2 8 PD1 9 PC1 10 PD0 11 PC0 12 NC 13 PB7 14 PA0 15 PB6 16 PA1 17 PB5 18 PA2 19 PB4 20 PA3 21 PB3 22 PA4 23 PB2 24 PA5 25 PB1 26 PA6 27 PB0 28 PA7 29 PC5 30 PC4 31 PD6 32 PD5 33 NC 34 PD4 35 NC 36 NC 37 NC 38 NC 39 NC 40 NC ...

Page 9: ...lopers Kit recommend v9 55 It must be installed prior to the following components 2 Dragonchip DC_TOOL_Rev3 2 1 exe or higher which includes the following items a Source Code Template b Emulator Driver c Software SLP Pin Description Pin Description 1 VDD 3 3V 2 VDD 3 3V 3 VSS 4 VSS 5 PD3 6 PD2 7 PD1 8 PD0 9 PB7 10 PB6 11 PB5 12 PB4 13 PB3 14 PB2 15 PB1 16 PB0 17 PA7 18 PA6 19 PA5 20 PA4 21 PA3 22 ...

Page 10: ... project settings for using emulators User can either start the development with the generated source code template or compare the project settings with their existing Keil project 3 4 2 Keil Project Settings All necessary Keil Project Settings are listed in this section The settings might vary from one part no to another For illustration DC6688FL96E is taken as an example 1 Enter Options for Targ...

Page 11: ...Dragonchip We bring silicon to life DragonFLASH TM 11 of 27 3 Target Tab Note The Clock frequency in this page is invalid setting The setting should be selected in Programming Setting instead 4 Debug Tab Follow the settings shown below ...

Page 12: ...ramming Setting Input relevant settings for programming the emulator chip Note Program File does not need to select path Select Device and Clock Frequency Select paths of Firmware files All these files should be put in the Keil project folder Model 2 bytes configure by Custom Info file Version 2 bytes configure by Custom Info file Checksum 2 bytes generate automatically from Program file ...

Page 13: ...0 C 0x0000 Data Flash FL16B FL32B 4KB 8KB code code 0x6000 0x6000 0x6FFF 0x7FFF C 0x6FFF C 0x6000 Internal SRAM 256 bytes idata 0x00 0xFF I 0x00 Expanded SRAM 2KB xdata 0x0200 0x09FF X 0x0200 SFR 128 bytes data 0x80 0xFF D 0x80 XFR 256 bytes xdata 0x00 0xFF X 0x0000 3 5 3 DC6688FLX FLE FLT FL96TE Memory Size Memory Type Start Address End Address Example Program Data Flash FL32T FLX FL64T FLE FL96T...

Page 14: ...e Program Data Flash BT32 BT96 Up to 31KB Up to 95KB code 0x0000 0x7BFF 0x17BFF C 0x0000 Internal SRAM 256 bytes idata 0x00 0xFF I 0x00 Expanded SRAM BT32 BT96 1 5KB 3KB xdata 0x0200 0x8200 0x07FF 0x8DFF X 0x0200 X 0x8200 SFR 128 bytes data 0x80 0xFF D 0x80 XFR 256 bytes xdata 0x00 0xFF X 0x0000 3 5 6 DC6288FT Memory Size Memory Type Start Address End Address Example Program Data Flash Up to 31KB ...

Page 15: ... In one shot mode CAM 0 this bit have to reset to 0 every time before setting CAS 1 3 6 2 Troubeshooting 1 Driver Installation After installing the DragonICE driver plug the emulator to PC the driver will be installed automatically for port connected In case the PC fails to locate the driver select the driver path C WINDOWS system32 manually 2 Upgrade Keil Project When uv2 uv3 projects are closed ...

Page 16: ... required on PC to control the hardware Detail refers to section 3 4 4 2 Hardware setup Programming port provides SL interface to IC Software SLP will automatically select this programming port to download firmware to IC During debug this port is disabled automatically Warning Keil IDE must exit debugger mode before using this port via Software SLP ...

Page 17: ... 27 Detail of Software SLP operation can refer to SLP user manual 4 3 DC6688FSX The 4 pin connection to the DCT EDP s programming port from chip is shown below 3 pin connection is not supported Programming P N DCT EDP Rev3 0 USB IC SL VDD ISPSEL VSS XIN DC6688FSX PCB VDD SL VSS CLK1 DCT EDP ...

Page 18: ...tor is 12MHz 4 4 DC6688FST FLT BT To do trimming during programming stage 6 pads are required on PCB to complete this process PD2 1 VSS 2 XOUT 3 XIN 4 ISPSEL 5 PA0 6 MISO PA1 7 PA2 8 PA3 9 PA4 10 PA5 11 PA6 12 PA7 13 PC4 14 28 PC3 27 VDD 26 PC2 T2 25 PC1 REM T1 24 PC0 T0 ISPSS 23 PB7 22 PB6 T2EX 21 PB5 20 PB4 19 PB3 TXD1 18 PB2 RXD1 17 PB1 TXD0 MOSI 16 PB0 RXD0 ISPSCK 15 PC5 ...

Page 19: ...to life DragonFLASH TM 19 of 27 DC6688FL32TH6 only requires 4 pads DC6688FL32TH6 QFN16 VDD SL PD0 VSS PROG ECLK PD1 PB6 DC6688FL32TC FL32T FL64T FL96T FST BT PCB VDD SL VSS PROG CLK1 CLK2 DCT EDP VDD SL VSS ECLK DC6688FL32TH6 PCB VDD SL VSS CLK1 DCT EDP Rev3 1 or ...

Page 20: ... PB0 INTB SCL0 10 PA5 INTA TXD0 SDO PWM0 9 PA4 INTA RXD0 SDI VSS 1 PB3 INTB SL 2 PB4 INTB ECLK 3 RSTN 4 16 IRI IRTX PC1 15 VDD_IR 14 VDD 13 PB2 INTB REM PA0 INTA T2EX T24EX PA1 INTA SCK T2 PA2 INTA SCL1 T1 PA3 INTA SDA1 T0 PWM1 5 6 7 8 PB0 PB4 PB5 RST N IRI PB1 PC2 VDD PC1 VSS PB6 PRO G PC0 PA1 PD0 PD1 A B C D 1 2 3 4 Top View ...

Page 21: ...C1 REM T1 24 PC0 T0 ISPSS SCL 23 PB7 INTB SDA 22 PB6 INTB T2EX 21 PB5 INTB 20 PB4 INTB SCK 19 PB3 INTB TXD1 SDO 18 PB2 INTB RXD1 SDI 17 PB1 INTB TXD0 MOSI 16 PB0 INTB RXD0 ISPSCK 15 PC5 VSS 1 PD1 INTD ECLK 2 PD0 INTD SL 3 PROG 4 PA0 INTA 5 PA1 INTA MISO 6 PA4 INTA 7 PA5 INTA 8 PA6 INTA 9 PA7 INTA 10 20 VDD 19 PC1 INTC REM IRTX T1 T24_OUT IRI 18 PB7 INTB T0 ISPSS 17 PB6 INTB T2EX T24EX PWM1 TRIM 16...

Page 22: ...C2 T2 22 PC1 REM T1 21 PC0 T0 ISPSS SCL 20 PB7 INTB SDA 19 PB6 INTB T2EX 18 PB5 INTB 17 PB4 INTB SCK 16 PB3 INTB TXD1 SDO 15 PB2 INTB RXD1 SDI 14 PB1 INTB TXD0 MOSI 13 PB0 INTB RXD0 ISPSCK PB0 1 PB1 2 PB4 3 PB5 4 PB6 5 PC0 6 PC1 7 VDD2 8 24 PA4 23 VDD3 22 RF 21 PA3 20 RA2 19 PA1 18 Reserve 17 PROG 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 VSS RSTN PC2 IRI VDD1 VSS ECLK PD1 SL PD0 Reserve Rese...

Page 23: ... XIN SL PD0 Reserve 42 VSS 41 CC0 40 VSS 39 XTAL2 38 XTAL1 37 VDD 36 VSS 35 RF 34 VSS 33 Reserve 32 VDD 31 Reserve 30 Reserve 29 DTM1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PROG PA0 PA1 PA2 PA3 Reserve PA4 PA5 Reserve Reserve Reserve Reserve VSS DTM0 PC1 PC0 PB7 PB6 PB5 PB4 PB3 Reserve Reserve PB2 PB1 PB0 CC0 CAP VSS QFN56 Top view 1 2 3 4 5 6 7 8 9 10 ...

Page 24: ...14 PA4 T2_CC4 MCLK 13 PA3 T2_CC3 12 PA2 SCK T2 CNVSTR 11 PA1 SDA T2EX 1 2 3 4 5 6 7 8 9 10 PWM1 PC0 T24_CB PB3 T24_CA PWM0 PB4 PB5 ECLK RSTN PC3 PC2 REM PC1 VSS VDD 20 PB2 19 PB1 T1 SL 18 PB0 17 PA7 SCK T2_CC2 16 PA6 SDI T2_CC1 15 PA5 SDO T24_OUT 14 PA4 T2_CC4 MCLK 13 PA3 T2_CC3 12 PA2 SCK T2 CNVSTR 11 PA1 SDA T2EX 1 2 3 4 5 6 7 8 9 10 ECLK RSTN PC2 PC1 VSS PC0 6 7 8 9 10 VDD PA0 PA1 PA2 PA3 VSS Q...

Page 25: ...nchip We bring silicon to life DragonFLASH TM 25 of 27 ECLK RSTN PC3 PC2 PC1 VSS PC0 7 8 9 10 11 12 VDD PA0 PA1 PA2 PA3 PA4 VSS QFN24 Top view 1 2 3 4 5 6 PB1 SL PB0 PA7 PA6 PC4 PA5 18 17 16 15 14 13 24 23 22 21 20 19 PB7 PB6 PB5 PB4 PB3 PB2 ...

Page 26: ...tion Page Description Edited By Reviewed By 1 0 May 2019 All Preliminary Danny Ho Patrick Li 1 1 May 2019 5 Add section 5 for programming Danny Ho Patrick Li 2 5 Add section for pin assignment 1 2 June 2019 6 1 Add hardware setup Danny Ho Patrick Li 3 Add Debug 1 3 June 2019 All Re organize the content Added section 3 3 2 Danny Ho Patrick Li ...

Page 27: ...by Dragonchip Ltd No part of this specification may be reproduced in any form or means without the expressed written consent Dragonchip Ltd Disclaimer Dragonchip Ltd assumes no responsibility for any errors contained herein Copyright by Dragonchip Ltd All Rights Reserved Dragonchip Ltd TEL 852 2776 0111 FAX 852 2776 0996 http www dragonchip com ...

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