Public Version
UART/IrDA/CIR Register Manual
www.ti.com
Bits
Field Name
Description
Type
Reset
0x1:
Enables the receiver line status interrupt
1
THR_IT
RW
0
0x0:
Disables the THR interrupt
0x1:
Enables the THR interrupt
0
RHR_IT
RW
0
0x0:
Disables the RHR interrupt and time out
interrupt.
0x1:
Enables the RHR interrupt and time out interrupt.
Table 19-48. Register Call Summary for Register IER_REG
UART/IrDA/CIR Functional Description
•
•
•
•
UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
•
•
:
•
•
UART/IrDA/CIR Basic Programming Model
•
:
[18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
•
:
•
:
UART/IrDA/CIR Register Manual
•
UART/IrDA/CIR Register Summary
•
UART/IrDA/CIR Register Description
:
CIR Bit Field Details
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
THR_IT
RHR_IT
RESERVED
RX_STOP_IT
TX_STATUS_IT
RX_OVERRUN_IT
Bits
Field Name
Description
Type
Reset
31:6
Reserved
Read returns 0. Write has no functional effect.
RW
0x0000000
5
TX_STATUS_IT
In IR-CIR mode, contrary to the IR-IrDA mode, the
RW
0
TX_STATUS_IT has only one meaning corresponding to
the case
[0] = 0.
4
RESERVED
Not used in CIR mode
RW
0
3
RX_OVERRUN_IT
RW
0
0x0:
Disables the RX overrun interrupt
0x1:
Enables the RX overrun interrupt
2
RX_STOP_IT
RW
0
0x0:
isables the receive stop interrupt
0x1:
Enables the receive stop interrupt
1
THR_IT
RW
0
0x0:
Disables the THR interrupt
0x1:
Enables the THR interrupt
0
RHR_IT
RW
0
2934
UART/IrDA/CIR
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated