TX FIFO
1
2
4
5
6
3
7
8
10
11
12
9
13
14
16
15
16XCLK
uart3_tx_irtx
output
uart-007
Public Version
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UART/IrDA/CIR Environment
stores it in the RX FIFO
–
If the byte is equal to the CE byte, discards the CE byte
–
Complements bit 5 of the byte following the CE
–
Sends the complemented byte to the CRC detector and stores it in the RX FIFO
19.2.5.2.1.3 Abort Sequence
The transmitter can decide to prematurely close a frame. The transmitter aborts by sending the following
sequence: 0x7DC1. The abort pattern closes the frame without a CRC field or an ending flag.
The receiver treats a frame as an aborted frame when a 0x7D character followed immediately by a 0xC1
character is received without transparency.
19.2.5.2.1.4 Pulse Shaping
The SIR mode supports both the 3/16th and the 1.6-µs pulse duration methods. The
UART3.
[7] PULSE_TYPE bit selects the pulse width method in transmit mode.
19.2.5.2.1.5 Encoder
Serial data from the transmit state-machine is encoded to transmit data to the optoelectronics. While the
TX FIFO output is high, the uart3_tx_irtx line is always low, and the counter used to form a pulse on
uart3_tx_irtx is cleared continuously.
After the TX FIFO output resets to 0, uart3_tx_irtx rises on the falling edge of the 7th 16XCLK. On the
falling edge of the 10th 16XCLK pulse, uart3_tx_irtx falls, creating a three-clock-wide pulse. While the TX
FIFO output stays low, a pulse is transmitted during the 7th to the 10th clock of each 16-clock bit cycle.
shows the IrDA SIR encoding mechanism.
Figure 19-7. IrDA SIR Encoding Mechanism
19.2.5.2.1.6 Decoder
After reset, the RX FIFO input is high and the 4-bit counter is cleared. When a rising edge is detected on
RX, the RX FIFO input falls on the next rising edge of 16XCLK with sufficient setup time. The RX FIFO
input stays low for 16 cycles (16XCLK) and then returns to high as required by the IrDA specification. As
long as no pulses (rising edges) are detected on the RX, the RX FIFO input remains high.
shows the IrDA SIR decoding mechanism.
2877
SWPU177N – December 2009 – Revised November 2010
UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated
