RX buffer
max
Zero level
Programmable
threshold
32 characters
Time
Data received while DMA
operation ongoing
DMA active periods; this
does not represent the DMA
signaling.
uart-026
Programmable
threshold
TX buffer max
Zero byte
DMA active periods; this
does not represent the
DMA signaling.
Example: DMA disabled to
show the end of the
transfer
Time
56 spaces
uart-027
Public Version
www.ti.com
UART/IrDA/CIR Functional Description
Figure 19-25. Receive FIFO DMA Request Generation (32 Characters)
In receive mode, a DMA request is generated when the receive FIFO reaches its threshold level defined in
the trigger level register (UARTi.
). This request is deasserted when the number of bytes defined
by the threshold level is read by the system DMA (sDMA).
In transmit mode, a DMA request is automatically asserted when the transmit FIFO is empty. This request
is deasserted when the number of bytes defined by the number of spaces in the trigger level register
(UARTi.
) is written by the sDMA. If an insufficient number of characters is written, the DMA
request stays active.
Figure 19-26. Transmit FIFO DMA Request Generation (56 Spaces)
2895
SWPU177N – December 2009 – Revised November 2010
UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated
