Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
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Table 7-398. DSI_CLK_TIMING
Address Offset 0x0000 006C
Physical Address 0x4804 FC6C Instance DSI_PROTOCOL_ENGINE
Description CLOCK TIMING REGISTER This register controls the DSI Protocol Engine module timers. This register
should not be modified while
DSI_CTRL .IF_EN is set to 1.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DDR_CLK_PRE DDR_CLK_POST
Bits Field Name Description Type Reset
31:16 RESERVED Write 0s for future compatibility. RW 0x0000
Reads returns 0.
15:8 DDR_CLK_PRE Indicates the number of TxByteClkHS cycles between the start of the RW 0x01
DDR clock and the assertion of the data request signal. The values
from 1 to 255 are valid. The value 0 is reserved. The value is not
used if
DSI_CLK_CTRL [13] DDR_CLK_ALWAYS_ON is set to 1
since the DDR clock is always present.
7:0 DDR_CLK_POST Indicates the number of TxByteClkHS cycles after the de-assertion of RW 0x01
the data request signal and the stop of the DDR clock. The values
from 1 to 255 are valid. The value 0 is reserved. The value is not
used if
DSI_CLK_CTRL [13] DDR_CLK_ALWAYS_ON is set to 1
since the DDR clock is always present.
Table 7-399. Register Call Summary for Register DSI_CLK_TIMING
Display Subsystem Functional Description
• Timing Parameters for an LP to HS Transaction : [0]
• Timing Parameters for an HS to LP Transaction : [1]
Display Subsystem Use Cases and Tips
• Configure DSI Timing and Virtual Channels : [2]
• Configure DSI Protocol Engine : [3]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [4]
Table 7-400. DSI_TX_FIFO_VC_SIZE
Address Offset 0x0000 0070
Physical Address 0x4804 FC70 Instance DSI_PROTOCOL_ENGINE
Description Defines the corresponding memory entries allocated for each VC. The VC must be disabled to
allocate/un-allocate some entries in the TX FIFO.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED
VC3_FIFO_ADD VC2_FIFO_ADD VC1_FIFO_ADD VC0_FIFO_ADD
VC3_FIFO_SIZE VC2_FIFO_SIZE VC1_FIFO_SIZE VC0_FIFO_SIZE
Bits Field Name Description Type Reset
31:28 VC3_FIFO_SIZE Size of the FIFO allocated for VC 3. For a complete description, RW 0x0
refer to Table 7-66 .
27 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
1934 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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