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Lattice mVision AR0234 Sensor Board

User Guide

FPGA-UG-02124-1.1

February 2022

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Summary of Contents for mVision AR0234

Page 1: ...Lattice mVision AR0234 Sensor Board User Guide FPGA UG 02124 1 1 February 2022...

Page 2: ...with all faults and associated risk the responsibility entirely of the Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by Lattice hav...

Page 3: ...red Components 8 3 Headers and Jumpers 10 4 Programming the Board 11 4 1 Programming the Device 11 5 Interfaces 13 5 1 J1 Interface 13 5 2 External Power Supply Connections 13 5 3 Flash and Shutter Co...

Page 4: ...nection Detail 9 Figure 4 1 Programming Cable Setup 11 Figure 4 2 CrossLink Programming Setup 11 Figure 4 3 CrossLink Programming Status 12 Figure 4 4 ECP5 Programming Setup 12 Figure 4 5 ECP5 Program...

Page 5: ...marks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02124 1 1 5 Acronyms in This Document A list of acrony...

Page 6: ...e provides a comprehensive setup interface and flexibility to evaluate the Lattice mVision ISP solution from Lattice and full sensor features and capabilities The sensor board comes with a lens suitab...

Page 7: ...egistered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02124 1 1 7 Camera Lens and Holder Figure 1 1 Top View of Lattic...

Page 8: ...nformation herein are subject to change without notice 8 FPGA UG 02124 1 1 2 Required Components Before starting the evaluation the following items must be available and ready to use on the test bench...

Page 9: ...oduct names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02124 1 1 9 Once all required ite...

Page 10: ...eaders and jumpers as shown in Figure 1 2 Table 3 1 AR0234 Sensor Board S No Jumper Name Description 1 J7 Short 2 J8 Short Table 3 2 CrossLink VIP Input Bridge Board S No Jumper Name Description 1 J4...

Page 11: ...ftware which can be started as a standalone tool or from a Lattice Radiant Project To program the Lattice mVision AR0234 Sensor Board using the Lattice EVDK 1 Connect the LF EVDK1 EVN board to the DC...

Page 12: ...o change without notice 12 FPGA UG 02124 1 1 Figure 4 3 CrossLink Programming Status 7 Select ECP5UM for Device Family LFE5UM 85F for Device Fast Program for Operation and mVision_ISP_1080p_impl1 bit...

Page 13: ...30 J1 CLK_N CLK_P GND1 DATA3_N DATA3_P GND2 DATA1_N DATA1_P GND3 DATA0_N DATA0_P GND4 DATA2_N DATA2_P GND5 EXTCLK SDATA SCLK RESET_BAR DVDD1V8E GND6 GND7 AVDD2V8E GND8 Kyocera 24 5804 030 000 829 Figu...

Page 14: ...J3 allow external control for Shutter and Flash DVDD1V8 1 2 3 1 2 3 SHUTTER FLASH J3 J2 C1 100nF HEADER 3 HEADER 3 SHUTTER FLASH Figure 5 3 Flash and Shutter Control Connections 5 4 IR_CUT Driver Cir...

Page 15: ...d 2 Exposure to absolute maximum rating conditions for extended periods may affect reliability 6 2 DC Electrical Characteristics Table 6 2 DC Electrical Characteristics Symbol Definition Condition Min...

Page 16: ...and PIXCLK 90 MHz TA 25 C CLOAD 10 pF 2 Values in Table 6 3 are subject to change 3 The following supply rails can be connected together a VDD VDD_PHY and VDD_DATA b VDD_IO and VDDIO_PHY c VAA VAA_PHY...

Page 17: ...RT Condition tBUF 4 7 1 3 s Capacitive Load for each Bus Line Cb 400 400 pF Serial Interface Input Pin Capacitance CIN_SI 3 3 3 3 pF SDATA Max Load Capacitance CLOAD_SD 30 30 pF SDATA Pull Up Resistor...

Page 18: ...ximum tHD DAT has only to be met if the device does not stretch the LOW period tLOW of the SCLK signal 7 A Fast mode I2 C bus device can be used in a standard mode I2C bus system but the requirement t...

Page 19: ...on VAA VAA_PIX VAA_PHY power supply After 100 s turn on VDDIO power supply After 100 s turn on VDDIO_PHY 1 8 V power supply After 100 s turn on VDD VDD_PHY power supply After 100 s turn on VDD_DATA po...

Page 20: ...Hard Reset t5 1 ms 7 Internal Initialization t6 16000 EXTCLK 8 PLL Lock Time t7 1 ms Notes 1 VDD and VDD_DATA can be tied together t4 becomes 0 in this case 2 VAA VAAPIX VAA_PHY can be tied together...

Page 21: ...rademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02124 1 1 21 Table 7 2 Power down Sequence SN Definition Symbol Min Typ Max...

Page 22: ...are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to...

Page 23: ...mers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subje...

Page 24: ...r respective holders The specifications and information herein are subject to change without notice 24 FPGA UG 02124 1 1 Revision History Revision 1 1 February 2022 Section Change Summary All Minor ad...

Page 25: ...www latticesemi com...

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