timers-014
MPU watchdog timer
(WDT2)
WDT2_FCLK
WDT2_CMDRST
WDT2_IRQ
IVA2 watchdog timer
(WDT3)
WDT3_FCLK
WDT3_CMDRST
WDT3_IRQ
32 kHz
M_IRQ_36
nc
nc
L4
interconnect
32 kHz
interrupt controller
MPU subsystem
PRCM
Action: Device warm reset
L4
interconnect
MPU_WD_RST
Public Version
Watchdog Timers
www.ti.com
16.4 Watchdog Timers
16.4.1 WDTs Overview
The device includes two instances of the 32-bit WDT: WDT2 and WDT3.
shows how each
timer is connected in the device.
NOTE:
WDTi (where i is the watchdog timer instance: i = 2 or 3) stands for the following:
•
WDT2: Watchdog timer 2, also called MPU watchdog timer
•
WDT3: Watchdog timer 3, also called IVA2 watchdog timer
Each WDT is an upward counter capable of generating both a pulse on the reset pin and an interrupt to
the device system modules following an overflow condition. The MPU WDT serves resets to the PRCM
module (its interrupt outputs are unused), and the IVA2 WDT serves watchdog interrupts to the MPU (its
reset outputs are unused).
The WDTs can be accessed, loaded, and cleared by registers through the L4 interface. The MPU and
IVA2 WDTs have the 32-kHz clock for their timer clock input.
The MPU WDT directly generates a warm reset condition on overflow. The IVA2 WDT generates an MPU
interrupt condition on overflow, which can be used by the application software via the PRCM to indirectly
trigger a reset condition (that is, to the IVA2 subsystem).
The MPU WDT connects to a single target agent port on the L4 interconnect.
Table 16-56. WD Timers Default State for GP and EMU devices
Timer
Device
EMU
GP
MPU WDTIMER2
Enabled
Running
Enabled
Running
IVA2 WDTIMER3
Enabled
NOT Running
Enabled
NOT Running
Figure 16-14. WDTs Block Diagram
16.4.1.1 WDT Features
The following are the main features of the WDT controllers:
•
L4 slave interface support:
–
32-bit data bus width
2746
Timers
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
