Public Version
McSPI Functional Description
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NOTE:
Fratio = spi1_clk frequency (Fout) division ratio.
Thigh = spi1_clk High Time period.
Tlow = spi1_clk Low Time period.
T_ref = SPI1_FCLK period.
Thigh_ref = SPI1_FCLK high Time period.
Tlow_ref = SPI1_FCLK low Time period.
If CLKG = 1: Fratio = EXTCLK concatenated with CLKD + 1 as shown below:
Fratio - 1
11
10
9
8
7
6
5
4
3
2
1
0
SPI1.MCSPI_CHxCTRL[15:8] EXTCLK bit field
SPI1.MCSPI_CHxCONF[5:2] CLKD bit field
15
14
13
12
11
10
9
8
5
4
3
2
For odd ratio values, the duty cycle is calculated as below:
Duty_cycle = (1-1/Fratio)/2
shows clock granularity examples with a clock source frequency of 48 MHz.
Table 20-13. Clock Granularity Examples
EXTCLK
CLKD
CLKG
Fratio
PHA
POL
Thigh (ns)
Tlow (ns)
Tperiod
Duty
Fout
(ns)
Cycle
(MHz)
X
0
0
1
X
X
10.4
10.4
20.8
50-50
48
X
1
0
2
X
X
20.8
20.8
41.6
50-50
24
X
2
0
4
X
X
41.6
41.6
83.2
50-50
12
X
3
0
8
X
X
83.2
83.2
166.4
50-50
6
0
0
1
1
X
X
10.4
10.4
20.8
50-50
48
0
1
1
2
X
X
20.8
20.8
41.6
50-50
24
0
2
1
3
1
0
41.6
20.8
62.4
66-33
16
0
2
1
3
1
1
20.8
41.6
62.4
33-66
16
0
3
1
4
X
X
41.6
41.6
83.2
50-50
12
5
0
1
81
1
0
852.8
832
1684.8
50.6-49.4
0.592
5
7
1
88
X
X
915.2
915.2
1830.4
50-50
0.545
20.5.3 Slave Mode
To select the McSPI slave mode, set the SPIm.
[2] MS bit.
A McSPI slave device can be connected to up to four external SPI master devices but handles
transactions with one SPI master device at a time.
In slave mode, the McSPI initiates data transfer on the data lines (spim_simo and spim_somi) when it is
selected by an active control signal (spim_csx) and receives an SPI clock (spim_clk) from the external SPI
master device. Only channel 0 can be configured as a slave. In slave mode, the McSPI uses the edge of
spim_csx to detect word length. For this reason, spim_csx must become inactive between each word.
The McSPI does not support spim_csx active between SPI words. It uses the edge to detect word length.
20.5.3.1 Dedicated Resources
Only channel 0 can be enabled in slave mode. In this section registers name such as
SPI1.
stand for SPI1.MCSPI_CH0CTRL where x=0 (channel 0 control register).
shows an example of four slaves wired on a single master device.
2998
Multichannel SPI
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
