Texas Instruments OMAP36 Series, Technical Reference Manual

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McSPI Register Manual
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Table 20-40. MCSPI_CHxCTRL
Address Offset 0x34 + (0x14 * x) Index x= 0 to 3 for MCSPI1.
x= 0 to 1 for MCSPI2 and MCSPI3.
x= 0 for MCSPI4.
Physical Address 0x4809 8034 + (0x14 * x) Instance MCSPI1
0x4809 A034 + (0x14 * x) MCSPI2
0x480B 8034 + (0x14 * x) MCSPI3
0x480B A034 + (0x14 * x) MCSPI4
Description This register is dedicated to enable the channel x
Type RW
Write Latency Immediate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved EXTCLK Reserved
EN
Bits Field Name Description Type Reset
31:16 Reserved Read returns 0s. RW 0x0000
15:8 EXTCLK Clock ratio extension: This register is used to concatenate with RW 0x00
MCSPI_CHxCONF [5:2] CLKD bit field for clock ratio only when
granularity is one clock cycle ( MCSPI_CHxCONF [28] CLKG bit
set to 1). Then the max value reached is 4096 clock divider ratio.
0x0: Clock ratio is CLKD + 1
0x1: Clock ratio is CLKD + 1 + 16
0xFF: Clock ratio is CLKD + 1 + 4080
7:1 Reserved Read returns 0s. RW 0x00
0 EN Channel enable RW 0x0
0x0: Channel x is not active.
0x1: Channel x is active.
Table 20-41. Register Call Summary for Register MCSPI_CHxCTRL
McSPI Functional Description
• Master Transmit-and-Receive Mode (Full Duplex) : [0]
• Single-Channel Master Mode : [1] [2]
• Programmable SPI Clock (spim_clk) : [3]
• Dedicated Resources : [4] [5]
McSPI Basic Programming Model
• McSPI Configuration and Operations Example : [6] [7]
McSPI Register Manual
• McSPI Register Summary : [8]
• McSPI Register Description : [9]
3050 Multichannel SPI SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated