Public Version
McSPI Functional Description
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In the master receive-only mode, software must write dummy data to the
register, and only
after the TX buffer is empty (check the MCSPI_CH0STAT[2] bit in the software).. Only one dummy write is
enough to receive any number of words from the slave. Software should ensure that the
register is always full (the TXx_EMPTY bits of SPIm.
) when receiving. The content of
the
register is always loaded into the shift register when the shift register is assigned. After
writing the dummy data to the
register, the TXx_EMPTY and TXx_UNDERFLOW bits in the
SPIm.
register are never set in receive-only mode.
The SPIm.
[2] EOT bit gives the status of serialization. The RXx_FULL bits of the
SPIm.
register are set when received data is loaded from the shift register to the
corresponding
register. The SPIm.
[3] RX0_OVERFLOW bit is never set
in this mode.
20.5.2.5 Single-Channel Master Mode
When the McSPI is configured as a master device with a single enabled channel, the assertion of the
spim_csx signal can be controlled in two different ways:
•
If the
[0] SINGLE bit is set to 0, spim_csx assertion/deassertion after each SPI
word is automatically controlled by the McSPI module (see subsections of
, Master
Mode Features.
•
If the
[0] SINGLE bit and the
[20] FORCE bit are set to 1:
spim_csx assertion/deassertion is controlled by software (see
, Programming Tips
When Switching to Another Channel.
20.5.2.5.1 Programming Tips When Switching to Another Channel
When a single channel is enabled and data transfer is ongoing:
•
Wait for completion of the SPI word transfer (wait until the SPIm.
[2] EOT bit is set to
1) before disabling the current channel and enabling a different channel.
•
Disable the current channel first, and then enable the other channel.
20.5.2.5.2 Force spim_csx Mode
Continuous transfers are manually allowed by keeping the spim_csx signal active for successive SPI
words transfer. Several sequences (configuration/enable/disable of the channel) can be run without
deactivating the spim_csx line. This mode is supported by all channels and any master sequence can be
used (transmit-receive, transmit-only, receive-only).
Keeping the spim_csx active mode is supported when:
•
A single channel is used (with the SPIm.
[0] SINGLE bit set to 1).
•
Transfer parameters are loaded in the configuration register of the appropriate channel
(SPIm.
The state of the spim_csx signal is programmable.
–
Writing 1 to the SPIm.
[20] FORCE bit drives the spim_csx line high when the
SPIm.
[6] EPOL bit is set to 0. spim_csx is driven low when the
SPIm.
[6] EPOL bit is set to 1.
–
Writing 0 to the SPIm.
[20] FORCE bit drives the spim_csx line low when the
SPIm.
[6] EPOL bit is set to 0. spim_csx is driven high when the
SPIm.
[6] EPOL bit is set to 1.
•
A single channel is enabled (the SPIm.
[0] EN bit is set to 1). The first enabled
channel activates the spim_csx line.
When the channel is enabled, the spim_csx signal activates with the programmed polarity. As in the
multichannel master mode, the transfer start depends on the status of the
register (the
SPIm.
[1] TXS bit), the status of the
register (the
SPIm.
[1] RXS bit), and the defined mode (the SPIm.
[13:12] TRM
field) of the channel enabled.
2994
Multichannel SPI
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
